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How about changing the telemetry ? Did anybody of you do this? I did, but can not really say if it improved anything :cry:
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How about changing the telemetry ?
I'd not recommend doing this either, unless your mb fw has scale values deliberately set so that the CPU think it's still within the allowed power envelope, when in fact it's not (as it often was the case on some gigabyte boards).
And since we're talking about asrock, mine is set to 240 for the CPU
 

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after adjusting the first value to 262, hwinfo reports only small power deviation of like max. 1% while running CB R23. Test settings were ppt 142, tdc 95 and edc 170 (to not hit a edc limit)

question: did you set it to 240 to achieve the same result (mitigate power deviation)?
 

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did you set it to 240
Since the agesa 1.2.0.2 I have it set to auto, but previously I had to adjust it to 220-225 to reach "recommended" 100 +/- 5% (see TheStilt's post) power reporting deviation in Hwinfo64 while running CBR23 MC.
It can't be 1% max. Perhaps you've mixed it up with something else. Also, do note bolded parts.

Not correct
He was talking about 5900/5950 downbins having one ccd disabled.
 

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Since the agesa 1.2.0.2 it have it set to auto, but previously I had to adjust it to 220-225 to reach "recommended" 100 +/- 5% (see TheStilt's post) power reporting deviation in Hwinfo64 while running CBR23 MC.
It can't be 1% max. Perhaps you've mixed it up with something else.
1% +/- from 100% ;) sorry for being unclear about this
 

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I installed that WHEA Error Suppressor service and I am very pleased with it. I had only issues with the error id #19 and now that those errors are no longer being logged in Event Viewer my system behaves much better and my benchmark scores have improved due to the overhead that was eliminated by stopping the event logging. I hope AMD fixes that mess, but this makes owning a Ryzen 9 CPU a lot less unpleasant than it was the day before. It's nice being able to run my FCLK above 1900 without those stupid warning logs being generated by in excessive volume.

The socket lid can be modified so the CPU dies will be the highest part. The socket lid is also removable, so you can modify a spare, if you have access to one, without mangling the original, should you need to restore the board to like-new condition.

LGA does have better electrical and mechanical properties, and AMD is finally switching to it on their consumer parts with AM5.
If the actual hardware under the plastic cover is lower than the top of the die that would definitely be a good solution. This is the first AMD CPU that I have owned since the original Athlon CPUs so there is a lot about the hardware I know nothing about and having to start from scratch on learning.
Look at it as a problem with the cold plate and not with the mounting?
While I think the mounting mechanism is pretty chintzy, a cold plate that fit the die instead of a random-sized chunk of metal that didn't get the amount of thought it deserved would be a reasonable solution.
Wow, I would not have expected that, really find it difficult to believe thats the case (not doubting your info) as with all the automation in fabrication etc
I also find it hard to believe. It could be, but I am going to have to find out for myself whether I agree with that assessment. When Intel went back to solder there were (and still are) lots of people saying it is not worth the effort to delid. And, that may be true for people that run stock or modest overclocks, but I have found it to be absolutely worth the effort. So much so that I won't even bother installing one without delidding it first. The difference is not as incredible as it was with the older CPUs that used a thermal compound, but still enough improvement with more severe levels of overclocking to be worth doing. That extra 6°C to 10°C reduction in load temperatures (which I have seen with all soldered Intel CPUs) can easily mean a lot when you are pushing very high clocks and voltage. If I can realize as little as a 5°C improvement in load temps on the 5950X it will be worth it. That might translate into another 100 MHz or mean the difference between finishing a Cinebench run versus a thermal shutdown. That makes it worth it.
 

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Robotic Chemist
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Wow, I would not have expected that, really find it difficult to believe thats the case (not doubting your info) as with all the automation in fabrication etc
It isn't that they aren't nominally the same height, but they are not the same height with the same precision a single piece of silicon is. There is no reason to get the heights matched with 100s of nanometers accuracy because the indium solder is much thicker than that (~500000 nm) and it would be expensive to get it that precise. Even getting them within a micrometer or two would be very expensive and is unimportant given the stock packaging. What about the automation would control this height with such precision? Just the solder balls and how they melt isn't that reproducible.

It is MUCH easier to get something very flat than to put two things down and have them at the same height.

If I can realize as little as a 5°C improvement in load temps on the 5950X it will be worth it.
It might be worth it to you then, you are a pretty extreme example. :)
Here is an example on a 3000 series, which is very similar to the 5000 series as far as the mounting of the chiplets and the IHS. I am having trouble finding an example with two chiplets or the 5000 series. :oops:

He was able to see an improvement, but not a very significant one (just over 4°C) even compared to soldered single die CPUs.
 

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Hmm what changed from novemeber? Did they do a "silent" revision? Did they have yield issues and changed the binning criteria (was it okay for this sensor to be defect in november?) ? Would be interesting to confirm if all early chips don't get whea 19s.
I'll try to write in short cutted sentences, it will be a long post

AMD didn't have much stock, generally 2nd & 3rd batch came late
First day Germany alone, sold around 4000+ Units. Mindfactory covered around 2500.
Only AMD Partners where allowed to sell them, soo Austria had close to Zero. Vienna metropolis had around 50 (embarrassing a bit)
There was pressure in the Server Segment too, soo most of it was a Dual CCD fabrication only - like 1devomer once mentioned.
Any sample that didn't pass Energy Efficiency was pushed to consumer 5950X and FW cut down
EE binning & Freq binning are two opposite things - both can OC very well.

2nd Batch came around February, but also was mostly first batch
Later assembly was split in couple more locations including Europe (Germany) to bypass SARS-CoV-2 lockdowns
What mainstream got later, was end March/April ~ when freight started to ship out from Taiwan. EU transports where locked fully

Binning criteria changes i feel happened, but they change it often.
There where couple of Bronze Rated (insufficient 1usmus defined rating) 5950X and actually a higher range of defective 5600X & 5800X. (chance to get a good gaming unit is higher on 5900X than 5950X)
People didn't understand/know between bad V/F Curve defective, and completely unstable even at 4.6Ghz. Soo RMA numbers (if anywhere ever published) are higher than usual.

Sensor (set) is not defective, predefined range is different
All Units where made equally, hidden dLDO sensor was activated later with several DPM patches ~ hence PM_Table function/methodic was rewritten.
Plans against Spectre.V5 exploit was made, but AMD was pushed to enable experimental dLDO sensor too early.
Patches result in unstable PCH links, together with SATA & NIC dropouts.
NIC ~ problem was Realtek with experimental Firmware (dropouts) and Intel Rev_02, known since Intel Z series days (I-225V Rev.03 is rock stable)
Both should be nearly resolved , but all these patches (who created usb dropouts on some) ~ had to do with DPM patches , and often came as #19 issue
#19 issue doesn't have a direct named path, nor has it an issue name or category. Hence i tell it as "potentially bad MB link" but all are just sideproducts of the I/O Die

Most of the problems where fixed (audio, sata, nic, pcie stability)
But PSP-FW was not fully. Which to some extend is good
Remain DPM/(x)GMI balancing sensors are still buggy and CPUs do overboost (even if PCH issues are "resolved"). C6 states (DF-C_States) are completely broken even before the dLDO_Injector
(while it was usable with good powerplans)
~ now with dLDO balancer, it is a complete mess but AMD was forced to act.
OCer like 1usmus also pushed information to AMD, but got ignored. I do think many people do.
AMD appears to be still overwhelmed with the situation as 1.1.8.X till 1.2.0.3 ~ AIB's got X random amount of patches on a weekly bases ~ while Zen3D awaits & they have to focus resources on cache interleaving FW
Bugs between bioses (brands) on the same looking AGESA still differs ~ soo we are just "recovering" from the mess.
1.2.0.3C is finally ok (yet not everywhere equal), but they had to do a lot of half-hearted work ~ soo sensors report still some nonsense, tho it is still much better than being ABL Locked before the cache boost and before dLDO & PM/SMU Patch (SMU 56.34 Patch C)
This is a big success (not like Powersaving Matisse @ 1901 Bootlock), but i know the mass that still cries about it.

Suppress them, is all i can say ~ i have many reasons why it is a good thing, while being against cheaterie/trickery (although XOC is full of such ~ all about the results, nevertheless of the cost)
An unstable setup will show very clearly. If you don't have PCH errors, you don't experience DPM instability. FIT is not fully disabled in OC_Mode, they remain active & still can report nonsense
There are many stages of limiting which i wrote across couple of threads here already (core cycler, whea surpressor, X370 Taichi and any other place people criticized but quoted me about it)

Else yes, all dual CCD bugged units (6 & 8 core units only who where last minute locked) ~ do not have this balancing issue
They are slightly different in FW, but there is much more broken on them when it comes to V/F curve - than it is recommendable.
In everyone's best interest, it would be to fix them ~ gain full control of the units and for every other new batches (which are split in 1CCD manuf-mode) having the same positives of it, while fixing V/F curve of the "broken" samples
Sadly as it remains common in this industry ~ everything is under NDA. People who have it are not allowed to publish "unpraised" software and can only speak about it if they themself found new things out.
They are not allowed to quote, share or support anything AMD doesn't agree with ~ yet are treated like hungry dogs and ignored by AMD (if they report critical security issues)
Industry practice has to change but that's beside this post here :)

EDIT:
(The only reason they are different while being same from the fab ~ is that there was nothing done against this topic.
They are just last minute "newer" than anything shipped out currently)

I do think that AMD doesn't want to touch bugged samples & FW ~ if they ever find any free time these months
As sensorics change/balance would again repeat the same mess, they have been fighting with since new year till Q2
(hence overboost might never get fixed, as FIT still can catch it although 1.68v sound frightening in OC_MODE)
It's in their best interest to keep consumers happy and have no common-use issues (audio, usb, gpu) than try to fix it for us enthusiasts
Damage Control , business decision
Either we fix it, or just deal with it and suppress them (at least we can enjoy higher FCLK ~somehow~ now)
PCH Link issues from the rewrite ~ to what i can see, have been resolved finally :)
Sadly again, permanent sensorics' fix, requires Bios Engineer Tools [RSMU and Documents]
 

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If the actual hardware under the plastic cover is lower than the top of the die that would definitely be a good solution. This is the first AMD CPU that I have owned since the original Athlon CPUs so there is a lot about the hardware I know nothing about and having to start from scratch on learning.
It is.


The socket mechanism and clearances have been roughly the same since the S754 days and I ran several A64s with no lids using waterblocks and cooler bases that covered more than the entire socket, with clearance to spare. All I had to do was sand down the upper part of the CPU socket/retention mechanism. If necessary, you could probably get away with cutting the whole back portion off and rigging up some sort of shim to keep the socket cover slid into the retention position and have no part of the socket even higher than the substrate of the CPU.
 

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After testing 1T recently I tried 60-20-30-24 and then I begun getting whea 19, setting 4-20-30-24 removed them. Everything was stable with 60, but event viewer began logging. I haven't had whea 19 since agesa 1.1.0.0 in April so this was a surprise, but showed med that drvstr can be a trigger.

It would seem like 1 CCD are less prone to whea 19 at higher ram speed. All people I know with dual CCDs get whea 19 above 1900 fclk, but all I know with 1 CCD get none even at 2000 fclk.
 

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After testing 1T recently I tried 60-20-30-24 and then I begun getting whea 19, setting 4-20-30-24 removed them. Everything was stable with 60, but event viewer began logging. I haven't had whea 19 since agesa 1.1.0.0 in April so this was a surprise, but showed med that drvstr can be a trigger.

It would seem like 1 CCD are less prone to whea 19 at higher ram speed. All people I know with dual CCDs get whea 19 above 1900 fclk, but all I know with 1 CCD get none even at 2000 fclk.
I've previously mentioned this, but if someone was to accumulate data regards non whea 19 samples you will find that most of them are not using full blown boards but micro ATX boards (I've not done this but through my browsing history I do believe this to be the case)

This for me is the clearest indicator with regards to the possible causes of WHEA 19s
 

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I've previously mentioned this, but if someone was to accumulate data regards non whea 19 samples you will find that most of them are not using full blown boards but micro ATX boards (I've not done this but through my browsing history I do believe this to be the case)

This for me is the clearest indicator with regards to the possible causes of WHEA 19s
Yeah, I remember you said that. It still seems as 2 CCDs are more likely to get whea 19 when OC ram. Friend of mine got a MSI B550 Tomahawk a month ago and 5600X recently, no whea 19 running ram at 4000, but he might be lucky.
 

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This is borderlining off-topic, but maybe these whea-errors are fixed in the B2 stepping..
Either that, or its just a preparation for the soon to be released v-cache versions.

The “new” Ryzen with a Stepping B2 in circulation?

It seems that AMD has proceeded with a small update at the sole discretion of some members of its Ryzen family. Some in the small community and see a small miracle that mechanically improves the performance… We do not have too much speed.

A Stepping B2 for more homogeneity?
The Ryzen 9 5950X, Ryzen 9 5900X, Ryzen 9 5900, Ryzen 7 5800X, Ryzen 7 5800, Ryzen 5600X and the APU Ryzen 7 5700GE in traffic will arrive with a Stepping B2. If nothing has changed in AMD's communication on these CPUs, neither in those concerned with the frequencies, nor in those concerned with the TDP, it seems that this stepping brings some improvements.

Ryzen Stepping b2

It's the overclocker @KCcRtttu who was able to take account of the changes when he wanted to “secure” the 5900X he was going to sue. It can also push the 12 cores of this CPU to a frequency of 5150 MHz using liquid refrigeration. Compared to the first version of the Ryzen 9 5900X (Stepping B0 ), it was noted that at the same frequency, the new model was 9ºC cooler and consumed less than 30W.

The other note is that it can now use DDR4 up to 4100 MHz on its Asus Crosshair VIII Extreme , which was not the case at all.

What conclusion is drawn from this first return?
For the moment, we find some users doing the same. But the CPU user base with this stepping B2 is too weak to have certificates.

Over the months, it has been incoherent to note that AMD is improving its manufacturing process. But until then, many of us have also noticed that the overclocking potential of a Ryzen 5000 is very random following its lot by example. This stepping B2 could bring more maturity but for the moment of our side we have nothing to measure.

If you have recently purchased a Ryzen 5000, do not hesitate to share with us your returns on this story within our Discord server.

AMD comments to Tomshardware back from May this year: "AMD Ryzen 5000 B2 Stepping CPUs Don't Bring Any Benefits"
 

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This is borderlining off-topic, but maybe these whea-errors are fixed in the B2 stepping..
It has potential
Confirming security issues, was expected.
Unclear if they could fix everything against meltdown and spectre.v5 yet. Branch Prediction is still an attack point
But a new revision "can" fix sensorics issues. ~ potentially.
~ potentially if AMD is even aware of the root cause.

But technically they wouldn't speak untrue, on "this current update has no changes"
When they last minute patched the first batch,
They wouldn't have discovered anything new since October/November ~ or February where Mr. Hallock invested himself a bit into memOC limits
Technically speaking, 3rd public batch March/April wouldn't have anything new ~ while assembly of it likely was done February already.

But i really think, AMD has no clue or doesn't want to bother with our samples at all. In the chance to do more damage than it already was
Else they could fix it with a PSP-FW update, or more likely break all things they fixed now but this time for everybody and have PCIe instability.
Not only for a handful of people experiencing USB Dropouts
 

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Yeah, I remember you said that. It still seems as 2 CCDs are more likely to get whea 19 when OC ram. Friend of mine got a MSI B550 Tomahawk a month ago and 5600X recently, no whea 19 running ram at 4000, but he might be lucky.
He should Zentimings - Debug , screenshot it for you
Seeing the mainboard, patch version, bios update and CCD Count
 

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He should Zentimings - Debug , screenshot it for you
Seeing the mainboard, patch version, bios update and CCD Count
I can ask him to :)
 

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Overclock the World
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edit
Veii were talking about bugged "dual ccd 5600x's".. carry on then :)

Last view before the lapping
Yours linked, was the 2nd batch.
All the examples I have seen of a delidded 5950X were not good (I haven't seen many). The issue is that the chiplets are not at exactly the same height, so the advantage from delidding (very thin thermal interface material) is not there. At best the same as stock. :(
I would say, lapping makes sense ~ if you switch the cooler
Both Matisse and Vermeer's heatsinks are softer than Pinnacle Ridge's. That's mostly due to TSMC's fab change.
Else just tightening it down strongly already does let the heatspreader adjust to your cooler.

Wouldn't entirely risk delidding it, not yet at least. Zen3D likely
But lapping should help for people who push it. Well or just strongly tightening it down & then never switching the cooler
so bringing the 1,8V rail as close as possible to the said 1,8V might do the trick? mine is in between 1,808 and 1,824.
so those dpm settings COULD fix the #19 ? :unsure: or did I get this wrong ?
Both parts no.
It can help , but it is no resolve
1.8V rail push does help with higher FCLK (1.83, 1.86, 1.93v ~ keep in mind procODT scaling changes too)
But as UCLK 1:1 Push has no direct connection to #19 - the answer is no :)
 
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Robotic Chemist
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I would say, lapping makes sense ~ if you switch the cooler
Both Matisse and Vermeer's heatsinks are softer than Pinnacle Ridge's. That's mostly due to TSMC's fab change.
Else just tightening it down strongly already does let the heatspreader adjust to your cooler.
Hmm, good point, it is probably not an issue with good mounting pressure and the stock IHS. :oops:
 
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