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Now this must be a bugged out reading in hwinfo64?
It is not bugged reading but actual overboost bug
I had 55ghz once
It was fortunate that it didn't crash your PC.
Can give you an experimental old powerplan to always trigger overboost - but it breaks CPPC tags , because Windows is not buggy at all
powercfg /IMPORT "path"
with " " , without .txt
Then drop minimum processor freq to 7% or 8% , or 1% - you'll notice what works out best
But it will reboot your system because Overboost Bug is still too strong & broken. Like written in the long history post. AMD hasn't fixed this since 6-7 months
Hmm, good point, it is probably not an issue with good mounting pressure and the stock IHS. :oops:
Igorslab continued his research and figured that the IHS Alloy, has changed and is very soft.
Glove Safety glove Thumb Gesture Nail
ZEN remains to be Concave, but this has changed recently & it doesn't matter all too much anymore, since it does adapt to your cooler
I still would lap them after a cooler swap ~ as it will be uneven.
The only reason i do it, is for collecting fabrication/lab footprints. Seeing if they changed their tooling, if soldering got different, and since it was an issue
Noticed IgorsLab research later on - while he didn't lap units.
This here was too abstractly shifted - soo i had to check what is going on & found his post.
Only trophy units get lapped ~ but it wouldn't matter too much till 260W i think was it. He tested after what point thermal density is too high
Like i think @MrFox mentioned. Tho for such i'd consider a direct die bracket and likely flatten out the silicon. Like XOC guys do for their GPUs these days
 

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@Veii

Interesting information (extensive research). I assumed like most say it was IMC related. I had a 5800x that had the 1900 fclk whole. It would post at 1933/66 but WHEA city. Nothing I did seemed to make a difference. I ended up selling it to get a 5900x which runs 1900fclk no issue but 1933-2000 has WHEA. I was able to lower the amount of errors with PLL voltage but had to go really high to get it to boot almost WHEA free. Seemed to be almost normal until stress testing then WHEAs showed up. It seemed to be stable but obviously performance suffered.

So are you recommending to run WHEA suppressor? Not sure it is worth it to me for another 100-200mhz ram speed.

I would love the idea of AMD fixing this, but I doubt it because even if they figure it out they would probably just implement it in new 3D cache models or other future models. I may get a 3D cache version down the road but I am going to wait and see if they have these same issues.

Either way I am happy with a decent OC, considering 3200 being stockish and able to run 3800CL14 isnt bad. I will admit Intel has been easier to OC for me in the past but I enjoy the challenge. Not a fan of the huge silicon lottery though, such big swings are surprising.
 

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So are you recommending to run WHEA suppressor? Not sure it is worth it to me for another 100-200mhz ram speed.

I would love the idea of AMD fixing this, but I doubt it because even if they figure it out they would probably just implement it in new 3D cache models or other future models. I may get a 3D cache version down the road but I am going to wait and see if they have these same issues.
About the FCLK holes, i sadly know nothing.
I heard it, keep hearing it but can not relate even remotely
Oh also thank you~ :)

The only time i had it, was with the broken 1.1.0.0 Patch C which introduced a hardlock even 1mhz beyond 1900 FCLK. It was an ABL Hardlock in the bootloader (in the AGESA blob)
There still is a memory training issue, for anything that's not Micron Rev.E ~ where in the early days, it could need 6 manual post attempts - till it finally trained correctly.
There where bugs where the bios was not cold-booting and freezing the reboot ~ soo needed a manual 2nd reboot.
A lot of annoying bugs , but only at that SMU (56.34), i really had a bad time

Else like on Matisse, on Vermeer CsOdtDrvStr (CAD_BUS) needs to be pushed, to help against bad memory training
Matisse was 24ohm, Vermeer is 30-40ohm.
VTT line aside.

AMD will have other fun issues with stacked interleaving on 3D Cache. Maybe numa interleaving even (maybe)
But i still feel, they have soo much left to fix - they wouldn't care touching it.

The only time i do recommend to run the surpressor, is after you know your CPU is stable @ 1900 or 1866. Have your Curve Optimizer set
And also reach correct L3 cache latency in Aida64 (this means, also extend your limits slightly).
4.85ghz all core reach is 10.4ns, 4.75ghz = 10.7ns, 4.65 = 10.9ns
5Ghz should be sub 9.9/9.8ns (for all you dual CCD guys)
As long as you do not hold this ~ cache is throttled and likely also package throttled.
Stability is one thing, but not being package throttled another.

It's not only the 100-200Mhz (which are quite a bit, up to workload)
But also the L3 cache that is bumped up by such.
Sadly too tight powerbudget remains an issue ~ and high SOC will cut into it too deeply.
MemOC guys need to extend their stock limits, else they lose performance
 
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Where can you find CCD count?
 

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About the FCLK holes, i sadly know nothing.
I heard it, keep hearing it but can not relate even remotely
Oh also thank you~ :)

The only time i had it, was with the broken 1.1.0.0 Patch C which introduced a hardlock even 1mhz beyond 1900 FCLK. It was an ABL Hardlock in the bootloader (in the AGESA blob)
There still is a memory training issue, for anything that's not Micron Rev.E ~ where in the early days, it could need 6 manual post attempts - till it finally trained correctly.
There where bugs where the bios was not cold-booting and freezing the reboot ~ soo needed a manual 2nd reboot.
A lot of annoying bugs , but only at that SMU (56.34), i really had a bad time

Else like on Matisse, on Vermeer CsOdtDrvStr (CAD_BUS) needs to be pushed, to help against bad memory training
Matisse was 24ohm, Vermeer is 30-40ohm.
VTT line aside.

AMD will have other fun issues with stacked interleaving on 3D Cache. Maybe numa interleaving even (maybe)
But i still feel, they have soo much left to fix - they wouldn't care touching it.

The only time i do recommend to run the surpressor, is after you know your CPU is stable @ 1900 or 1866. Have your Curve Optimizer set
And also reach correct L3 cache latency in Aida64 (this means, also extend your limits slightly).
4.85ghz all core reach is 10.4ns, 4.75ghz = 10.7ns, 4.65 = 10.9ns
5Ghz should be sub 9.9/9.8ns (for all you dual CCD guys)
As long as you do not hold this ~ cache is throttled and likely also package throttled.
Stability is one thing, but not being package throttled another.
What L3 latency is expected at 4000 on single CCDs? I usually get 10.6-10.7 with +200 pbo and -29x2/-30x4 CO, allcore in CB23 runs at 4.55GHz at 76W stock PPT. Is this expected or below?
 

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What L3 latency is expected at 4000 on single CCDs? I usually get 10.6-10.7 with +200 pbo and -29x2/-30x4 CO, allcore in CB23 runs at 4.55GHz at 76W stock PPT. Is this expected or below?
Try raising PLL voltage, this is occurring because more of the power budget is allocated to the higher FCLK
 

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It is not bugged reading but actual overboost bug
I had 55ghz once
It was fortunate that it didn't crash your PC.
Can give you an experimental old powerplan to always trigger overboost - but it breaks CPPC tags , because Windows is not buggy at all
powercfg /IMPORT "path"
with " " , without .txt
Then drop minimum processor freq to 7% or 8% , or 1% - you'll notice what works out best
But it will reboot your system because Overboost Bug is still too strong & broken. Like written in the long history post. AMD hasn't fixed this since 6-7 months

Igorslab continued his research and figured that the IHS Alloy, has changed and is very soft.
View attachment 2528523
ZEN remains to be Concave, but this has changed recently & it doesn't matter all too much anymore, since it does adapt to your cooler
I still would lap them after a cooler swap ~ as it will be uneven.
The only reason i do it, is for collecting fabrication/lab footprints. Seeing if they changed their tooling, if soldering got different, and since it was an issue
Noticed IgorsLab research later on - while he didn't lap units.
This here was too abstractly shifted - soo i had to check what is going on & found his post.
Only trophy units get lapped ~ but it wouldn't matter too much till 260W i think was it. He tested after what point thermal density is too high
Like i think @MrFox mentioned. Tho for such i'd consider a direct die bracket and likely flatten out the silicon. Like XOC guys do for their GPUs these days
Pretty sure this was with df cstates off, that should stop overboosting, no? Have to check again. Any software read if the bios settings are sticking?

re IHS, yea that looks like my 3800x when I lapped it… my 5800 looks better by eye but we’ll see when I lap it next tear down.
 

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Try raising PLL voltage, this is occurring because more of the power budget is allocated to the higher FCLK
I just wanted to know if 10.6-7 at 4000 is throttling or not :) Veii say at 4.85 dual ccds 10.4 is expected, just wondered what is expected at 4.55 allcore at 4000 :) I can try that and see if it changes.
 

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He should Zentimings - Debug , screenshot it for you
Seeing the mainboard, patch version, bios update and CCD Count
Rectangle Font Screenshot Software Parallel

He runs Samsung D-die and don`t have time to tune as much as me. Timings are terrible, but it`s the best he got, CL16 even at 1.45V and GDM is impossible. He has some wheas after all, I made him check event viewer again. We found none when I helped him tune ram a month ago, but the seem to pop-up now and then.

I guess the theory still stick then, mATX and ITX are much less prone to whea 19, ATX is much more likely above 3800\1900 :/ Too bad that ITX lacks a lot of connectivity and that most mATX-boards are very budget oriented.
 

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Pretty sure this was with df cstates off, that should stop overboosting, no? Have to check again. Any software read if the bios settings are sticking?
Set Powersuply Idle control, to typical current ~ too
It not always applies the DF-C_States
Global C-States have to run.
Where can you find CCD count?
ZenTimings, Tools, Debug

What L3 latency is expected at 4000 on single CCDs?
Non. The same one
It only depends on Frequency the cores can hold on this SSE test
It's a per core and a burst allcore test. 10.7 means you only hit 4.75-4.8 for this short burst test. Or some cores can not hold 4.8 at all
Any software read if the bios settings are sticking?
https://cdn.discordapp.com/attachme...4415275089/ZenStates_2.0.0_debug_20210810.zip
Don't complain to IrusanovBG/1nfraredBG about it - it's an alpha release and PBO functionality doesn't work.
But C6 and C-State toggle/readout functions :)
 
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I just wanted to know if 10.6-7 at 4000 is throttling or not :) Veii say at 4.85 dual ccds 10.4 is expected, just wondered what is expected at 4.55 allcore at 4000 :) I can try that and see if it changes.
Where can I find the pll voltage? Is it the 1.8V?
 

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The only time i do recommend to run the surpressor, is after you know your CPU is stable @ 1900 or 1866. Have your Curve Optimizer set
And also reach correct L3 cache latency in Aida64 (this means, also extend your limits slightly).
4.85ghz all core reach is 10.4ns, 4.75ghz = 10.7ns, 4.65 = 10.9ns
5Ghz should be sub 9.9/9.8ns (for all you dual CCD guys)
As long as you do not hold this ~ cache is throttled and likely also package throttled.
Stability is one thing, but not being package throttled another.

It's not only the 100-200Mhz (which are quite a bit, up to workload)
But also the L3 cache that is bumped up by such.
Sadly too tight powerbudget remains an issue ~ and high SOC will cut into it too deeply.
MemOC guys need to extend their stock limits, else they lose performance
So in some of my testing at 2000fclk I saw L3 @10.4 so I am I to assume CPU was stable? Copy and Latency seemed to suffer and I used loose timings for testing.
Font Screenshot Electronic device Software Technology
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off topic: So is there some trick to running GDM disabled at 1T & such high Mem/IF speeds? I could only get my single rank kit to post at 3400 1/1
 

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So in some of my testing at 2000fclk I saw L3 @10.4 so I am I to assume CPU was stable? Copy and Latency seemed to suffer and I used loose timings for testing.
View attachment 2528626 View attachment 2528627
Package throttle, as mentioned has nothing to do with stability
You should first test IMC and Fabric stability with y-cruncher (all tests 4 loops minimum, 72min = 1,7,0 key combination)
cLDO_VDDP is far to high for you ~ 950mV is enough for the memory controller (MCLK) to run 2500MCLK async. It has no connection to UCLK and only controls the memory controller
1150 is already in the dangerous region, i wouldn't even close approach 1.1v. It only degrades signal integrity for no reason

SETUP timings & tCKE are MCLK synced
You can not run X fixed delay between MCLKs
tCKE 11 should be fine for 2000 MCLK

Vermeer again needs bump on CsOdtDrvStr - opt 30-40, but minimum 24. Memory training needs this
If this is hydra, then higher latency expected
Even in OC mode, package throttle is still active by FIT ~ soo it depends on IOD, and procODT + VDD18 line. The combination
Single CCD are easier to spot throttling, as Write bandwidth has to be perfect half of MCLK maximum bandwidth (-1 MB/s)
Lower shows package throttle or core instability somewhere. For dual CCD you can use this trick

I think the 5900X holds 4.85 boost on stock , when limits are reworked
If it is so, then it is correct
If you did even 50mhz boost extend, then it's throttling already.
Also check both channels A2 & B2 , if tPHYRDL matches or you have (IO-L) missmatches
off topic: So is there some trick to running GDM disabled at such high Mem/IF speeds? I could only get my single rank kit to post at 3400 1/1
ClkDrvStr push, RTT_PARK weakening, more VDD18 - a lot of powering balance work
2T is what you start with , and forget GDM :)
 

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pls del
 

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Package throttle, as mentioned has nothing to do with stability
You should first test IMC and Fabric stability with y-cruncher (all tests 4 loops minimum, 72min = 1,7,0 key combination)
cLDO_VDDP is far to high for you ~ 950mV is enough for the memory controller (MCLK) to run 2500MCLK async. It has no connection to UCLK and only controls the memory controller
1150 is already in the dangerous region, i wouldn't even close approach 1.1v. It only degrades signal integrity for no reason

SETUP timings & tCKE are MCLK synced
You can not run X fixed delay between MCLKs
tCKE 11 should be fine for 2000 MCLK

Vermeer again needs bump on CsOdtDrvStr - opt 30-40, but minimum 24. Memory training needs this
If this is hydra, then higher latency expected
Even in OC mode, package throttle is still active by FIT ~ soo it depends on IOD, and procODT + VDD18 line. The combination
Single CCD are easier to spot throttling, as Write bandwidth has to be perfect half of MCLK maximum bandwidth (-1 MB/s)
Lower shows package throttle or core instability somewhere. For dual CCD you can use this trick

I think the 5900X holds 4.85 boost on stock , when limits are reworked
If it is so, then it is correct
If you did even 50mhz boost extend, then it's throttling already.
Also check both channels A2 & B2 , if tPHYRDL matches or you have (IO-L) missmatches

ClkDrvStr push, RTT_PARK weakening, more VDD18 - a lot of powering balance work
2T is what you start with , and forget GDM :)
I might play around with this again when I have more time with your above advice. I might ask you some things about my current OC in the ram stability thread as well ;)
 

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Yes
PLL18
Or VDD18
Okay, tried both 1840 and 1760, both gave me 10.8-10.9 L3 latency so auto/1800 works better at 10.6-10.7. Any other voltages etc that might impact this? I run ccd and vddp at 840mv, might be too low?
 

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Okay, tried both 1840 and 1760, both gave me 10.8-10.9 L3 latency so auto/1800 works better at 10.6-10.7. Any other voltages etc that might impact this? I run ccd and vddp at 840mv, might be too low?
My setup has never been one to follow these ultra low vDDP recommendations, running vDDP @ 840mv will just tank performance, I need + 920mv and up to 960mv when pushing 2067 mhz ...
 

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My setup has never been one to follow these ultra low vDDP recommendations, running vDDP @ 840mv will just tank performance, I need + 920mv and up to 960mv when pushing 2067 mhz ...
Okay, can try higher vddp/ccd then :)
 
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