Overclock.net banner
1 - 20 of 394 Posts

·
Registered
Joined
·
4,613 Posts
Discussion Starter · #1 ·
Did I miss a Zen 4 OC and result thread?

Zen 4 memory arrived :p
 

Attachments

  • Rep+
Reactions: rluker5 and bscool

·
Registered
Joined
·
2,381 Posts
Did I miss a Zen 4 OC and result thread?

Zen 4 memory arrived :p
"Zen 4 memory" ????? It's just DDR5.
No, you didn't miss Zen4 OC. it's not for sale yet even and MBs for it are rarer than hen's teeth. Only handful of privileged can have engineer samples of each but bound by contracts until official releases.
 
  • Rep+
Reactions: Yuriewitsch

·
Registered
Joined
·
985 Posts
So what memory IC are those ? ranks ?

Not interested in ddr5 or zen4 but I would never buy anything before reviews / reading forums for best boards, memory oc and agesa stability.

There's no way in hell I'm wasting months with a new platforms. Made that mistake with Zen launch. Asrock board, early agesa & dual rank hynix = crap all around.
 

·
Registered
Joined
·
2,381 Posts
I will buy a Zen 4 if they make one to go in my B550 MB. Otherwise I think I am good for a couple of years.
There are some talks to adapt some Zen4 for AM4 socket, something like they did with some FM APUs to AM4. Problem is IMC and if they make it to work with DDR4.
 
  • Rep+
Reactions: crastakippers

·
Registered
Joined
·
153 Posts

·
Not a linux lobbyist
Joined
·
2,879 Posts
"Zen 4 memory" ????? It's just DDR5.
No, you didn't miss Zen4 OC. it's not for sale yet even and MBs for it are rarer than hen's teeth. Only handful of privileged can have engineer samples of each but bound by contracts until official releases.
I already have Raptor memory. Picked up some Gskill 6400c32 for it. Works great with my Alder, but that cpu is going to go back with it's release period micron stuff when Raptor becomes available.
I also nabbed the Strix b660i mobo my Alder will be going in which is running that micron ram with a celeron 6900 in the itx case (just making sure everything is running fine) my 12700k will be going in when Raptor arrives.

I'm excited about Raptor so preparing ahead of time. Seems Nizzen is excited about Zen4. I couldn't help but notice the core chiplets were much closer together than Zen3. Might say something about chiplet to chiplet and core to core latency? Maybe more games might start scaling past 8 cores? Also seems like heat dissipation may be a limiting factor in power input which may be the primary limiting factor in core speeds for these chips. They might go pretty fast with very good cooling. We don't know yet.

Seems like somebody is planning on having a good time seeing just what these chips can do.
 

·
Iconoclast
Joined
·
32,827 Posts
There are some talks to adapt some Zen4 for AM4 socket, something like they did with some FM APUs to AM4. Problem is IMC and if they make it to work with DDR4.
AM4 and AM5 mandate different memory controllers.

However, AMD's IMC is not on die, just on package. It's part of the IOD, not CCD.

If Zen4 CCDs can work with the old IOD (which was the same on both Zen 2 and 3), then they could easily make DDR4 AM4 Zen4 parts. The only connection AMD's CCD have to anything else, is the Fabric interconnect and power delivery. So, if those are compatible, it could be attached to almost anything.

TLDR; an AM4 Zen4 part would likely just use the old IMC.

I couldn't help but notice the core chiplets were much closer together than Zen3. Might say something about chiplet to chiplet and core to core latency? Maybe more games might start scaling past 8 cores? Also seems like heat dissipation may be a limiting factor in power input which may be the primary limiting factor in core speeds for these chips. They might go pretty fast with very good cooling. We don't know yet.
The ~60% increase in expected FCLK suggests a similar reduction to inter-CCD latency. Shorter traces are probably a part of what allows that, but how close the CCDs are to each other isn't very relevant as the CCDs cannot talk directly to each other; any traffic needs to go through the IOD.

Heat dissipation has been a major limiting factor for AMDs 7N parts and will probably be an even bigger deal with the 5N AM4 parts as they have a correspondingly higher thermal density.
 

·
Registered
Joined
·
2,030 Posts
The ~60% increase in expected FCLK suggests a similar reduction to inter-CCD latency. Shorter traces are probably a part of what allows that.

Heat dissipation has been a major limiting factor for AMDs 7N parts and will probably be an even bigger deal with the 5N AM4 parts as they have a correspondingly higher thermal density.
The only information we've gotten on FCLK is that the maximum multiplier is 3000 MHz. If the limitation for FCLK is truly 3000 MHz, then I doubt we'll see FCLK actually running that fast.

Heat dissipation will also be harder, as the IHS is ~1mm thicker due to the socket being ~1mm closer to the motherboard, and AMD wanting to keep compatibility with AM4 coolers.
 

·
Iconoclast
Joined
·
32,827 Posts
The only information we've gotten on FCLK is that the maximum multiplier is 3000 MHz. If the limitation for FCLK is truly 3000 MHz, then I doubt we'll see FCLK actually running that fast.
The "sweet spot" was reported to be DDR5-6000 with a 1:1 ratio, meaning 3000MHz FCLK. This aligns with the pre-release information of Matisse and Vermeer, where the FCLKs mentioned were generally possible, not some absolute maximum selectable value. Vermeer's initially rumored FCLK (2000MHz) was a little optimistic, but most parts still did 1900 without issue and some can do quite a bit higher.

3000MHz would be lower than the current maximum selectable multiplier on AM4, by quite a bit, and I'll be surprised if 2800MHz (the minimum needed to support 1:1 with the fastest current DDR5 JEDEC bin) isn't essentially a given on Zen 4.

Edit: I suppose it's possible that 1:2 could be the default ratio, or that a more granular range of multipliers could be in place, but a reduction in FCLK without an increase in the width of the Fabric connection would destroy both bandwidth an latency. I would also expect it to be easier to increase FCLK frequency when the CCDs and especially IOD were being made on more advanced processes than it would be to widen the the physical connection between the CCDs and IOD.
 

·
Registered
Joined
·
2,030 Posts
The "sweet spot" was reported to be DDR5-6000 with a 1:1 ratio, meaning 3000MHz FCLK. This aligns with the pre-release information of Matisse and Vermeer, where the FCLKs mentioned were generally possible, not some absolute maximum selectable value. Vermeer's initially rumored FCLK (2000MHz) was a little optimistic, but most parts still did 1900 without issue and some can do quite a bit higher.
The sweet spot was reported to be DDR5-6000, no mention of FCLK, but people like to assume that stuff works exactly as previously.

What's to say FCLK hasn't increased it's link width by 50%, and the "optimal" FCLK for DDR5-6000 is 2000 MHz? Or 100% wider link, and optimal FCLK = 1500 MHz?

Let me link you the Twitter post made by 1usmus. That's where the rumor of 3000 MHz FCLK comes from. All he's saying there is that he's had a look at the AGESA, and noted down:
  • Active Memory Timing Settings feature with Memory Target Speed setting.
  • Max IF frequency - 3000MHz
  • LCLK Frequency Control
  • VDDIO Voltage Control: DIMM VDD and DIMM VDDQ
  • VPP Voltage Control
  • UCLK MODE - no changes
  • PBO and Curve Optimizer - no changes
  • Timings per channel: A, B, C and D.
  • Extreme Memory Profile(XMP/EXPO) operates in two modes: Low Latency and High Bandwidth.
  • Active OC Tuner with 2 settings: CPU Current Limit and CPU Temperature Limit.
  • Async CPU/PCIe Clock
  • CCX Clock Control, 4 CCX
  • Host Clock
3000MHz would be lower than the current maximum selectable multiplier on AM4, by quite a bit, and I'll be surprised if 2800MHz (the minimum needed to support 1:1 with the fastest current DDR5 JEDEC bin) isn't essentially a given on Zen 4.

Edit: I suppose it's possible that 1:2 could be the default ratio, or that a more granular range of multipliers could be in place, but a reduction in FCLK without an increase in the width of the Fabric connection would destroy both bandwidth an latency. I would also expect it to be easier to increase FCLK frequency when the CCDs and especially IOD were being made on more advanced processes than it would be to widen the the physical connection between the CCDs and IOD.
What is possible, is that the "low latency mode" is operating at UCLK = MCLK, while the "high bandwidth mode" operates at UCLK = MCLK/2. With transfer rates in low latency being limited to something like DDR5-4000.

There's also the fact that AMD is dropping XMP, and make their own standard called EXPO. Needing two sets of memory timings and frequencies (low latency and high bandwidth), would make the decision to create a new standard fit quite well.

This is pure speculation from my part, but if what 1usmus read from the AGESA is correct, and there are no mistranslations, it fits a lot better than "3000 MHz FCLK 1:1". AMD has rated their memory controllers quite close to the limit recently, so only leaving ~500 MT/s of headroom would fit the pattern when looking at Zen 1, Zen+, Zen 2, and Zen 3.
 

·
Iconoclast
Joined
·
32,827 Posts
What's to say FCLK hasn't increased it's link width by 50%, and the "optimal" FCLK for DDR5-6000 is 2000 MHz? Or 100% wider link, and optimal FCLK = 1500 MHz?
The main contraindication to this would be the significant amount of extra vias and traces required to to go from 32/16B per cycle to 48/24 or 64/32. It's certainly not impossible, but it would be a huge increase in density and substrate complexity for the AM5 parts with only two CCDs maximum, and it would be ridiculous for the Genoa parts that can have six CCDs per package.

I've seen it, and I'm doubtful, especially in light of more recent information.

The parts about the FCLK and the reduction in CCD core count back to four strike me as particularly suspect.

What is possible, is that the "low latency mode" is operating at UCLK = MCLK, while the "high bandwidth mode" operates at UCLK = MCLK/2. With transfer rates in low latency being limited to something like DDR5-4000.
There are JEDEC DDR5 bins going down to 3200, I'm doubtful that AMD would target something as low as 4000MT/s for the top of their lower latency mode.

There's also the fact that AMD is dropping XMP, and make their own standard called EXPO. Needing two sets of memory timings and frequencies (low latency and high bandwidth), would make the decision to create a new standard fit quite well.
This is pure speculation from my part, but if what 1usmus read from the AGESA is correct, and there are no mistranslations, it fits a lot better than "3000 MHz FCLK 1:1". AMD has rated their memory controllers quite close to the limit recently, so only leaving ~500 MT/s of headroom would fit the pattern when looking at Zen 1, Zen+, Zen 2, and Zen 3.
A 500MT/s pattern with DDR4 would be proportionally much higher with DDR5 and both Zen 2 and 3, in practice support far higher than the highest JEDEC DDR4 bin available, even at 1:1. Not even being able to run the current top bit at rated speeds at 1:2 and barely being able to support the next bin at 1:4 seems far fetched to me.

Not saying it can't be true, but it sounds both needlessly expensive and probably damagingly slow to clock the Fabric so low. Without more information, my feeling is that the path of least resistance to making sure fabric performance keeps up with the new architecture and memory subsystems is to increase it's clock speed.

I guess we'll see for sure on the 29th.
 

·
Registered
Joined
·
2,030 Posts
The main contraindication to this would be the significant amount of extra vias and traces required to to go from 32/16B per cycle to 48/24 or 64/32. It's certainly not impossible, but it would be a huge increase in density and substrate complexity for the AM5 parts with only two CCDs maximum, and it would be ridiculous for the Genoa parts that can have six CCDs per package.
I was thinking more like similar amount of PHYs and SerDes, but internal FCLK width is doubled, and the SerDes transfers twice the amount of data per FCLK tick. Zen 2/3 PHYs transfer 8 bits per FCLK if I remember correctly, what's stopping AMD from going to 16 bits?

A 500MT/s pattern with DDR4 would be proportionally much higher with DDR5 and both Zen 2 and 3, in practice support far higher than the highest JEDEC DDR4 bin available, even at 1:1. Not even being able to run the current top bit at rated speeds at 1:2 and barely being able to support the next bin at 1:4 seems far fetched to me.

Not saying it can't be true, but it sounds both needlessly expensive and probably damagingly slow to clock the Fabric so low. Without more information, my feeling is that the path of least resistance to making sure fabric performance keeps up with the new architecture and memory subsystems is to increase it's clock speed.

I guess we'll see for sure on the 29th.
There is no 1:4 ratio for UCLK as per 1usmus, so AM5 might not even set a new DDR5 frequency record compared to LGA1700. As for clocking the fabric so low, it could also be a matter of power savings, as IF power isn't exactly low on Vermeer or Matisse as it is, doubling the internal width and keeping FCLK low seems like a smarter choice in terms of power.

As for the 6000 MT/s being "optimal", it might also be a motherboard factor. Most 4 DIMM boards on Z690 struggle to run anything more than DDR5-6000 stable.
 

·
Iconoclast
Joined
·
32,827 Posts
I was thinking more like similar amount of PHYs and SerDes, but internal FCLK width is doubled, and the SerDes transfers twice the amount of data per FCLK tick. Zen 2/3 PHYs transfer 8 bits per FCLK if I remember correctly, what's stopping AMD from going to 16 bits?
Increasing the internal width doesn't do any good if that SerDes IFOP link is the bottleneck, and it is. At current speeds (1600MHz stock) and widths 32/16 bytes per cycle a CCD has 51.2GB/s of downstream and 25.6GB/s of upstream bandwidth.

You can't increase bandwidth without making it physically wider, or increasing the clock speed. Making it physically wider will increase power consumption at the same clock speed linearly and proportionally increase the number of vias and traces for the physical layer. This might be workable on AM5 where there are only two CCDs. However, Genoa will have up to twelve Zen 4 CCDs. A 100% increase to the number of data lines and 50% more cores on top of it would mean for a phenomenally complex substrate and IOD. Not impossible, but speeding up current links strikes me as easier.

There is no 1:4 ratio for UCLK as per 1usmus, so AM5 might not even set a new DDR5 frequency record compared to LGA1700.
If 1:2 is the max, then it needs to clock extremely high just to hit current JEDEC DDR5 bins. The memory controller clocking higher than the Fabric might make sense, but not if the link between the CCD and IOD doesn't physically widen...unless the main purpose of the additional memory bandwidth is for the new IGP, which seems unlikely. Starving the cores of memory bandwidth while increasing the latency of the memory subsystem by mandating more clock crossing boundaries probably wouldn't bode well for performance.

Maybe they're using different dies for Genoa this time around and going back to two CCXes per CCD for the AM4 parts, then giving each CCX it's own links to the IOD but that also seems unlikely, to me.

As for clocking the fabric so low, it could also be a matter of power savings, as IF power isn't exactly low on Vermeer or Matisse as it is, doubling the internal width and keeping FCLK low seems like a smarter choice in terms of power.
I'm not convinced it would be more power hungry to increase FCLK frequency by ~75% rather than double the physical width and even if peak power is higher, I'm not convinced it wouldn't be worthwhile for the cost/complexity saving.
 

·
Registered
Joined
·
561 Posts
Excited for new toys, we'll know more(everything there is to know from AMD's side) by the end of the month.
 

·
Registered
Joined
·
219 Posts
Zen 4 memory arrived :p
It's a good idea to buy DDR5 RAM now. Because nobody is buying those hot Intel CPUs, and DDR5 prices have been falling dramatically, but this may change after Zen 4 hits the marked.

But the big question is, what's the equivalent of "Samsung B-die" on DRR5?
 

·
Registered
Joined
·
4,613 Posts
Discussion Starter · #18 ·
It's a good idea to buy DDR5 RAM now. Because nobody is buying those hot Intel CPUs, and DDR5 prices have been falling dramatically, but this may change after Zen 4 hits the marked.

But the big question is, what's the equivalent of "Samsung B-die" on DRR5?
Samsung b-die is Hynix in general. The best is Hynix a-die.
 
  • Rep+
Reactions: Sam_Oslo

·
Registered
Joined
·
144 Posts
Samsung b-die is Hynix in general. The best is Hynix a-die.
When this Hynix a-die coming, any available with it yet?

I am thinking now to buy this,

But unsure if the 4800 variant with overclocking can do the same as the 5600mhz variant?
 

·
Registered
Joined
·
2,030 Posts
When this Hynix a-die coming, any available with it yet?

I am thinking now to buy this,

But unsure if the 4800 variant with overclocking can do the same as the 5600mhz variant?
4800 kits are almost guaranteed Micron (****)

Micron can't do 5600, so get kits rated 5600 and up
 
  • Rep+
Reactions: Alexshunter
1 - 20 of 394 Posts
Top