[mike7877]

The kit is Patriot Viper 3 1866 CL10 in an Asus P8Z68-V GEN3 motherboard with an i5 2500K @ 4600MHz (static). Once RAM timings have been finalized, the CPU will be increased to the highest frequency it can hit with 100MHz FSB between 1.32 and 1.35V.

RAM
Frequency: 1866MHz overclocked to 2133
Timings: 10-11-10 overclocked/changed/changed to 10-12-11
Voltage: 1.5V XMP running at 1.65V (for now, lowering after tweaking, probably by ~0.02-0.03V)

I've only ever spent a few hours specifically reading up on overclocking DDR3 back in 2011 when I got the CPU in the machine this is for. I lost interest really - undervolted the chip to ~1.2V and overclocked to 42-4400MHz and left the RAM at its XMP timings and clock speed (1600MHz), with a slightly lowered voltage (by 0.07V to 1.58V. This was to keep Intel's stated mandatory 0.5V maximum difference between VCCIO (VTT) and DRAM for Sandy Bridge (and some other) processors.

A little bit below is a graphic I made using a screenshot of AIDA64's northbridge (RAM timings) page and MSPaint to outline the timings I have.

Purple is as low as it'll go without causing errors at 2133MHz
Green will go lower but hasn't been checked for errors during operation
Small blue dash underneath means no BIOS access to the timing (thankfully they're all pretty much low enough)

tRFC at 220T is stable, 204 errored. It's up at 240 until all others are finished, at which point I will lower it to 10 over what generates errors in a hot case
This is 3T RAM (weird, I know), so 2T is it "optimized". It wouldn't do anything at any useful frequency at 1T
Purple stars mean the BIOS doesn't allow a lower number to be set. Eg. tRRD of 4? Press minus and 4 changes to Auto - press plus and 4 changes to 5. No 3!
tWR is at 10. Like tCL, but 2 higher than tCWL. I haven't tested it lower - does anyone know if there are any benefits lowering it? Or will other timings effectively limit any performance gains it would otherwise cause if they were lower?
tREF of 9999 is the highest number (unfortunately). It's like DDR4's 65000 being ripped off to 25-28K. But it's at its highest and best option, unless someone knows something I don't and I should lower it?

My biggest curiosity is tRAS. It's set to 31, which I've heard is perfect because one less than CL + tRCD + tRP is said to be optimal, and 10+12+11-1 = 31
Is that rule correct?

 

[mike7877]

If nobody's responded because it's DDR3 and they never overclocked DDR3, just advise like it's 4 and say you're doing so (they're similar enough).
And if you haven't responded because it's been a really, really long time since you overclocked your DDR3, and almost 10 years since you even tweaked it, and over 5 since you've been in the BIOS, and 7 since you gave it to your girlfriend, and 4 since she became your ex, and please tell me if tRAS worth lowering

 

[gtz]

If nobody's responded because it's DDR3 and they never overclocked DDR3, just advise like it's 4 and say you're doing so (they're similar enough).
And if you haven't responded because it's been a really, really long time since you overclocked your DDR3, and almost 10 years since you even tweaked it, and over 5 since you've been in the BIOS, and 7 since you gave it to your girlfriend, and 4 since she became your ex, and please tell me if tRAS worth lowering

Sorry I am no help, don't remember DDR3 that much. But the "7 years since you gave it to your girlfriend and 4 since she became you ex" gave me a good laugh.

Free bump for you, but oddly enough I can't recall DDR3. I can remember DDR2 timings but not DDR3.

 

[mike7877]

Sorry I am no help, don't remember DDR3 that much. But the "7 years since you gave it to your girlfriend and 4 since she became you ex" gave me a good laugh.

Free bump for you, but oddly enough I can't recall DDR3. I can remember DDR2 timings but not DDR3.

Thanks.
Memory's funny that way lol

I wasn't really enamored with DDR3 when it came out (latency). Come to think of it, DDR2's latency was worse as well, but I don't think it was as bad. DDR5 takes the cake.
I was really young when I had my DDR system (dual channel DDR 266 with a P4 2.66B (533FSB - perfect match for the RAM). At one point I had 2x 512GB DDR400 running at 266, timings must've been amaaazing. Too bad P4 architecture kinda sucked and I was too young to really care much. I think it was CL2 or 3. Were there CL 2.5?

 

[Blameless]

The kit is Patriot Viper 3 1866 CL10

What ICs are in it? That's generally more important than the specs.

tRRD of 4? Press minus and 4 changes to Auto - press plus and 4 changes to 5. No 3!

This is normal. Some platforms will allow lower, but most won't. It's related to tFAW; the minimum useful tFAW is 4*tRRD.

tWR is at 10. Like tCL, but 2 higher than tCWL. I haven't tested it lower - does anyone know if there are any benefits lowering it? Or will other timings effectively limit any performance gains it would otherwise cause if they were lower?

tWR is expected to be double tRTP. Some memory allows lower, but if you can set it lower, it might be worth trying to lower tRTP as well. Conversely, if you need a tWR of 10, but are using a tRTP of 4, I'd double check if 4 is really stable.

tREF of 9999 is the highest number (unfortunately). It's like DDR4's 65000 being ripped off to 25-28K. But it's at its highest and best option, unless someone knows something I don't and I should lower it?

Higher tREFI is always faster, but it's a hard setting to test, and quite temperature sensitive.

My biggest curiosity is tRAS. It's set to 31, which I've heard is perfect because one less than CL + tRCD + tRP is said to be optimal, and 10+12+11-1 = 31
Is that rule correct?

That 'rule' is just a rough guideline, one that usually results in higher than optimal tRAS, in my experience, but everyone has a favorite formula and some of them even have rational arguments for them (tCL + tRCD + tRP is the the time it takes to close an active page and open another, so is a suitable minimum tRAS at least some of the time). Optimal setting will vary with workload; the timing is a window and some things like it held open longer to fit as many burst operations as possible, others like it short to minimize the latency when dealing with small transfers or page misses. Tighter has a tendency to be faster, both because the window has some flexibility to it and shorter tRAS allows for a lower tRC. Stability is also a factor...some ICs don't like tRAS being too tight or too loose, irrespective of other guidelines.

tCKE doesn't have any measurable performance impact, except, perhaps, if memory power down is enabled, but even with such features disabled it can sometimes influence stability. I'd just leave it on auto on a DDR3 setup.

I wasn't really enamored with DDR3 when it came out (latency). Come to think of it, DDR2's latency was worse as well, but I don't think it was as bad. DDR5 takes the cake.
I was really young when I had my DDR system (dual channel DDR 266 with a P4 2.66B (533FSB - perfect match for the RAM). At one point I had 2x 512GB DDR400 running at 266, timings must've been amaaazing. Too bad P4 architecture kinda sucked and I was too young to really care much. I think it was CL2 or 3. Were there CL 2.5?

Timings are just a means to an end. Actual memory latency hasn't changed a lot, but bandwidth has increased dramatically.

Back in the S754/939 days I was running Winbond CH-5 UTT stuff at DDR-500 2-3-2-6(or 12 on 939, which was a faster tRAS for that platform)-T1 and real latency to main memory has about the same in most well-tuned setups since, assuming there was a true IMC present, with the notable exceptions of Bulldozer/Piledriver. Bandwidth with the same number of channels is more than ten times as high on modern DDR4 platforms though, and pushing twenty times higher at the same buswidth with DDR5.

 

[mike7877]

What ICs are in it? That's generally more important than the specs.

Unfortunately I'm not sure what they are and have no clue where to even begin looking. Do you know if there are any programs that report a number I could use somewhere for searching with? Heatsinks block the chips unfortunately

tWR is expected to be double tRTP. Some memory allows lower, but if you can set it lower, it might be worth trying to lower tRTP as well. Conversely, if you need a tWR of 10, but are using a tRTP of 4, I'd double check if 4 is really stable.

After further testing tWR, I found its minimum to be 7. Does that make it less likely tRTP's report of 4 is wrong?

Somewhat unrelated, to my knowledge tWCL is supposed to be 2 less than tCL.
I have tCL set to 10 - will it not being 9 cause any issues (edit for clarity: tWCL is 7)? I don't think tCL of 9 is stable (at least at this voltage which I don't plan on increasing. Well, maybe I would, but by no more than 0.02V)

Higher tREFI is always faster, but it's a hard setting to test, and quite temperature sensitive.

I'll leave it at 9999

That 'rule' is just a rough guideline, one that usually results in higher than optimal tRAS, in my experience, but everyone has a favorite formula and some of them even have rational arguments for them (tCL + tRCD + tRP is the the time it takes to close an active page and open another, so is a suitable minimum tRAS at least some of the time). Optimal setting will vary with workload; the timing is a window and some things like it held open longer to fit as many burst operations as possible, others like it short to minimize the latency when dealing with small transfers or page misses. Tighter has a tendency to be faster, both because the window has some flexibility to it and shorter tRAS allows for a lower tRC. Stability is also a factor...some ICs don't like tRAS being too tight or too loose, irrespective of other guidelines.

So it seems there's some flexibility here. How much lower do you think would be optimal for this setup (being used for general purpose)? 28? 26?

tCKE doesn't have any measurable performance impact, except, perhaps, if memory power down is enabled, but even with such features disabled it can sometimes influence stability. I'd just leave it on auto on a DDR3 setup.

As far as I've been able to tell, this board's BIOS doesn't have a memory power down option

Timings are just a means to an end. Actual memory latency hasn't changed a lot, but bandwidth has increased dramatically.
Back in the S754/939 days I was running Winbond CH-5 UTT stuff at DDR-500 2-3-2-6(or 12 on 939, which was a faster tRAS for that platform)-T1 and real latency to main memory has about the same in most well-tuned setups since, assuming there was a true IMC present, with the notable exceptions of Bulldozer/Piledriver. Bandwidth with the same number of channels is more than ten times as high on modern DDR4 platforms though, and pushing twenty times higher at the same buswidth with DDR5.

Are you saying 3:1 is a good ratio for tRAS to tCL?

 

[mike7877]

Performing well!

I assume that "Unknown 1866 CL10 Series 2x8GB" means "Patriot 1866 CL10 Series 2x8GB"

they got everything in the name but the manufacturer!

Oh, can't forget latency. If too small, on the left is 0, 10ns, 20ns, 30ns, 40ns, 50ns, 60ns.
Bottom: 8kB, 16kB, 32kB, 64kB, 128kB, 256kB, 512kB, 1024kB, 2048kB, 4096kB, 8192kB, 16384kB, 32768kB, 65536kB, 131072kB

Edit: Although AIDA64's memory bandwidth test hasn't changed much since I started lowering timings, benchmarks such as Browserbench.org's Speedometer (V 2.0) have indicated performance increases. I didn't do multiple runs for the baseline at the beginning, but the result now is 144 and doesn't do so much as even vary by 1, so the initial measurement of 132 is probably accurate - 8.33% increase in performance there!

Once all settings are final, I'll run a bunch of benchmarks. Then I'll reset all the timings to default and run them again. Then I'll also reset the frequency (from 2133 to 1866) and run them one last time. Then I'll post them all here

 

[Blameless]

Unfortunately I'm not sure what they are and have no clue where to even begin looking. Do you know if there are any programs that report a number I could use somewhere for searching with? Heatsinks block the chips unfortunately

Thaiphoon Burner (even the free version) will read the entire SPD and usually be able to report IC and PCB type.

After further testing tWR, I found its minimum to be 7. Does that make it less likely tRTP's report of 4 is wrong?

It means you should probably leave tRTP at 4 and use a tWR of 8, unless you very carefully validate 7 for stability.

Somewhat unrelated, to my knowledge tWCL is supposed to be 2 less than tCL.
I have tCL set to 10 - will it not being 9 cause any issues (edit for clarity: tWCL is 7)? I don't think tCL of 9 is stable (at least at this voltage which I don't plan on increasing. Well, maybe I would, but by no more than 0.02V)

There is no hard rule for this. tCWL may need to be as high as tCL on some memory at some clocks, but as clocks fall the wider the gap can usually be. tCL-2 is pretty typical for your clocks, but if -3 is stable, use it. However, if -3 does work, it may imply that tCL itself could be lowered another notch. -4 or higher is almost certain not to be stable.

So it seems there's some flexibility here. How much lower do you think would be optimal for this setup (being used for general purpose)? 28? 26?

With your other timings, I'd see if 20 was stable (depending on ICs it may not even POST, or it could be rock solid), then if 24 was any faster.

Are you saying 3:1 is a good ratio for tRAS to tCL?

It was on Winbond CH-5 on a single-channel K8 IMC, but that says almost exactly nothing about your situation.

 

[mike7877]

Thaiphoon Burner (even the free version) will read the entire SPD and usually be able to report IC and PCB type.

I downloaded it, ran the free version. It doesn't seem to be giving the information you're looking for though. Found out my 1866 sticks have chips that are officially rated for 1600 though. Maybe they're all like that? If I'm remembering right, my DDR4 I run at 3900 is Patriot Viper Steel 4400 C19 which is officially rated for 2133.

It means you should probably leave tRTP at 4 and use a tWR of 8, unless you very carefully validate 7 for stability.

tWR of 7 is 12 hours P95 large FFT stable, but not 3 consecutive runs of extreme1 anta777 stable (which I'm doing at the end. For reasons unknown, when I open TM5 with admin privilages, this install of Windows causes it to malfunction. After the reload I do before giving the machine to parents I'm running TM5, then doing Windows updates, then installing programs, then giving). Anyway, if during this final run I get errors, changing tWR from 7 to 8 will be the first thing I try.

There is no hard rule for this. tCWL may need to be as high as tCL on some memory at some clocks, but as clocks fall the wider the gap can usually be. tCL-2 is pretty typical for your clocks, but if -3 is stable, use it. However, if -3 does work, it may imply that tCL itself could be lowered another notch. -4 or higher is almost certain not to be stable.

I'll try it again at 9 - the last time I tried was early on.

With your other timings, I'd see if 20 was stable (depending on ICs it may not even POST, or it could be rock solid), then if 24 was any faster.

I've verified 22 is stable. In a small assortment of programs, tRAS of 22 and 24 seem to benchmark the same as 28. With 26 and 27 (no 23 or 25 benchmarks) there appears to be a bit of a slump (~0.65%, so it may be nothing).
I'll try 20 and see how it benchmarks. Off hand, do you know what happens when the read/write process is cut short because tRAS is set too low?

It was on Winbond CH-5 on a single-channel K8 IMC, but that says almost exactly nothing about your situation.

True, a very different platform. I thought you were reminiscing of a previous system, just wanted to make sure it didn't have a dual purpose.

 

[Blameless]

I downloaded it, ran the free version. It doesn't seem to be giving the information you're looking for though. Found out my 1866 sticks have chips that are officially rated for 1600 though. Maybe they're all like that? If I'm remembering right, my DDR4 I run at 3900 is Patriot Viper Steel 4400 C19 which is officially rated for 2133.

Yeah, doesn't look like Patriot programmed the SPD with IC part number. Unfortunate, but not uncommon. Timing wise, it's behaving somewhat like Hynix stuff, but the only way to tell for sure would be to find a DDR3 IC list and match exact part numbers/revisions or remove the heatspreaders.

And yes, most OCer DDR3 was built on ICs binned for 1333 or 1600 by the original IC manufacturer then given a second (or third, or fourth) round of binning by the actual module assembler.

Off hand, do you know what happens when the read/write process is cut short because tRAS is set too low?

It's my understanding that the memory controller will try to issue the next precharge command as soon as possible. This will either really be too soon and data will be lost, or will just be before is optimal, in which case performance won't be best as certain commands are repeated (instead of just continuing to transfer data) before they'd otherwise need to.

 

[mike7877]

Yeah, doesn't look like Patriot programmed the SPD with IC part number. Unfortunate, but not uncommon. Timing wise, it's behaving somewhat like Hynix stuff, but the only way to tell for sure would be to find a DDR3 IC list and match exact part numbers/revisions or remove the heatspreaders.

And yes, most OCer DDR3 was built on ICs binned for 1333 or 1600 by the original IC manufacturer then given a second (or third, or fourth) round of binning by the actual module assembler.



It's my understanding that the memory controller will try to issue the next precharge command as soon as possible. This will either really be too soon and data will be lost, or will just be before is optimal, in which case performance won't be best as certain commands are repeated (instead of just continuing to transfer data) before they'd otherwise need to.

I found more information - does any of it helps you infer more? It's something still being manufactured, at least as of March 7-11, 2022.

 

[Blameless]

I found more information - does any of it helps you infer more? It's something still being manufactured, at least as of March 7-11, 2022.

View attachment 2568355

Well, it's definitely Hynix, and almost certainly MFR or AFR (BFR won't do the tRFC you're using), but without the component and die revision entries knowing which of those it is would require looking at the ICs. That said, there probably isn't enough difference between 4Gb AFR and MFR dies to make a very meaningful difference.

Anyway, the timings you've got are pretty close to what I'd expect on AFR/MFR.

 

[mike7877]

Well, it's definitely Hynix, and almost certainly MFR or AFR (BFR won't do the tRFC you're using), but without the component and die revision entries knowing which of those it is would require looking at the ICs. That said, there probably isn't enough difference between 4Gb AFR and MFR dies to make a very meaningful difference.

Anyway, the timings you've got are pretty close to what I'd expect on AFR/MFR.

Very good. I'm testing 20 now - 25 minutes in. I don't expect there to be errors.
Before starting this I tried a few new timings:
I tried tCL 9 - wouldn't POST. Went back to 10, increased DRAM voltage +0.1V to 1.75V, and VCCIO from 1.26 to 1.32. Rebooted, tried tCL 9 again -
wouldn't POST.
So I don't think tCL 9 at 2133 will work - at least not at any voltages I'm willing to set. It might not be the RAM's fault, a VCCIO of 1.21 is the absolute minimum required for 2133 10-12-11, so 1.32 might not have been enough. Or VCCSA needs a bit of an increase from 0.925V for the memory controller to run faster and I don't have access to it. Something I haven't tried is using the motherboard's auto RAM overclock function and checking to see if it increases VCCSA. Even if there's no direct access to it, it's possible this could still do it
Back to DRAM 1.75V and VCCIO 1.32V - I tried lowering tRP from 11 to 10. Without elaborating (basically I did what I did above with tCL), it didn't work.

After I verify tRAS of 20 is very stable, I think I'll try what I mentioned above to try to get the motherboard to increase VCCSA. If it does, I'll do more testing. If not, I won't. I'm happy either way - this RAM already did much better than I anticipated - it's clocked 266MHz faster and has tCL set 2 lower. Some secondaries are even significantly lower than I thought (specifically tRRD, tWTR, tRTP all set to the BIOS minimum of only 4, tWCL and tWR: 7, tRFC yet to be determined but somewhere between 204 and 210, and tREFI maxed out at (the unfortunately low) 9999

 

[mike7877]

I found out a few more timings are able to be optimized. I tried lowering them in bulk - all by 1. Two of the 4s wouldn't go any lower (tRTR and tWTR). The three other 4s that were able to be lowered, I lowered to 3, all 3s were lowered to 2. There were no 2s, and the 1s stayed as they were.

Unfortunately it caused errors. A blue screen about a minute into P95 actually. I'm going to try lowering these one at a time to see how they take. Should skip any of them, just leaving them as they are because in all likelihood they can't go any lower? Asking to potentially save time because there are likely 5 and are possibly up to 15 individual steps that each take a minimum of 2.5 hours to verify relative stability