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[EETimes] Intel built a 32nm test chip

1311 Views 18 Replies 17 Participants Last post by  MasterFire, 
linskingdom
Quote:


SAN JOSE, Calif. -- At the upcoming 2008 IEEE International Electron Devices Meeting (IEDM), Intel Corp. is expected to take the wraps off its new 32-nm process technology for high-performance microprocessors.

According to the IEDM paper, Intel built a functional 32-nm, 291-Mbit SRAM array test chip with a 0.171-micron2 cell size. The device has nearly 2 billion transistors, and an array density of 4.2-Mbit2.

The test chip operated at 3.8-GHz at 1.1 Volt, according to the paper. Intel (Santa Clara, Calif.) is expected to deploy its first immersion lithography scanners at 32-nm. The 193-nm machines will be sourced from Nikon Corp. (Tokyo).

The process also makes use of a second-generation, high-k/metal gate technology, a strained channel, and nine levels of low-k interconnect dielectrics, according to a sneak preview of the paper.

The process enables the highest drive currents reported to date for 32-nm technology. NMOS saturated drive current is 1.55-mAmicron while the corresponding PMOS value is 1.21-mAmicron.

At IEDM, there are also other major papers. HRL Laboratories will describe the integration of RF CMOS and indium phosphide (InP) transistors.

''Indium phosphide (InP) transistors are much faster than those made from silicon, but dense InP integrated circuits haven't been made because indium phosphide technology is less advanced and harder to work with than silicon, and it costs much more,'' according to the paper.

HRL is said to have integrated entire wafers of high-performance 250-nm, 300-GHz ft/fmax InP DHBTs (double-heterostructure bipolar transistors) with wafers of IBM's existing 130-nm RF-CMOS technology, according to the paper

Also at the IEDM, Tohoku University will discuss a novel way to use magnetic tunnel junctions (MJTs) for data storage in a high-density 3D processor architecture.

The researchers used them to construct a type of memory called a SPRAM (spin-transfer torque RAM). ''Then, they used the SPRAMs to drive reconfigurable 3D logic blocks fabricated with a standard 0.14-micron CMOS process,'' according to the paper.

''Experimental results showed that the reconfigurable logic blocks achieved a 25-MHz readout speed and relatively low levels of magnetic resistance,'' according to the paper.

The 54th annual IEDM is Dec. 15-17 at the Hilton San Francisco. The conference will be preceded by a day of short courses on Sunday, Dec. 14.

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xlastshotx
3.8Ghz at 1.1v !!!

(i bet if you give it 1.2v it burns out
)
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V
yeah yeah... what can it overclock to ?
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BizzareRide
Lets hope is has the same voltage tolerance of 1.3625.
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bretto22
2
Quote:


Originally Posted by xlastshotx
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3.8Ghz at 1.1v !!!

(i bet if you give it 1.2v it burns out
)

haha so true! btw nice find
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Odyn
.......... WAYYYYYYYYYYYYY too many abbreviations. I feel like I was reading Sanskrit.
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R
Quote:


Originally Posted by BizzareRide
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Lets hope is has the same voltage tolerance of 1.3625.

Not a chance in hell.
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BizzareRide
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Originally Posted by ReignsOfPower
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Not a chance in hell.

lol one can only dream

Nice OC on your quad BTW. 470fsb with only 1.28v, you must feel good!
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Tator Tot
I want to know its max volts, cause I got a fear that at 1.3 volts its a goner.
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R
Quote:


Originally Posted by BizzareRide
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lol one can only dream

Nice OC on your quad BTW. 470fsb with only 1.28v, you must feel good!

Thanks mate. I definitely do, it cost me though. If it didn't hit 4GHz I'd cry and just buy a PS3 lol
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niteshade
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Originally Posted by Odyn
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.......... WAYYYYYYYYYYYYY too many abbreviations. I feel like I was reading Sanskrit.

Yea......I didn't understand any of that either besides the speed ,size and the voltage.
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rduffy123
Well if you think about it, the lower the voltage goes, the less voltage it takes to oc more. So adding .05 volts in like adding .1. Just my .02
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A
I remember seeing a video (~1.5 yrs ago) of a woman working at Intel showcasing the then new 45nm process and pointing out to the cameraman how they were also working on the 32nm and 25nm process.
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C
3.8GHz at 1.1V is really good but keep in mind that it was just a SRAM array. Full logic is a bit more complicated to fab and may not run at that speed and voltage. Nonetheless, that is pretty amazing considering they are switching to immersion lithography. That only means much better parts are still to come!
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X
And for this reason I plan on attempting to skip Core i7... I knew that they had a major leap coming

Did any of you catch this?

Quote:


The process also makes use of a second-generation, high-k/metal gate technology, a strained channel, and nine levels of low-k interconnect dielectrics, according to a sneak preview of the paper.

The process enables the highest drive currents reported to date for 32-nm technology. NMOS saturated drive current is 1.55-mAmicron while the corresponding PMOS value is 1.21-mAmicron.

Basically its a higher current tolerance which, I hope, should allow for better voltage acceptance to the chip
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joemaniaci
Its crazy to see people talking about a transistors speed, when im just getting use to thinking of it as going off to on or on to off instantaneously, and yet its not and they can actually improve upon that.
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cubanresourceful
Wow, all that looks interesting, but I don't really get what the 3D cube thing they are talking about.... :/
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Ned_Campose
Quote:


Originally Posted by Tator Tot
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I want to know its max volts, cause I got a fear that at 1.3 volts its a goner.

Im assuming 1.26v to 1.28v range

1.3v on water. 1.35 suicide run.. Max
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MasterFire
A nice Phase Change loop or two and on to 10Ghz? Nèh... Although... Neh...
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