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Let's look at a classic CPU, the i5 2500k:
Quote:
Past that, well, I'm lost. The 4x32KiB part (L1) makes sense - that means there are four of these (one per core) with 32768 bytes of memory each. What do "8-way" and "12-way" mean? Is this like RAM channels? If yes, how wide is the bus? Further down on the page, it says each cache level has a "line size" of 64 bytes. Is that a 512-bit bus per "channel?" If yes, then it sounds like - assuming these don't use anything like DDR (double data rate) or QDR (quadruple) - the L3's bandwidth is:
(12 "channels") * (64B / channel) * (3.3GHz) = 2.534TB/s of bandwidth, shared among all four cores.
But I'm not sure if I'm right.
Let's look at another, the good ol' FX-8350:
Quote:
(2.534TB/s) * (64 / 12) * (4 / 3.3) = 16.39TB/s of raw bandwidth, shared among all four modules.
Am I on the right track, or am I totally lost? These numbers sound way too high and I might be totally wrong with regards to my interpretation of whatever "##-way associative cache" means.
Quote:
I think it's safe to assume that latency is how many clock cycles it takes to read or write to that level of cache, right? I assume also that the cache speed is linked to the CPU's frequency. That would make sense, because cache is an important part of the core. Accessing instructions stored in the L1, for example, would take four cycles or, at a stock speed of 3.3GHz, ~1.21ns.Originally Posted by CPU-world.com
Level 1 cache size:
4 x 32 KB 8-way set associative instruction caches
4 x 32 KB 8-way set associative data caches
Level 2 cache size:
4 x 256 KB 8-way set associative caches
Level 3 cache size:
6 MB 12-way set associative shared cache
Cache latency:
4 (L1 cache)
11 (L2 cache)
25 (L3 cache)
(Source: http://www.cpu-world.com/CPUs/Core_i5/Intel-Core%20i5-2500K%20CM8062300833803.html)
Past that, well, I'm lost. The 4x32KiB part (L1) makes sense - that means there are four of these (one per core) with 32768 bytes of memory each. What do "8-way" and "12-way" mean? Is this like RAM channels? If yes, how wide is the bus? Further down on the page, it says each cache level has a "line size" of 64 bytes. Is that a 512-bit bus per "channel?" If yes, then it sounds like - assuming these don't use anything like DDR (double data rate) or QDR (quadruple) - the L3's bandwidth is:
(12 "channels") * (64B / channel) * (3.3GHz) = 2.534TB/s of bandwidth, shared among all four cores.
But I'm not sure if I'm right.
Let's look at another, the good ol' FX-8350:
Quote:
It doesn't give latency numbers. Too bad. Again, we see a "line size," and again, it is 64 bytes. Plugging that into the previous equation and accounting for the additional frequency and 52 channels in the L3 gets us:Originally Posted by CPU-world.com
Level 1 cache size:
4 x 64 KB 2-way set associative shared instruction caches
8 x 16 KB 4-way set associative data caches
Level 2 cache size:
4 x 2 MB 16-way set associative shared exclusive caches
Level 3 cache size:
8 MB 64-way set associative shared cache
(Source: http://www.cpu-world.com/CPUs/Bulldozer/AMD-FX-Series%20FX-8350.html)
(2.534TB/s) * (64 / 12) * (4 / 3.3) = 16.39TB/s of raw bandwidth, shared among all four modules.
Am I on the right track, or am I totally lost? These numbers sound way too high and I might be totally wrong with regards to my interpretation of whatever "##-way associative cache" means.