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Interesting article from Igor's lab


Even on DDR4 boards, there are actually two memory controllers active. I never seen this before on a CPU.

Very interesting and could explain why some boards have issues going past DDR4 3600-3800 for speed since prev gen it was one memory controller per CPU.


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Two memory controllers have been around for a while, I have a second one. Called a cache controller, even though it controls dram. I was hoping that I could get the two controllers on Alder to run out of sync, to reduce overall latency like in Broadwell, but the mixing of the memory modules with controllers for DDR5 makes that look impossible. It was a wistful longshot anyways. Maybe it will work with DDR4?
 

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Twin Turbski
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Interesting article from Igor's lab


Even on DDR4 boards, there are actually two memory controllers active. I never seen this before on a CPU.

Very interesting and could explain why some boards have issues going past DDR4 3600-3800 for speed since prev gen it was one memory controller per CPU.


View attachment 2533916
So I have seen a few members here with this 12900K and quad channel DDR5 memory, with all four slots on the motherboard populated.
How is this possible if the sum total of both IMCs is only two channels?
 

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Discussion Starter · #4 ·
So I have seen a few members here with this 12900K and quad channel DDR5 memory, with all four slots on the motherboard populated.
How is this possible if the sum total of both IMCs is only two channels?
Even 2 dimms DDR5 would be quad since each stick has two channnels. The data path to each channel is only 32bits but bank groups are more isolated with DDR5.

It's not really quad channel since (2x64bits)ddr4 4000+ pushes about 70G/s and (4x32bits)DDR5 ~4800+ is not really double but more around 100Gb/s.
 

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Are z690 boards T-Topology? Seems that would be necessary in this case to keep the memory controllers in sync, no?
 

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Twin Turbski
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Even 2 dimms DDR5 would be quad since each stick has two channnels. The data path to each channel is only 32bits but bank groups are more isolated with DDR5.

It's not really quad channel since (2x64bits)ddr4 4000+ pushes about 70G/s and (4x32bits)DDR5 ~4800+ is not really double but more around 100Gb/s.
Yes it's so shocking they would do this to DDR5. Unconscionable!
To provide an example, my 16 module octal-channel memory setup on one of my dual processor z820 surpasses 107GB/s. So what that means is DDR5 is only twice as fast as DDR3. When we were promised DDR4 we were promised huge leaps in bandwidth with every release. That did not happen. I can't believe into would cripple their best CPU in this way.
 

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Yes it's so shocking they would do this to DDR5. Unconscionable!
To provide an example, my 16 module octal-channel memory setup on one of my dual processor z820 surpasses 107GB/s. So what that means is DDR5 is only twice as fast as DDR3. When we were promised DDR4 we were promised huge leaps in bandwidth with every release. That did not happen. I can't believe into would cripple their best CPU in this way.
They won't cripple Xeons. ;)
 
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