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Source: https://www.kitguru.net/components/cpu/joao-silva/intel-alder-lake-s-p-possible-core-configurations-leaked/

The new leak comes from Coreboot and was shared by Coelacanth’s Dream (via VideoCardz). The leak includes an extensive list totaling 24 possible core configurations for the upcoming Alder Lake-S/P architectures. For those of you who don’t know, Intel Alder Lake is expected to feature a big.SMALL core architecture, similar to ARM processors. The first and second number of the leaked core configurations refers to the big and small cores, while the last number points to the GPU cores.
Pretty interesting core configurations.
 

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LTSC for life crew
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So Intel is making some mobile SOC style chips similar to the snapdragon 855?

I do have to wonder how these will perform in real world usage once they are out and about in people's devices.
 

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So Intel is making some mobile SOC style chips similar to the snapdragon 855?
-S are desktop chips (65-125w)
-SP are high end desktop (165w)
-U are low power mobile (up to 15w typically)
-H are higher power mobile (laptop, up to 45w)
-Y are extra low power (typically 5w)
-W are workstation/server
-P are low power server

So possible core configs for Alder Lake -S/P would mean desktop and either HEDT or server configs. Intel has had plans to go small cores and big cores for a while now. Personally I think it is a great idea. We dont need big fat cores to browse facebook, it would be nice to have a group of Atom level cores for basic tasks like that and then big, fat cores with all the performance for gaming and other heavy tasks. This would also let things like background processes for OS and such run on the "little cores" while a game has dedicated access to the "big cores" so you dont have anything else holding up your processing.
 

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-S are desktop chips (65-125w)
-SP are high end desktop (165w)
-U are low power mobile (up to 15w typically)
-H are higher power mobile (laptop, up to 45w)
-Y are extra low power (typically 5w)
-W are workstation/server
-P are low power server

So possible core configs for Alder Lake -S/P would mean desktop and either HEDT or server configs. Intel has had plans to go small cores and big cores for a while now. Personally I think it is a great idea. We dont need big fat cores to browse facebook, it would be nice to have a group of Atom level cores for basic tasks like that and then big, fat cores with all the performance for gaming and other heavy tasks. This would also let things like background processes for OS and such run on the "little cores" while a game has dedicated access to the "big cores" so you dont have anything else holding up your processing.
So literally exactly how both AMD and Intel CPUs work now with asymmetrical core turbos. No change in practical use.

big.LITTLE only works in extreme low power environments, not in HEDT or Desktop. They would be better served putting more specialized silicon on the die such as adding Quicksync to HEDT than giving precious space to little cores that function worse than low-clocked big cores in an effectively idle-power unlimited environment.

Intel can not afford the silicon/yield budget hit this would give them in environments outside of low-power use cases such as NAS units, ultra-portables, and perhaps web-servers that might also be doable on ARM instead. To waste space like this on anything AMD competes with them on is directly detrimental to making money.
 

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So literally exactly how both AMD and Intel CPUs work now with asymmetrical core turbos. No change in practical use.

big.LITTLE only works in extreme low power environments, not in HEDT or Desktop. They would be better served putting more specialized silicon on the die such as adding Quicksync to HEDT than giving precious space to little cores that function worse than low-clocked big cores in an effectively idle-power unlimited environment.

Intel can not afford the silicon/yield budget hit this would give them in environments outside of low-power use cases such as NAS units, ultra-portables, and perhaps web-servers that might also be doable on ARM instead. To waste space like this on anything AMD competes with them on is directly detrimental to making money.
It is actually taking the dynamic clocking for loads to the next level. Right now you can be running a program and background processes still use execution time, robbing performance from what you want to do. It isnt a problem when you are doing nothing, and cores can clock down for these low loads. But with different core types those background processes dont take any performance away from what you actually want to run because they never request execution time from the main cores.

And Intel isnt the only one doing this/planning on doing this, AMD plans to as well and has a patent to such effect recently. Both companies see this configuration as the future on all platforms.
 

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It is actually taking the dynamic clocking for loads to the next level. Right now you can be running a program and background processes still use execution time, robbing performance from what you want to do. It isnt a problem when you are doing nothing, and cores can clock down for these low loads. But with different core types those background processes dont take any performance away from what you actually want to run because they never request execution time from the main cores.

And Intel isnt the only one doing this/planning on doing this, AMD plans to as well and has a patent to such effect recently. Both companies see this configuration as the future on all platforms.
The power savings are not significant to the overall platform when in a desktop or HEDT environment. In a tablet or a laptop, 3 watts may mean quite a bit, but in a desktop...

This is CPU only;


And this is whole system:


That is a lot of extra silicon for a <10% idle power savings, and right now Intel is at a significant node disadvantage and is stuck on monolithic silicon.

Additionally, what makes you think the "background processes" do not already get offloaded to slow cores? Why would big.LITTLE change that? Set affinity and process priority if you think they don't do so automatically, but you will not see statistically significant changes.

As I said, it makes sense in extreme low power environments where the workload is 90%+ no work with bursts of heavy work, and you really need to get that power consumption down. Like a NAS, Laptop, or Webserver. Not a desktop.
 

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there is still a benefit for desktop, cheaper multi-thread performance.



you can get a 8+8 configuration that would perform at about the level of a 12core chip according to Intel's slides (1sunnyclove core = 2tremont cores).
plus with more raw number of available cores theres more effective room for load spreading, as Enigma mentioned this will reduce core load saturation.
 

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there is still a benefit for desktop, cheaper multi-thread performance.



you can get a 8+8 configuration that would perform at about the level of a 12core chip according to Intel's slides (1sunnyclove core = 2tremont cores).
plus with more raw number of available cores theres more effective room for load spreading, as Enigma mentioned this will reduce core load saturation.
You'll need to forgive me if I do not take Intel's "realistic workloads" claim at face value given recent events.

But, ignoring that for a minute. 1) The atom cores do not take up significantly less space per performance than normal cores do, and that Sunny Cove core is fatter than it needs to be given it still has AVX-512 in there;


And 2) when in a maxed-performance scenario, such as a desktop or HEDT many-core environment that this would theoretically help with, the Atom cores are LESS efficient than Core ones;


Not including that 3) The Atom cores do not have not benefit from the same instruction sets. The Tremont Atom cores do not have even basic AVX. The workloads we need 8+ cores in on PC typically get major performance benefits from these larger instructions sets.

big.LITTLE never was and never will be about performance. It was about power savings, reducing idle and light workload power consumption to extend battery life.
 

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You'll need to forgive me if I do not take Intel's "realistic workloads" claim at face value given recent events.

But, ignoring that for a minute. 1) The atom cores do not take up significantly less space per performance than normal cores do, and that Sunny Cove core is fatter than it needs to be given it still has AVX-512 in there;


And 2) when in a maxed-performance scenario, such as a desktop or HEDT many-core environment that this would theoretically help with, the Atom cores are LESS efficient than Core ones;


Not including that 3) The Atom cores do not have not benefit from the same instruction sets. The Tremont Atom cores do not have even basic AVX. The workloads we need 8+ cores in on PC typically get major performance benefits from these larger instructions sets.

big.LITTLE never was and never will be about performance. It was about power savings, reducing idle and light workload power consumption to extend battery life.
it would be better to understand this chip configuration the other way around, they're enhancing an atom chip with sunny clove cores.

from what i understand of what Anand described of the die shot, thats one sunnyclove core with four tremont cores.
the slide chart you have there is also about single-thread performance, of which we dont really need more than a few fast cores to handle.
https://www.anandtech.com/show/15877/intel-hybrid-cpu-lakefield-all-you-need-to-know/3

At the top is the single Sunny Cove core, also present in Ice Lake. Intel has stated that it has physically removed the AVX-512 part of the silicon, however we can still see it in the die shot.
This is despite the fact that it can’t be used in this design due to one of the main limitations of a hybrid CPU. We’ll cover that more in a later topic.


At the bottom in the middle are the four Tremont Atom cores, which are set to do most of the heavy lifting (that isn’t latency sensitive) in this processor.
It is worth noting the relative sizes of the single Sunny Cove core compared to the four Tremont Atom cores, whereby it seems we could fit around three Tremont cores in the same size as a Sunny Cove.
now with this basis alone, we can see that tremont cores can contribute a lot for multi-thread performance, if we take 1sunny = 2tremont at face value, at worse 2tremont would perform a bit less.


Using a similar power/performance graphs, the effect of having a 1+4 design is quite substantial. On the left is the single core power/performance graphs, but on the right is when we compare 1 Sunny Cove to all 4 Tremont cores working together.
Where the previous graph considered a 1+1 design, which is more relevant in those user experience scenarios listed above, on the right is the 1+4 design for when the user demands a heavier workload that might not be latency critical. Because there are four Atom cores, the blue line multiplies by four in both directions.
now using these tidbits to make a point, 3 tremont is roughly as big as one sunny clove core, which means we can expect "up to" 50% more multi-thread performance from the same die area they occupied.
while we only need four or perhaps eight sunny clove cores to tackle single-thread latency sensitive workloads.

as such stuffing a chip full of tremont cores with 4 or 8 sunny clove cores for single-thread performance will give us the most performance leverage per die area used.
 

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it would be better to understand this chip configuration the other way around, they're enhancing an atom chip with sunny clove cores.

from what i understand of what Anand described of the die shot, thats one sunnyclove core with four tremont cores.
the slide chart you have there is also about single-thread performance, of which we dont really need more than a few fast cores to handle.
https://www.anandtech.com/show/15877/intel-hybrid-cpu-lakefield-all-you-need-to-know/3

now with this basis alone, we can see that tremont cores can contribute a lot for multi-thread performance, if we take 1sunny = 2tremont at face value, at worse 2tremont would perform a bit less.



now using these tidbits to make a point, 3 tremont is roughly as big as one sunny clove core, which means we can expect "up to" 50% more multi-thread performance from the same die area they occupied.
while we only need four or perhaps eight sunny clove cores to tackle single-thread latency sensitive workloads.

as such stuffing a chip full of tremont cores with 4 or 8 sunny clove cores for single-thread performance will give us the most performance leverage per die area used.
Agreed, they are trying to add performance to a low power platform. Not to a high powered one. To clarify further I am only arguing that this is not an appropriate design for desktop and HEDT.

Correct, four Tremont cores are about 60% bigger while offering about 100% more theoretical performance in unlisted software than a single overly fat Sonny Cove core limited to 3Ghz with no hyper-threading. As I said, not significantly better performance per area, and if anything, would actually be perf/area negative in comparison to something like a 9900K.

When Intel says this chip will perform "like a 12-core", what they mean is that it will perform like a 12-core at 3ghz. Atom cores do not scale up like Core does, as evident in their graph, and you are still ignoring all the missing instruction sets that Tremont does not have, as well as the challenges of trying to have an OS schedule for multiple core types in a single system efficiently.

But, on the topic of raw performance, STH thinks it will get about 70% higher performance than a C3558 for the same core count based on Intel's numbers;
https://www.servethehome.com/intel-tremont-low-power-architecture-detailed/

Which would put it at about 80% performance as a Xeon Bronze 3104. A 1.7Ghz no turbo hex core with no hyper-threading. When you compare that to a 10900K, you get 2.8x clock speed, 1.67x cores, 1.2x for HT. Add an extra 1.15x IPC for Sunny Cove, and you'd need about 32 Tremont cores to compete.

At the end of the day, an 8+8 config is barely on par, or perhaps a bit faster, than a theoretical 11900K. If they traded two Sunny Cove cores for eight Tremont cores. That is not a perf/area improvement.

It may be tempting to call it a perf/watt improvement over the 10900k due to it having absurd power numbers, but if you keep the 10900k at stock, you are looking at a total improvement of maybe 15-20w for this 8+8 chip. For the same die space, they could throw on two more cores and down-clock them a bit to save on voltage, get the same performance/power, and not have to deal with all the handicaps of having split core designs.

Provided of course they can get Ring working on 12 cores, which is yet another problem an 8+8 faces. Ready for the dual-ring fun from the older Xeon platforms?

This is a low power design. Not a high performance one. If this type of design could compete in non-low power space, you would see a lot more news articles about ARM stealing high performance server share from Intel and AMD. It is simply not a competitive design compared to AMD's chiplets or even Intel's own Mesh when your power budget is effectively unlimited.
 

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Agreed, they are trying to add performance to a low power platform. Not to a high powered one. To clarify further I am only arguing that this is not an appropriate design for desktop and HEDT.

Correct, four Tremont cores are about 60% bigger while offering about 100% more theoretical performance in unlisted software than a single overly fat Sonny Cove core limited to 3Ghz with no hyper-threading. As I said, not significantly better performance per area, and if anything, would actually be perf/area negative in comparison to something like a 9900K.

When Intel says this chip will perform "like a 12-core", what they mean is that it will perform like a 12-core at 3ghz. Atom cores do not scale up like Core does, as evident in their graph, and you are still ignoring all the missing instruction sets that Tremont does not have, as well as the challenges of trying to have an OS schedule for multiple core types in a single system efficiently.

But, on the topic of raw performance, STH thinks it will get about 70% higher performance than a C3558 for the same core count based on Intel's numbers;
https://www.servethehome.com/intel-tremont-low-power-architecture-detailed/

Which would put it at about 80% performance as a Xeon Bronze 3104. A 1.7Ghz no turbo hex core with no hyper-threading. When you compare that to a 10900K, you get 2.8x clock speed, 1.67x cores, 1.2x for HT. Add an extra 1.15x IPC for Sunny Cove, and you'd need about 32 Tremont cores to compete.

At the end of the day, an 8+8 config is barely on par, or perhaps a bit faster, than a theoretical 11900K. If they traded two Sunny Cove cores for eight Tremont cores. That is not a perf/area improvement.

It may be tempting to call it a perf/watt improvement over the 10900k due to it having absurd power numbers, but if you keep the 10900k at stock, you are looking at a total improvement of maybe 15-20w for this 8+8 chip. For the same die space, they could throw on two more cores and down-clock them a bit to save on voltage, get the same performance/power, and not have to deal with all the handicaps of having split core designs.

Provided of course they can get Ring working on 12 cores, which is yet another problem an 8+8 faces. Ready for the dual-ring fun from the older Xeon platforms?

This is a low power design. Not a high performance one. If this type of design could compete in non-low power space, you would see a lot more news articles about ARM stealing high performance server share from Intel and AMD. It is simply not a competitive design compared to AMD's chiplets or even Intel's own Mesh when your power budget is effectively unlimited.
yes of course, thats why i mentioned it on the first post i made that this configuration can be used for desktops as a cheaper multi-thread performance, with emphasis on "cheap".
to point out we have i3s, pentiums and celerons on the bottom of the desktop stack, of which adding tremont cores can beef up their performance to pull them up to i5 and i7 performance level.

on this topic point, the best configuration would actually be mostly tremont with a few sunny clove, e.g. 2+8 configuration would put it on par with i5 6core chips, yet be cheaper overall.


to be honest though, i would rather want to see Intel and AMD look into higher SMT4 and SMT8 instead like IBM POWER9.
 

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Until today Speedshift/(What ever bull Intel power saving) never worked perfectly, If you monitor your wattage on an OC'd system @ idle it will spike a lot power saving + OC is something we were only dreaming of.

AMD seems to do it better specially after the latest chipset drivers, So I don't see this really working for us that really want to push it to the limit and save power when browsing/office. (Maybe a little bit of lasso)
 

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yes of course, thats why i mentioned it on the first post i made that this configuration can be used for desktops as a cheaper multi-thread performance, with emphasis on "cheap".
to point out we have i3s, pentiums and celerons on the bottom of the desktop stack, of which adding tremont cores can beef up their performance to pull them up to i5 and i7 performance level.

on this topic point, the best configuration would actually be mostly tremont with a few sunny clove, e.g. 2+8 configuration would put it on par with i5 6core chips, yet be cheaper overall.


to be honest though, i would rather want to see Intel and AMD look into higher SMT4 and SMT8 instead like IBM POWER9.
I can agree that 2+8 in a <20w package would make for an excellent NUC/Laptop design for everyone that doesn't need an i7/i9.

Especially with the recent prevalence of GPU acceleration, QuickSync utilization, and Intel's improved iGPUs.

Until today Speedshift/(What ever bull Intel power saving) never worked perfectly, If you monitor your wattage on an OC'd system @ idle it will spike a lot power saving + OC is something we were only dreaming of.

AMD seems to do it better specially after the latest chipset drivers, So I don't see this really working for us that really want to push it to the limit and save power when browsing/office. (Maybe a little bit of lasso)
SpeedStep.

Modern CPU p-states switch so quickly it is effectively impossible to measure the actual draw without dedicated in-line hardware with an extreme polling rate.

They are designed to have those spikes, as most modern CPUs are designed for "Time to Sleep", which is the design theory that if you high-burst your workload to get it done quicker, you can spend more time in low power mode, lowering power consumption overall as compared to a more spread out approach.

And of course the moment you OC a system you can't really complain about stock features that you specifically overwrote anymore. What you are asking for is control over multiple p-states, and while that is an option, its a pretty new thing to CPUs and not available on everything;
https://hardforum.com/threads/ryzen-pstate-overclocking-method-calculation-and-calculator.1928648/
 

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I can agree that 2+8 in a <20w package would make for an excellent NUC/Laptop design for everyone that doesn't need an i7/i9.

Especially with the recent prevalence of GPU acceleration, QuickSync utilization, and Intel's improved iGPUs.



SpeedStep.

Modern CPU p-states switch so quickly it is effectively impossible to measure the actual draw without dedicated in-line hardware with an extreme polling rate.

They are designed to have those spikes, as most modern CPUs are designed for "Time to Sleep", which is the design theory that if you high-burst your workload to get it done quicker, you can spend more time in low power mode, lowering power consumption overall as compared to a more spread out approach.

And of course the moment you OC a system you can't really complain about stock features that you specifically overwrote anymore. What you are asking for is control over multiple p-states, and while that is an option, its a pretty new thing to CPUs and not available on everything;
https://hardforum.com/threads/ryzen-pstate-overclocking-method-calculation-and-calculator.1928648/
Exactly, What my point is why implement this(Hybrid cores) in an S/SP product? is it for OEMs? or are they planning on something else.
 

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So does it mean at the end of the day, Intel Alderlake S desktop cpu, the successor of 10900K, will not be much faster than 10900K? (I'm referring to pure performance standpoint, have no interest in power saving for a high end gaming PC)


I need a very powerful gaming CPU, It will be very sad for intel if what I mentioned is true. Very very sad.
 

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So does it mean at the end of the day, Intel Alderlake S desktop cpu, the successor of 10900K, will not be much faster than 10900K? (I'm referring to pure performance standpoint, have no interest in power saving for a high end gaming PC)


I need a very powerful gaming CPU, It will be very sad for intel if what I mentioned is true. Very very sad.
If Intel can hit 5Ghz+ with Sunny Cove cores, it will be significantly faster in single thread workloads than a 10900K, and the 8+8 config will still offer enough big-boy multithread for the games that can make use of it.

I consider the design wasteful and unneeded in the environments we (OCN members) use, but that doesn't mean it can't perform. This design's existence also does not exclude other non-hybrid designs from existing.
 

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Discussion Starter #17
So does it mean at the end of the day, Intel Alderlake S desktop cpu, the successor of 10900K, will not be much faster than 10900K? (I'm referring to pure performance standpoint, have no interest in power saving for a high end gaming PC)


I need a very powerful gaming CPU, It will be very sad for intel if what I mentioned is true. Very very sad.
Alder Lake is going to be using Golden Cove(4th generation 10nm architecture) cores which are significantly larger than Sunny Cove cores(18% faster IPC than Skylake). Tiger Lake is going to be announced next month which uses Willow Cove cores(25% faster IPC than Skylake) and the frequency looks similar to Comet Lake-u from the leaks.

8 large cores with 25%+ faster IPC will outperform a 10900k when it comes to gaming. Rumors suggest Golden Cove cores are going to have 50% faster IPC than the 10900k.
 

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Alder Lake is going to be using Golden Cove(4th generation 10nm architecture) cores which are significantly larger than Sunny Cove cores(18% faster IPC than Skylake). Tiger Lake is going to be announced next month which uses Willow Cove cores(25% faster IPC than Skylake) and the frequency looks similar to Comet Lake-u from the leaks.

8 large cores with 25%+ faster IPC will outperform a 10900k when it comes to gaming. Rumors suggest Golden Cove cores are going to have 50% faster IPC than the 10900k.
Hope so. Intel needs some good news. I am waiting for that next conroe (intel/amd) before I update from 3950X. That first Gen i7 was one of the best CPU's to buy day one with minimum gains of 50%. I was about to buy an Q6600/AMD CPU when my friend told me about the conroe chipset coming out in one week. I decided to wait and get that instead.
 

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Alder Lake is going to be using Golden Cove(4th generation 10nm architecture) cores which are significantly larger than Sunny Cove cores(18% faster IPC than Skylake). Tiger Lake is going to be announced next month which uses Willow Cove cores(25% faster IPC than Skylake) and the frequency looks similar to Comet Lake-u from the leaks.

8 large cores with 25%+ faster IPC will outperform a 10900k when it comes to gaming. Rumors suggest Golden Cove cores are going to have 50% faster IPC than the 10900k.
Without AMD Zen, I dunno how long is Intel going to feed us with their skylake nonsense.
 
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