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Hello, I have a Maximus II Formula which I would like to use a my computer's motherboard. My P5E still runs, but the top PCI-E 16x is stuck in 8x and a copper trace on the back has peeled off. While it still seems stable, I rather use the MIIF due to this issues.
With the MIIF I am having problem achieving the same 3.6GHz clock with my Q6600. I've been able to successfully boot at 3.2GHz and it appears stable. However, I can only successfully boot the computer if I set 3.2 and then bump up to 3.6GHz. If I restart or the computer crashes, I need to load to defaults in order to POST.
When I am able to boot into Windows at 3.6, LinX always crashes ~5 seconds in and I get the 124 BSOD.
I've increased vCore and FSB Termination Voltage, but neither seemed to make a difference. My current MIIF settings are below. Note the the voltages being used on the MIIF are approximations since I don't recall the exact decimal values and should be the same as the ones used on the P5E.
Code:
With the MIIF I am having problem achieving the same 3.6GHz clock with my Q6600. I've been able to successfully boot at 3.2GHz and it appears stable. However, I can only successfully boot the computer if I set 3.2 and then bump up to 3.6GHz. If I restart or the computer crashes, I need to load to defaults in order to POST.
When I am able to boot into Windows at 3.6, LinX always crashes ~5 seconds in and I get the 124 BSOD.
I've increased vCore and FSB Termination Voltage, but neither seemed to make a difference. My current MIIF settings are below. Note the the voltages being used on the MIIF are approximations since I don't recall the exact decimal values and should be the same as the ones used on the P5E.
Code:
Code:
Extreme Tweaker
Ai Overclock Tuner : Manual
OC From CPU Level Up : AUTO
Ratio CMOS Setting : 9
FSB Frequency : 400
CPU Clock Skew : AUTO
NB Clock Skew : AUTO
FSB Strap to North Bridge : 400
DRAM Frequency: 800
DRAM CLK Skew On Channel A1: AUTO
DRAM CLK Skew On Channel A2: AUTO
DRAM CLK Skew On Channel B1: AUTO
DRAM CLK Skew On Channel B2: AUTO
DRAM Timing Control: Manual
CAS# Latency : 5
RAS# to CAS# Delay : 5
RAS# Precharge : 5
RAS# Activate to Precha : 15
RAS# to RAS# Delay : AUTO
Row Refresh Cycle Time : AUTO
Write Recovery Time : AUTO
Read to Precharge Time : AUTO
Read to Write Delay (S/D) : AUTO
Write to Read Delay (S) : AUTO
Write to Read Delay (D) : AUTO
Read to Read Delay (S) : AUTO
Read to Read Delay (D) : AUTO
Write to Write Delay (S) : AUTO
Write to Write Delay (D) : AUTO
Write to Pre Delay : Auto
Read to Pre Delay : Auto
Pre to Pre Delay : Auto
All Pre to act Delay : Auto
All Pre to Ref Delay : Auto
DRAM Static Read Control: Disabled
Dram Read Training : Auto
Mem. OC Charger : Auto
Ai Clock Twister : AUTO
Transaction Booster : AUTO
PCIE Freguency : 100
CPU Voltage : 1.35
CPU PLL Voltage : 1.6
FSB Termination Voltage : 1.4
DRAM Voltage : 2.0
North Bridge Voltage : 1.45
South Bridge 1.5 Voltage : 1.5
South Bridge 1.1 Voltage : 1.1
CPU GTL Reference (0) : AUTO
CPU GTL Reference (1) : AUTO
CPU GTL Reference (2) : AUTO
CPU GTL Reference (3) : AUTO
NB GTL Reference : AUTO
DDR2 ChA Reference Voltage : AUTO
DDR2 ChB Reference Voltage : AUTO
North Bridge DDR Reference :AUTO
CPU Configuration
Ratio CMOS Setting : 9
C1E Suppport : Disabled
Max CPUID Value Limit : Disabled
Intel (R) Virtualization Tech. : Disabled
CPU Disable Bit : Disabled
Execute Disable Bit : Disabled
Intel (R) Speed Step (tm) Tech : Disabled
Load-Line Calibration :
CPU Spread Spectrum : Disabled
PCIE Spread Spectrum : Disabled