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Discussion Starter · #1 ·
ok just a quick question here. I know that when looking for memory, generally lower CAS latency means that the memory should be quicker. But what about the timings of the RAM.

For example, this RAM has CAS latency of 7 and timings of 7-7-7-20
http://www.newegg.com/Product/Produc...82E16820146871

but this RAM has CAS latency of 7 also but timings of 7-7-6-18.
http://www.newegg.com/Product/Produc...82E16820146799

does that mean the kit with the lower timings should also be faster or can someone please clarify what the timings mean on the memory and why they r sometimes differnt. Also what do the first 3 numbers mean in the timings compared to the last one? Thanks for the replies
 

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Basically, the first number has the biggest impact on performance, and the last number has the least impact.
 

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Typical timing parameters appear as 2-3-2-6-T1 or some variant. So what do these numbers mean?

Before delving into these specific settings, let's first define some common terms used when discussing memory timings.
RAS - Row Address Strobe or Row Address Select
CAS - Column Address Strobe or Column Address Select
tRAS - Active to precharge delay; this is the delay between the precharge and activation of a row
tRCD - RAS to CAS Delay; the time required between RAS and CAS access
tCL - (or CL) CAS Latency
tRP - RAS Precharge; the time required to switch from one row to the next row, for example, switch internal memory banks
tCLK - ClocK; the length of a clock cycle
Command Rate - the delay between Chip Select (CS), or when an IC is selected and the time commands can be issued to the IC
Latency - The time from when a request is made to when it is answered; the total time required before data can be written to or read from the memory.
Some of the above terms are more important to system stability and performance than others. However, to understand the whole, it is important to understand the role of each of these settings/signals. Therefore, the numbers 2-3-2-6-T1 refer to CL-tRCD-tRP-tRAS-Command Rate and are measured in clock cycles.

tRAS
Memory architecture is like a spreadsheet with row upon row and column upon column, with each row being one bank. For the CPU to access memory, it first must determine which row or bank in the memory is to be accessed and then activate that row with the RAS signal. Once activated, the row can be accessed over and over, until the data is exhausted. This is why tRAS has little effect on overall system performance but could impact system stability if set incorrectly.

tRCD
tRCD is the delay from the time a row is activated to when the cell (or column) is activated via the CAS signal and data can be written to or read from a memory cell. When memory is accessed sequentially, the row is already active and tRCD will not have much impact. However, if memory is not accessed in a linear fashion, the current active row must be deactivated and then a new row selected/activated. In such an example, low tRCD's can improve performance. However, like any other memory timing, putting this too low for the module can cause in instability.

CAS Latency
Certainly, one of the most important timings is the CAS Latency, which is also the one most people understand. Since data is often accessed sequentially (same row), the CPU need only select the next column in the row to get the next piece of data. In other words, CAS Latency is the delay between the CAS signal and the availability of valid data on the data pins (DQ). The latency between column accesses (CAS) then plays an important role in the performance of the memory. The lower the latency, the better the performance. However, the memory modules must be able to support low-latency settings.

tRP
tRP is the time required to terminate one row access and begin the next row access. tRP might also be seen as the delay required between deactivating the current row and selecting the next row. So in conjunction with tRCD, the time required (or clock cycles required) to switch banks (or rows) and select the next cell for reading, writing, or refreshing is a combination of tRP and tRCD.

tRAS
tRAS is the time required before (or delay needed) between the active and precharge commands. In other words, how long the memory must wait before the next memory access can begin.

tCLK
This is simply the clock used for the memory. Note that because frequency is 1/t, if memory were running at 100Mhz, the timing of the memory would be 1/100Mhz, or 10nS.

Command Rate
The Command Rate is the time needed between the chip select signal and when commands can be issued to the RAM module IC. Typically, these are either 1 clock or 2.

Link.
 

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Discussion Starter · #4 ·
ok thanks for all the valuable information. REP'd. But i am still a little unsure of what the actual numbers mean. When looking at RAM timings, if the timings are lower than another set of timings, does that mean that a particular set of RAM would be faster/slower? Or are timings just not really considered that big of a deal like CAS latency is.
 

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Yes lower is always better if all else is the same. Real world? No. It also depends on the application.

Between those two you linked you would be hard pressed to be able to perceive a difference. I mean unless you can perceive ns? I would save the $20.

OK the first 7 vs 6 is the:

tRP
tRP is the time required to terminate one row access and begin the next row access. tRP might also be seen as the delay required between deactivating the current row and selecting the next row. So in conjunction with tRCD, the time required (or clock cycles required) to switch banks (or rows) and select the next cell for reading, writing, or refreshing is a combination of tRP and tRCD.

What does this mean? I don't know. Could matter more on some than others. Consider that 6 to 7 is a 14% improvement. But consider it may be 2% of the total equation. So what is 14% of 2% in the total equation? Not much. Same with 18 vs 20? What a 9% improvement? 9% of what?

Buy the cheaper.
 
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