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Yep it is lower, but I'm aiming to shave voltage and heat with my drop to 3466 tests.

I did have to go to 1.1V SOC for my 3733 stable settings, from 3600 where I was 1.05V.

But here I've kept to 1.05V so far. Still, I'm pushing semi-tight values here, and I'm holding out stubbornly :) but this is on my list to try 1.10V SOC if I can't get stability with other timings tweaks.

I'm trying my best to treat the late-error symptom as a tRFC timing issue lol. I proved to myself that tRTP=6 (half of tWR=12) was just too aggressive, as I got quick errors with that. So I'm trying tRFC=294 (7*tRC), even though it's a tightening from tRFC=336. I'm also stubbornly holding my ground on flat 14's at 3466 so I'm thinking it means I may have to loosen elsewhere, including tRC and/or tRFC? Am I barking up the wrong tree?
The timings you saw are stable 100% sure - they do work :D
The issue is , why can't you run them :)
Here something more lightweight, but 10% slower
If even that one fails, i would be worried that something clearly is messed up
Well i'd be worried already if you can't even run the harsh 3467 ones :eek:
Try to get that to work, before you dive too deep into the debugging rabbit hole and try to find out of 20 settings something that works :eek:

I guess a combination of voltage, RTT and CAD_BUS is your issue
well about vSOC:
We shouldn't compare 14nm zen IMC voltage scaling, with 12nm zen+ & so also 3rd gen voltage scaling :eek:

14nm:
2934MT/s =1.0125-1.025vSOC
3200MT/s = 1.0325-1.0475vSOC
3300MT/s = 1.05-1.065vSOC
3400MT/s = 1.072-1.089vSOC
3467MT/s = 1.075-1.1vSOC
3600MT/s = >1.175vSOC
anything above 1.1 had negative scalling, 20mV vSOC = 25-30W TDP bump
* maximum frequency 3467MT/s hittable only <53.3Ω procODT
12nm:
2933-3200MT/s = 0.098-1.0125vSOC
3334-3400MT/s = 1.025-1.0325vSOC
3467-3600MT/s = 1.042-1.055vSOC
3667-3734MT/s = 1.068-1.089vSOC
3800MT/s = >1.15vSOC
anything above 1.125 had negative scaling, 50mV = 35-40W TDP bump
* maximum frequency 3734MT/s hittable only <48Ω procODT

** both use 8 core for TDP bump comparison
3rd gen is pretty much identical in scaling
* maximum frequency 3800MT/s hittable only < 36.9Ω procODT, rarely 40Ω

Less remains more, on every voltage and resistance you apply :handlebar
Look up the DRAM OC leaderboard for rare's result, about what the minimum is for 3rd gen
https://docs.google.com/spreadsheets/d/1HKPVfDcFO-aieAOXHFQZp15rwWadbPTVDNgO8vtyDCM/edit#gid=509536383
Although his vSOC is high ~ likely his CCX OC needed it, and he used 50mV instead of 75mV scaling
 

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As for voltage, is that really a thing? Needing more over time?
Yes, I first notice ram life aging and record in this thread = https://www.overclock.net/forum/13-amd-general/1640919-new-dram-calculator-ryzena-1-7-3-overclocking-dram-am4-membench-0-8-dram-bench-821.html#post28489844

It also happens to SOC both my zen-1 and now zen-2. i.e. SOC 1.05v pass TM5 3 cycles only and 1usmus easy, (didn't want to waste electricity bills), game is my ultimate pass/fail. Anyway, managed to game for one week or 10 days may be and game crash return for a couple of days continuous then change timing change this and change that, ultimately up the SOC 1.0625v and all OK return to 3600 fast no more crash. New chip 1.5 months baby just entered childhood still growing.

Yes, my older AMD Phenom II didn't experience grow like this, only Zen I think......
 

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Here something more lightweight, but 10% slower...If even that one fails, i would be worried that something clearly is messed up.
Well i'd be worried already if you can't even run the harsh 3467 ones :eek:
I guess a combination of voltage, RTT and CAD_BUS is your issue
Yes, and so this is a rabbit hole. My stable 3733cl16 ran 60ohms on both procODT and RTT_Park. But I'm trying to not increase resistances again since it feels like that would worsen my voltage requirements? Tho, I'm already high on DRAM voltage now again.

Thanks for the vSOC info. :) And note that 3800 is generally procODT < 40ohms.

Question: Please teach me the importance of tRDWR/tWRRD at 6/3 vs 7/1 or 8/1? You previously mentioned SR B-Dies can commonly do 8/1. And 7/1 for CL14 naturally. And you mentioned 6/3. The engineer in me wants to understand the technical "why".

Also behind that same link, you mentioned an imagined timing for SR B-dies of 14-14-14-14-28-32. did you mean 42? Or really imply to shave tRC down that much, to 32?

Look up the DRAM OC leaderboard for rare's result, about what the minimum is for 3rd gen[/COLOR]
The bottom of this spreadsheet has me looking at only three results at 3200 and 3533 combined. Only one (Reous) did 14 at primary timings -- but still not flat. And his tRC was loosened significantly to 46 and tRFC to 416. Charts don't expose subtimings which I'd like so I can more easily deduce what I need to find stability.

I really want to know what tiny little difference is making Test 2 fail. :eek:

I'll test tRDWR/tWRRD at 6/3 (update: can't post with these), in case that's a looser timing from 7/1. And then I'll try your new preset. The new has me changing:
  • tighter tRRDL (to 4)
  • looser tWR (to 16)
  • tighter SCLs (to 3, which was there in the other preset but I stayed at 4 based on testing)
  • tCKE to 16 (wow, really?)
  • procODT looser to 53.3 (that's a huge jump back)
  • 24/20/20/24 aka ClkDrvStr back to 24 (from 40) and CsOdtDrvStr to 20 (never tried this, always been at 24)
  • Setting RTT_NOM to RZQ/7(34) which I've never set before (always off)
That's quite a few things changing. Why the changes to RTT, and tCKE, in particular?
 

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@Veii - so, about tRDWR and tWRRD... I found 6/3 won't let me post. It has to be 8/1 or 7/1.
 

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Run it in Windows, then compare. :rolleyes:
We have ready discussed this and you said you used another linux distro and did not achieve lower results. If I can do as close as a theardripper 3000 series in blender using arch linux which is a much better system than Windows. Then, no.
 

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Hi @Veii, i ditched my micron b dies for a brand new shiny crucial ballistix kits ^^

a little help i would appreciate a lot ^^

can you detect what is the PCB of my kits?

what is the error 12 is usually related to?

which timings should i concentrate on what basis should I follow? my friend told me to try 1.42v 3533 cl14-18-14-34-56 and it seems to work outright albeit errors on test 12

(my mobo is a gigabyte b450 gaming x with 4 dimm slots and my cpu is 2700x, to remind)

i also checked the ram's heat spreader with my hand, it is relatively stays cooler compared to my old vengeance lpx kits at this voltage, just a fyi

my friend also says setting CADBUS addrCMd/csodt/cke to 55-55-55 would let me turn off GDM with stability. is it true? is it safe? i dont nothing about those three and i never meddled with them so i wondered :eek:

---

oh and for an update: i got a refund on crap cjr kits... :specool:
 

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Hi @Veii, i ditched my micron b dies for a brand new shiny crucial ballistix kits ^^

a little help i would appreciate a lot ^^

can you detect what is the PCB of my kits?

what is the error 12 is usually related to?

which timings should i concentrate on what basis should I follow? my friend told me to try 1.42v 3533 cl14-18-14-34-56 and it seems to work outright albeit errors on test 12

(my mobo is a gigabyte b450 gaming x with 4 dimm slots and my cpu is 2700x, to remind)

i also checked the ram's heat spreader with my hand, it is relatively stays cooler compared to my old vengeance lpx kits at this voltage, just a fyi

my friend also says setting CADBUS addrCMd/csodt/cke to 55-55-55 would let me turn off GDM with stability. is it true? is it safe? i dont nothing about those three and i never meddled with them so i wondered :eek:

---

oh and for an update: i got a refund on crap cjr kits... :specool:
My Micron Rev.E [D9VPP] liked procODT 36.9Ohm setting, GDM:disabled [60-20-20-20/60-20-24-24] CAD_BUS on X570 & Ryzen 3000. [4x8GB CL13 3800Mhz]
My Ryzen 1700 B350 board needed 43.6Ohm procODT with same kit of memory.[4x8GB 3733Mhz]

[RZQ/7][RZQ/3][RZQ/1] should be ok.
 

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Hi @Veii, i ditched my micron b dies for a brand new shiny crucial ballistix kits ^^
a little help i would appreciate a lot ^^
Hello ^^
try to drop procODT one step down to 48Ω
tRP would feel better at 16
Match tWR inside that range

Don't have to follow 1 rule, but should try to be inside all of them
higher than rec, near or lower than Alt.1 , at least > Alt.2
can you detect what is the PCB of my kits?
Sadly no, ICs are on the other side
We need a closeup from the side or the bottom and a center shot
Single Rank has them placed on one side, Dual rank on both
Height of the ICs and center of the PCB is important
For reference:


~ by Guizan33
what is the error 12 is usually related to?
Comes together with error 6 at the start = Impedance error, procODT and/or CAD_BUS
Error 12 after time, is heat vdroop on vSOC line or VDDP droop while testing (cpu vddp)
Error 6 belongs to voltage/IMC Limit ~ CAD_BUS and cLDO_VDDP
which timings should i concentrate on what basis should I follow? my friend told me to try 1.42v 3533 cl14-18-14-34-56 and it seems to work outright albeit errors on test 12
(my mobo is a gigabyte b450 gaming x with 4 dimm slots and my cpu is 2700x, to remind)
It's been some time :)
Try this tiny writeup
https://www.overclock.net/forum/10-amd-cpus/1628751-official-amd-ryzen-ddr4-24-7-memory-stability-thread-378.html#post28482232
Don't drop tRC -2 on 4 dimms
Add tRDWR +1 not -1 as "lowest" else tRCD RD/2 +1 for stability without the need for tWRRD (1)
tRCD RD/2 = tRDWR on 4 dimms needs usage of tWRRD, no -1 possible
~ although micron Rev E have exceptions here
Lower tRDWR remains better, but either it works or it's too low

my friend also says setting CADBUS addrCMd/csodt/cke to 55-55-55 would let me turn off GDM with stability. is it true? is it safe? i dont nothing about those three and i never meddled with them so i wondered :eek:
Used them on my old HynixMFR
I think it was 52-52-52, Use that one only as last resort
It adds latency and scales by used frequency
between 50-58 is what you look for, but use it only as the last option after setting everything incl voltages
It's a bit recommended for higher vDIMM, although i doubt you would exceed 1.5v at all
oh and for an update: i got a refund on crap cjr kits... :specool:
Congrats :thumb:
Sad that yours where cr*p, CJR aren't thaat bad just require a bit more work
Anyways, happy that you have a new toy
Push ClkDrStrngh on Micron kits like Nighthog suggested :)
40ish should be fine, they aren't dual rank after all
How about:
Will that work out ?
 

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i will try all your suggestions, thank you alot

my SOC temp is quite cool relatively, its maximum 50 degrees. same for the test im using it right now

so i guess the "vddp" droops then? is there anyway to mitigate it or is it simply board sucks at that?

my vddp is fixed to 0.700 by your suggestions till the ancient times :D

in some of the tries, i also got mixed error 6 and error 12 as you said, but usually only error 12


i also provided my voltages and temps

--

update

i've settled on 3466 cl14 as my basis and i will continue to move on from here

i tried turning gdm off with auto cadbusses, no boot

i tried 55-55-55 and voila, im in desktop now

is these 55-55-55 are harmful in anyway , do they increase heat or what are they exactly? is 55-55-55 a safe value for them?

should i use gdm off 55-55-55 or gdm on auto-auto-auto?

---

second update,

https://prnt.sc/sxampk

here is what i'm trying now.

i think my tWR is not coherent to your ruleset. will fix it later :eek:
 

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Did you update tRFC2/4 from the tRFC calculator?

Because I've just found out that was the reason I got so unusual variance testing different tRFC values. Hours wasted.
I've read multiple times with Ryzen 3000 that tRFC2/4 are not used/relevant but it's simply not true... :mad:
Plugged in the correct values from the calculator and got immediately back the normal consistency in Sandra MT, including better CB20 results and stable throughput in CPU-z bench.
Yep.
 

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We have ready discussed this and you said you used another linux distro and did not achieve lower results. If I can do as close as a theardripper 3000 series in blender using arch linux which is a much better system than Windows. Then, no.
Linux is not a much better OS, it is just a different OS. it does somethings better than Windows, and somethings not as well as Windows.

Blender does really well in Linux, and not so well on Mac and Windows. With Blender, you can't really compare benches between OS's because of how the application is written.
 

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@Veii

Made a little progress yesterday.

I tired 1-5-5-1-7-7-1, but I will have to try again today as I can't tell if I really had a better result or a worse result. I was able to get SCL running at 2 without any issue. In the screenshot with the HCI memtests there is an open text file with all the profiles settings.

Can you (or anyone) explain how VDDP voltage may help lower timings?

My panned next steps are to try to push tRP down, then tune tRFC

Edit: Forgot to add the blender bench. 235.32s blender classroom. https://opendata.blender.org/benchmarks/0d463923-9266-4fef-8efb-0e7f202aa8ea/ ; which officially takes the #1 spot on for a Windows 3950X CPU Classroom run. Gotcha @KedarWolf :D

https://opendata.blender.org/benchmarks/query/?device_name=AMD Ryzen 9 3950X 16-Core Processor&device_type=CPU&os=Windows&benchmark=classroom&blender_version=2.82
 

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@Veii

Made a little progress yesterday.

I tired 1-5-5-1-7-7-1, but I will have to try again today as I can't tell if I really had a better result or a worse result. I was able to get SCL running at 2 without any issue. In the screenshot with the HCI memtests there is an open text file with all the profiles settings.

Can you (or anyone) explain how VDDP voltage may help lower timings?

My panned next steps are to try to push tRP down, then tune tRFC

Edit: Forgot to add the blender bench. 235.32s blender classroom. https://opendata.blender.org/benchmarks/0d463923-9266-4fef-8efb-0e7f202aa8ea/ ; which officially takes the #1 spot on for a Windows 3950X CPU Classroom run. Gotcha @KedarWolf :D


With 2.81 I got 2:34.49

https://opendata.blender.org/benchmarks/433f982d-6c7f-45a5-85cc-758dbe935d32/ :D

Edit: Never mind, I never sorted it right. :(
 

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How do you guys handle vdroop with LLC? I have both CPU and SOC LLC's set to High, I can go to Extreme or back on Auto?

During TM5 testing:
I'm seeing CPU Core Voltage (SVI2 TFN) average 1.267V but I requested 1.275V (for fixed 4.0Ghz, no boosts, during mem testing).
And I see SoC Voltage (SVI2 TFN) average 1.043V but I requested 1.05V

I'm wondering if this is pinching me off during TM5 tests. I'm repeatedly failing Test 2 after a handful of cycles (or many cycles) when it's not something related to immediate failures. I'm fairly confident in my tRFC as I've primarily tested with a multiple of tRC, tRTP, tWR.
 

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How do you guys handle vdroop with LLC? I have both CPU and SOC LLC's set to High, I can go to Extreme or back on Auto?

During TM5 testing:
I'm seeing CPU Core Voltage (SVI2 TFN) average 1.267V but I requested 1.275V (for fixed 4.0Ghz, no boosts, during mem testing).
And I see SoC Voltage (SVI2 TFN) average 1.043V but I requested 1.05V

I'm wondering if this is pinching me off during TM5 tests. I'm repeatedly failing Test 2 after a handful of cycles (or many cycles) when it's not something related to immediate failures. I'm fairly confident in my tRFC as I've primarily tested with a multiple of tRC, tRTP, tWR.
I see no mention of testing with a different tRP than 8

:D

Regards LLC, as long as the voltage after droop is where you want it to be it should not be the reason for your issues.

Having no droop is probably less desirable, I have my LLC at 3, from a scale of 1 to 8 with 1 being no droop and 8 being a lot of it

:p

Do you have any options for changing the switching frequency for SOC/DIMM/CPU ?
 

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I see no mention of testing with a different tRP than 8 :D

Regards LLC, as long as the voltage after droop is where you want it to be it should not be the reason for your issues.

Having no droop is probably less desirable, I have my LLC at 3, from a scale of 1 to 8 with 1 being no droop and 8 being a lot of it :p

Do you have any options for changing the switching frequency for SOC/DIMM/CPU ?
I believe you typo'd but mean tRTP, and yeah I've tried 6, as half of tWR. But it got me to errors fast (in cycle 2, Test 6). And thanks for your fast reply.

I don't know what LLC 3 means for your board. I'll assume some level of moderate vdroop correction (voltage increase) I assume. My last asrock board (z87) had numbers. So, on mine, I can choose Auto, Regular, Medium, High, Extreme.

So the question remains, do I push Extreme and do my best to prevent any droop? Or correct it with slightly altered voltages (+.1V each?) across the board? Is it a non issue?

And, forgive me - what do you mean "the switching frequency"? :)
 

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I believe you typo'd but mean tRTP, and yeah I've tried 6, as half of tWR. But it got me to errors fast (in cycle 2, Test 6). And thanks for your fast reply.

I don't know what LLC 3 means for your board. I'll assume some level of moderate vdroop correction (voltage increase) I assume. My last asrock board (z87) had numbers. So, on mine, I can choose Auto, Regular, Medium, High, Extreme.

So the question remains, do I push Extreme and do my best to prevent any droop? Or correct it with slightly altered voltages (+.1V each?) across the board? Is it a non issue?

And, forgive me - what do you mean "the switching frequency"? :)
You need to go up not down

:D

Sorry, you didn't understand my LLC scaling explanation

LLC 1 is no droop, LLC 8 is a lot of droop

I keep mine on 3 as I want some droop, but not a lot (image below shows my LLC when I was using PBO, I wanted more droop as it assisted single core clocks ...)

Hope that is clearer …

See image for "switching frequency"
 

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