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For the timings look at other B-Die configurations similar to yours in the spreadsheets:


Okay I will do that. This is what I'm currently running off of.


2465898
 

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Old crazy guy
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Okay I will do that. This is what I'm currently running off of.


View attachment 2465898
I'd check if you can use 14 for tRCDRD; it could need more voltage.
Then look for the lowest tRFC you can set, it's strictly dependent on voltage.
Better if a multiplier of CL at 14 eg. 14x18 = 252
Low like that will probably require 1.5V or more.
But 14 x 20 = 280 will probably need 1.45V or less.

And use the tRFC calculator to set the proper tRFC2/4 values or the latency will suffer.
 
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Not more than that
Look on twitter for Shimizu_OC
He is the recent new partner and now freelancer Overclocker , for MSI
Near december was mentioned, and MSI teased for the 20th something
It's unclear if they launch both boards at the same time. Only the B550 Unify non X was teased
@Veii and @ManniX-ITA , starting today B550 Unify-X was listed by some finnish retailer.


You guys think it's coming, at last ? :)
 

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I hope so but I'm still hawking for a 5950x :p
Tbh, thinking at a 5950x too, yet I don't know if I'll be able to get over the mediocre boosts of the second chiplet. I looked alot at both 5950x and 5900x, all the reviews shown that the second chiplet is really low binned, so it feels like a rip-off.
 

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Tbh, thinking at a 5950x too, yet I don't know if I'll be able to get over the mediocre boosts of the second chiplet. I looked alot at both 5950x and 5900x, all the reviews shown that the second chiplet is really low binned, so it feels like a rip-off.
Yes I expected that.
Didn't look a lot lately but mostly seems that also the second CCD can be clocked at 4.7-4.8 in most cases which would be awesome.
For PBO thanks to the curve optimization per core it should be less of a problem.
 

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In all honesty, I am sad they didn't do an XT version of the 5800, I would've bought it in a split of a second. All this "we'll give you one decent CCD but you know, the 2nd is mediocre" is making me puke.
 

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No problem, I don't think you're being rude at all. But I don't think you're reading my post because you keep telling me to stabilize my 3733 MHz and I've told you a few times already that it is stable.

I just don't get why I needed more voltage to stabilize 3733 MHz on my 3900X than Indo on my 5900X. I don't get why my 3900X can't boot 3800 MHz no matter what I tried and did and my 5900X can, and quite easily.

My point is, there are limitations to what my 5900X can do with ram that my 3900X can't. My question is, why?
I missed that point - because i read "it wasn't stable till 1.49v" or something similar. My bad~
To spoil a bit, my 5600X struggled to hit 1900 FCLK at the very start. It did work work with higher procODT then should be needed ~ near 48-53 region
I didn't want to touch on this topic, as i was investigating how VDDG voltages scale this time with procODT and where the ranges are now (we can go to procODT 480ohm after all)
Seeing on soo many zentimings readouts of Vermeer , all with identical cLDO_VDDP = cLDO_VDDG (usually an issue)
Something was different.
Didn't want to touch on this topic , till i figure out what changed ~ instead of spreading missinformation

Nearly all Matisse samples can stabilize 1900FCLK @ cLDO_VDDP 1000mV, cLDO_VDDG CCD 1050, IOD 1150, SOC 1200mV
But this is borderline high voltage which can degrade the fabric quite fast if the voltage peaks a subtle bit or you run beyond 48ohm proc
High impedance and high current = bad experience to the fabric
Soo i can not recommend this at all ~ but Matisse and Renoir purely on the IMC side are not different ~ just around it changed. Same story for the 2700X and 3700X :)

On Matisse you can try to see if you get even to the bios , by using a SOC loadline 1 under flat (flat will overshoot and degrade it)
If that with procODT near 36-42ohm posts, just to the bios without any load ~ then you can scale down and likely need a bit more procODT and more SOC current to begin with.
But close to every Matisse unit can hit 1900FCLK. They could go beyond that, but other issues came with it.
Soo because of marketing and PCIe 4.0 user experience, it was hard locked
Although still, nearly all if not all 3rd gens should be able to run 1900FCLK.
If you can't get it to post at all with whatever options ,then maybe PSP Firmware wasn't updated.
Speaking of PSP Firmware ~ a 3950X was in coma by a bad OC which pretty much made the CPU report "dead memory controller" and refuse to post ~ till put on another board with higher major AGESA
Same apparantly was for my 1700X ~ but this poor little thing had many confusions and low level self-resets :D

I focused on the 3734, as the difference should be bigger than you report
It would be good to get the same set stable at 3800MT/
a tRCD_RD bump of +1 (15 instead 14) is a very big difference. a tCL difference of 2 is not such a big one
If 3800 tRCD_RD 14 can not work, and a set of tRCD_WR 7 tRCD_RD 15 (GMD off) or 8-16 (GDM on) doesn't work.
The tRCD_RD 14 set will continue to be better ~ even at lower frequency

⚠ oh if you ever want to try this high voltages above, do not use procODT 53-60ohm.
The IMC will not like high SOC and high procODT.
Couple AGESA's ago, there was a bug which pushed cLDO_VDDP as 1150mV
Combined with a bug where procODT 60ohm was loaded by using XMP or pushing beyond 3600MT/s
~ result in couple of dead units, but where luckily warranty covered
The reason was, if your VDDP is already 1150, VDDG can be as absolute minimum 1200 (beyond 1150mV is strongly damaging) and SOC can be as absolute minimum 1250 here

"and my 5900X can, and quite easily"
~ well my could not before the new patches. It seems to be a voltage settings missmatch,
but i won't spread unclear information why and why not on this topic so far, till i figure out what's the current optimal set of voltages :)
Many still wait for the "better Patch C" or "Pre Release Patch D" 1.1.0.0 Agesa
 

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@Veii and @ManniX-ITA , starting today B550 Unify-X was listed by some finnish retailer.


You guys think it's coming, at last ? :)
309-319€ for EU
This is for Austria, once they actually get the slock back
and Norway
Bit on the expensive side. Should move in the 259-275€ region. Sadly i have to pass on it for now
Hi @all,

I'm pretty new to this topic and also new to Ryzen platform but coming here for as a last chance before RMA, requesting some help that I would really apreciate for sure ;)

After following so many guidelines and reading so many posts about how to stabilice memory on Ryzen I can't make my system RAM to run fully stable. Many many days and weeks of testing.

Tried even at the lowest speed 2400mhz with all on Auto but it keeps firing some error in stress tests, sometimes just some minutes after the begining of the test and other times after hours wihout any error. On average same number of errors occurs at 2400 and other speeds like XMP 3200 or higher 3466.

These are the specs of the system:
  • MB: MSI B450M-MORTAR-MAX
  • CPU: Ryzen 5 3600
  • RAM: HX432C16FB3AK2/32 (Kingston HyperX Fury RGB DDR4 3200Mhz PC-25600 32GB 2x16GB CL16)
Notice that memory is supported in the QVL of the MB at rated speeds.

I'm doing the testing using: LinpackXtreme-1.1.3, TestMem5 v0.12 (best configs) using [email protected], Prime95 Small FFT, Large, Blend Custom, Memtest...

So far the most stable configuration with least number of errors is this one:

The errors that appears in TestMem5 v0.12 (best configs) using [email protected]:

Any help will be really appreciated. Let me know if you need to add more details about any configuration or something.

Thank you!!!!
If anta's config did not change much, error 2 should still be a timeout issue
tRFC, tRDWR, tWRRD
"Crash on mirrormove big data size"
"copy from one bank to another" or "copy from one dimm to another"up to how the config is set up to test
~ timeout issue non there less

ProcODT 48 is too high for "just 1050mV" vSOC
Take a read on the bottom half of this post
If VDDP on the main menu is CPU VDDP, then it should be 900
If it's cLDO_VDDP , then you need to take care of the voltage stepping between VDDP-VDDG-SOC
925mV cLDO_VDDP and 1050 SOC - means VDDG could be at best 62.5mV. Or if the bios is inteligent it would push VDDG CCD to 975 and IOD to 1000mV
You can try applying this two voltages on VDDG and drop procODT to 32-36 range,. Maaybe 42ohm could be just enough ~ up to how SOC Loadline behaves on auto
It's better if you use a lower procODT and fix SOC loadline at 1 under flat

Then also manually set tRC as 75 and use tRFC 600-446-214 (for 1/2/4)
If this isn't stable at 1.42v memory voltage - then something is not correct with your setup
Try the voltage patterns first, see if it's cpu related - if not maybe RMA your RAM :)
 

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"and my 5900X can, and quite easily"
~ well my could not before the new patches. It seems to be a voltage settings missmatch,
but i won't spread unclear information why and why not on this topic so far, till i figure out what's the current optimal set of voltages :)
Many still wait for the "better Patch C" or "Pre Release Patch D" 1.1.0.0 Agesa
Okay, this makes my a bit concerned. I am using a ASUS CH8, so I'm hoping the voltages are being reported correctly. I posted my Zentimings earlier and they seem safe right?

A user above recommended I play with tRFC and try to get it lower.

 

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Okay, this makes my a bit concerned. I am using a ASUS CH8, so I'm hoping the voltages are being reported correctly. I posted my Zentimings earlier and they seem safe right?

A user above recommended I play with tRFC and try to get it lower.

It should be just a configuation issue. IMC is still bad - but it should be able to run in the region of 2100~2200 after we get 1100 Patch D to every board
You have a lot of playroom on tRC, tRRD_
Get SiSoftware Sandra - run the "multicore efficiency test" with this set
Filter at the bottom to local results , and when you optimize this set , always compare the "latency curve" the ~detailed view~ what set looks to run better
Aida64 doesn't tell the whole story

Using tRFC mini so far has not lead to any issues. (not even one "doesn's work" report, but it's a simple tool) :giggle:
The timings copied from 1usmus calculator are perfect - but if you change one little thing, they will not be in sync.
Using timely triggered tRFC (mini sheet shows the range it "can potentially" trigger) does lower latency and helps stability against random postponed refresh cycles

Push tRDWR to 9
maybe try SOC as 1.125 with a loadline that drops it to perfect 1.1v
Load procODT 42ohm and try to up BLCK to 100.9Mhz. Else just 110Mhz
See if you can get 1933Mhz stable. "not unlocked" firmware will refuse it post & and you either need to step by step update from 1080 AGESA upwards or just wait for the next official patch

Else you can just out of fun work on getting tRC= tRAS+tRP & the correct tRFC & tWR stable
tRTP = a clean divider of the used tRFC.
tWR = double the "tRC multiplier"
if used *6 , then tWR is 12
if used *8 then tWR is 16
~ as for a stable baseline, not a "best possible option" ruleset
 

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It should be just a configuation issue. IMC is still bad - but it should be able to run in the region of 2100~2200 after we get 1100 Patch D to every board
You have a lot of playroom on tRC, tRRD_
Get SiSoftware Sandra - run the "multicore efficiency test" with this set
Filter at the bottom to local results , and when you optimize this set , always compare the "latency curve" the ~detailed view~ what set looks to run better
Aida64 doesn't tell the whole story

Using tRFC mini so far has not lead to any issues. (not even one "doesn's work" report, but it's a simple tool) :giggle:
The timings copied from 1usmus calculator are perfect - but if you change one little thing, they will not be in sync.
Using timely triggered tRFC (mini sheet shows the range it "can potentially" trigger) does lower latency and helps stability against random postponed refresh cycles

Push tRDWR to 9
maybe try SOC as 1.125 with a loadline that drops it to perfect 1.1v
Load procODT 42ohm and try to up BLCK to 100.9Mhz. Else just 110Mhz
See if you can get 1933Mhz stable. "not unlocked" firmware will refuse it post & and you either need to step by step update from 1080 AGESA upwards or just wait for the next official patch

Else you can just out of fun work on getting tRC= tRAS+tRP & the correct tRFC & tWR stable
tRTP = a clean divider of the used tRFC.
tWR = double the "tRC multiplier"
if used *6 , then tWR is 12
if used *8 then tWR is 16
~ as for a stable baseline, not a "best possible option" ruleset
Sorry for continously bugging you. This is becoming mind boggling to me. I see other users with near exact RAM timings as me but they get latency in the 55ish range. I just tried this and get 60.7, not much improvement over my 60.9. Can be my mobo bios? I feel like with these timings I should be getting much better.

2465969

EDIT

Current Latency going back to 3800MHz CL16

2465970
 

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ProcODT 48 is too high for "just 1050mV" vSOC
Take a read on the bottom half of this post
If VDDP on the main menu is CPU VDDP, then it should be 900
If it's cLDO_VDDP , then you need to take care of the voltage stepping between VDDP-VDDG-SOC
925mV cLDO_VDDP and 1050 SOC - means VDDG could be at best 62.5mV. Or if the bios is inteligent it would push VDDG CCD to 975 and IOD to 1000mV
You can try applying this two voltages on VDDG and drop procODT to 32-36 range,. Maaybe 42ohm could be just enough ~ up to how SOC Loadline behaves on auto
It's better if you use a lower procODT and fix SOC loadline at 1 under flat
I didnt really notice any explanation of much talk about ProcODT in that post you linked. I really only do a bunch of memory tuning each time I build a new computer, so every 2-4 years so I always forget the ins and outs of these sorts of things from how long it has been. Could you help me understand the relationship with the voltage and on-die termination resistance? Why is it that you are supposed to lower the ODT setting as you go higher in voltage? And how are you determining the resistance setting based on voltage and the FCLK frequency you are going for?
 

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Sorry for continously bugging you. This is becoming mind boggling to me. I see other users with near exact RAM timings as me but they get latency in the 55ish range. I just tried this and get 60.7, not much improvement over my 60.9. Can be my mobo bios? I feel like with these timings I should be getting much better.

View attachment 2465969
EDIT

Current Latency going back to 3800MHz CL16

View attachment 2465970
I don't think the timings are good
You waste 2ck on tRC , should be 48
You waste 2ck on tRRD_S and
tFAW is 24 in this case , which is oke - but SCL is high too
Single Rank should be able to do 288-214-132 tRFC ~ near 1.44-1.46v

All this changes are a noticable bump
It's all about the tertiaries. Primaries can be worked on, but there is no need yet
tRTP can stay 8 , but tWR can go down to 12
tCWL can go -2 and tRDWR +2 as change
you can still do a lot :)

Just double check under AMD CBS ,that TSME
and under NBIO or DF, Memory scramble - both are disabled
Memory encryption = scramble,could also be under a MBIST section ~ which has ECC stuff inside
I didnt really notice any explanation of much talk about ProcODT in that post you linked. I really only do a bunch of memory tuning each time I build a new computer, so every 2-4 years so I always forget the ins and outs of these sorts of things from how long it has been.
Could you help me understand the relationship with the voltage and on-die termination resistance?
Why is it that you are supposed to lower the ODT setting as you go higher in voltage?
And how are you determining the resistance setting based on voltage and the FCLK frequency you are going for?
I wish i could link you all the old posts from this and the AMD 24/7 mem stability thread
But since the Xenforo migration , the links are dead
And there is too much to explain alone for procODT
Not to forget explaining Ohm's law, of current~impedance~ampere

ProcODT has many usages,
You have to increase it in order to bruteforce higher FCLK ~ when signals are unstable
But you should lower it and start with lower current (voltage) soo signal integrity improves
Then the range "when" low procODT works, is bigger
Also lower procODT with improved signal integrity, guarantees higher potential FCLK

It has two usecases, one it's an impedance and scales with SOC
on the other hand it's a signal-cut-off resistance
Low proc resistance with high current is equally as bad , as high current with high impedance
You need to get a ohm-current-ampere calculator to visualize , but at the end ~ only the pushed amperage matters and so also heat density and signal loss (signal integrity)

each CPU gen had a bit of different ranges
on Zen 1 , proc 53.3 was about near 1.15v as peak while only functioning above 1.0675v (min)
Zen1+ around 48ohm with min 1.05v max 1.125v
Zen 2's 28ohm for example works as min 0.8875-0..9v optimal is then 1.025 and peak 1.075
30ohm here moves that near 1v min, optimal 1.05 , and peak about ~1.08
32ohm can run fine 1.1v , but 30 ohm will cause issues
It's a long long topic

I linked you this specific post only for the voltage patterns , as AMD on stock has a minimum "stepping" of ~46mV , +/- 3mV loss
+50mV is always requested afterwards, neverless of what the bios reads at first for the VDDG or SOC line. More is requested afterwards to guarantee stability
A big topic exists here on OCN by The Stilt
"Matisse demystified (not really)" or something similar in title :D
 

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Just double check under AMD CBS ,that TSME
and under NBIO or DF, Memory scramble - both are disabled
Memory encryption = scramble,could also be under a MBIST section ~ which has ECC stuff inside
Okay, I think this is the major one I need to check because others with near identical if not exact same settings as me are getting better latency.

EDIT:

Okay your suggestions are definitely helping

2465981
3800CL1611192020 1530HRS LATENCY.png


EDIT 2: Okay this is where I ended up



3800CL1611192020 1730HRS LATENCY.png
2466009


EDIT 3:

Ran the same settings but this time in safe mode

2466271
 

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anta777 _ Extreme1

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1usmus_v3
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#Test 13 Mb=64

+--------------------------------+
 

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What can I do to get this stable?
Do any of these settings look wrong/suboptimal or too extreme/require excessive voltage for little latency gain?
I can last like 50 minutes TM5 1usmus_V3 before "Error 13", I don't know what that means.
2466016

Also I've tried so much to get 1900 FCLK... I don't if it's impossible or if someone smarter could do it, it just doesn't post, hope new BIOS will help.

Is it a problem tRTP isn't a clean divider of tRFC?
Thanks

Edit: got an Error 12 23 minutes in
 

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