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Thank you. I had to bump the voltage to 1.495 and now I'm stable in hci.

I had those settings previously, Veii helped be adjust to what you see in my Zen timings which dropped me from 61ns to 54.1ns.
Also, according to his recent test,
performance-wise, 1T (GDM OFF) > 2T (GDM OFF) > 1T (GDM ON).
 

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Some test I did today
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Also, according to his recent test,
performance-wise, 1T (GDM OFF) > 2T (GDM OFF) > 1T (GDM ON).
Interesting. I have mostly seen test where the last two are swapped.
 

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A user over at reddit posted the following response to my test. How true is this in terms of Zen 2 and Zen 3?

"With 4 single rank sticks you lose rank interleaving which is why a 2X16 kit of dual rank dimms can carry more bandwidth. Single rank dimms disable rank interleaving regardless of if you have 4 sticks running in dual channel for a pseudo "dual rank" setup.

You still won't see much of a performance difference, especially while gaming, but there is a technical advantage to using actual dual rank dimms.

See the quote from this article below, it goes it to more detail;"

Interleaving across Ranks
Interleaving is continued from interleaving across the channels to interleaving across the ranks in a channel. This only occurs when using dual or quad rank DIMMs. If a channel is populated with mixed ranking DIMMS and a single rank DIMM is present, rank interleaving will revert back to 1-way interleaving. 1-way rank interleaving results in storing bits in a single DRAM chip until it’s at capacity before moving to another DRAM chip. Rank interleaving provides performance benefits as it provides the memory controller to parallelize the memory request. Typically it results in a better improvement of latency. However the performance difference between dual ranking and quad ranking is minute and comes only into play when squeezing out the very last ounce of performance. Try to avoid single rank DIMMs.
 

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Hello!
Writing here to get some help with my timings, trying to get them working as good as possible.
People claiming they are wrong and shouldn't work or even post. My settings do 24cycle TIM5 without error etc, but if someone here can help me out I would be very happy!
My cpu is 5900x on gigabyte aorus master x570.
My memory is G.Skill ripjaws

Wouldn't i get better latency? Haven't reinstalled win10 in a while so its not a fresh install. But hope to get some help!

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well ns is a problem if not all is closed in the taskmanager, what you can close and should be closed... and will not open again. My record was 54.0 same 31k bios but DS ram and crazy timings. 31N bios i lost 0.7ns with same timings as not so fast sadly. I don't think your timings will be working up to 10000% in karhu memtest. So here what i made and worked with my ram 10000%



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here the settings in 31N bios from this week

cachemem14-31n.png
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Hello!
Writing here to get some help with my timings, trying to get them working as good as possible.
People claiming they are wrong and shouldn't work or even post. My settings do 24cycle TIM5 without error etc, but if someone here can help me out I would be very happy!
My cpu is 5900x on gigabyte aorus master x570.
My memory is G.Skill ripjaws

Wouldn't i get better latency? Haven't reinstalled win10 in a while so its not a fresh install. But hope to get some help!

View attachment 2467809 View attachment 2467810
That people would be me :)

What I find weird is the latency which with such low timings, if they were not auto-corrected, my guess would be should give 53ms or even better.
Also that huge gap between R/W speed and copy speed, for what I remember, means something is wrong with timings.
But it could be the AGESA version used in the latest GB BIOS releases.
I have a gap as well now but not that huge.

I mean SCL at 2, RTP at 6, RFC at 245, RRDS/RRDL 4/4, SC 1/1, etc
Don't think I have seen any profile with all this stuff so tight at the same time at 3800MHz.
If it was really working it the performances should be better than this, which is good but not that much.
 

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That people would be me :)

What I find weird is the latency which with such low timings, if they were not auto-corrected, my guess would be should give 53ms or even better.
Also that huge gap between R/W speed and copy speed, for what I remember, means something is wrong with timings.
But it could be the AGESA version used in the latest GB BIOS releases.
I have a gap as well now but not that huge.

I mean SCL at 2, RTP at 6, RFC at 245, RRDS/RRDL 4/4, SC 1/1, etc
Don't think I have seen any profile with all this stuff so tight at the same time at 3800MHz.
If it was really working it the performances should be better than this, which is good but not that much.
well you linked med Zen RAM Overclocking
check all the gaps there! It must be the bios, I know my timings are extreme, but they work! Been running with the for months ;) And got with 3900xt around 62ns.
So they work.
 

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mmmh... hard to think as check my timings...I could not get ProODT under 48 working in 31K BIOS
 

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well you linked med Zen RAM Overclocking
check all the gaps there! It must be the bios, I know my timings are extreme, but they work! Been running with the for months ;) And got with 3900xt around 62ns.
So they work.
Yes they work but not as you would think.
They are likely auto-corrected, probably the 3900XT was doing a very good job at it.
But on the 5900X you are beaten badly by a CL16 profile with RFC all sub-timings much higher.
This means if you do it right then you'll see a sensible improvement.
 
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Here are my BDIE timings, if it helps...
The copy value is behind, as i have the trial version.
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Im also open for any recommendations!😄
 

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Can someone please share a source and answer a question about memory interleaving?

I understand that memory interleaving occurs in dual rank memory, but what about quad channel single rank memory running in dual rank?

Another user on Reddit claimed that 4x single rank sticks in dual rank mode does not take advantage of memory interleaving and used an article written in 2015.

Is this the case with Zen 1, 2 and 3? Or is the controller different?
 

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Can someone please share a source and answer a question about memory interleaving?

I understand that memory interleaving occurs in dual rank memory, but what about quad channel single rank memory running in dual rank?

Another user on Reddit claimed that 4x single rank sticks in dual rank mode does not take advantage of memory interleaving and used an article written in 2015.

Is this the case with Zen 1, 2 and 3? Or is the controller different?
If you mean rank interleaving only happens within a memory module.
Two single rank modules in a single channel will not do rank interleaving.

Mixing a SR and a DR in a single channel will disable rank interleaving for the DR module as well.
At least that's what happens in a server, guess it's the same for Ryzen.

Quad channel SR is the same, rank interleaving will not work.

If you mean channel interleaving as long the layout of the 2 channels is identical will be enabled.
 

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If you mean rank interleaving only happens within a memory module.
Two single rank modules in a single channel will not do rank interleaving.

Mixing a SR and a DR in a single channel will disable rank interleaving for the DR module as well.
At least that's what happens in a server, guess it's the same for Ryzen.

Quad channel SR is the same, rank interleaving will not work.

If you mean channel interleaving as long the layout of the 2 channels is identical will be enabled.
Yes, I'm asking about memory interleaving and 4x single rank sticks. So there's no memory interleaving? And what is the performance impact?

The reason I ask is because from the test I have done, dual rank hasn't done much in terms of Performance. I posted some benchmarks earlier.
 

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Yes, I'm asking about memory interleaving and 4x single rank sticks. So there's no memory interleaving? And what is the performance impact?

The reason I ask is because from the test I have done, dual rank hasn't done much in terms of Performance. I posted some benchmarks earlier.
There is channel interleaving, not rank interleaving, with 4 x SR modules.

When you talk generically about memory interleaving it's meant channel interleaving.
Which means bonding 2 channels and doubling the bandwidth for every memory transfer operation.

Rank interleaving means the DIMM will execute, internally, another operation on the 2nd rank while the 1st is doing something else, usually refreshing.
Which means a small improvement in latency, commands are executed faster.
Only those which doesn't need the data bus which is shared between the 2 ranks.
Another small bump comes from the higher density; same density (2x8GB SR vs 1x16GB DR) means 2 vs 1 DIMMs and that's less commands overhead.

If you want to see the performance increase, which is a very small 3-5% tops usually, you need a latency sensitive real workload.
Assassin Creed and Shadow of The Tomb Raider at 1080p should show a few fps more with Dual Rank.
 
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Just putting this out there for those who want a quick fix instead of spending time getting to know their hardware.

So.…..I receive a set of F4-3200C14D-16GTZR that are going to go into a friends rig, as I am waiting for the motherboard to arrive I decide to get some baseline settings for this set of modules

Now, look at the screenshot below, for this set of modules and with my hardware, one value made the difference between almost instant crash with TM5 to being "stable" TM5 when switching from command rate of 2T to 1T (stable in "" because I am yet to run a 25 cycle loop, but so far its at cycle 4 with no errors).

Try to guess which value that may be before looking below, a clue, its not a memory timing (BTW this is 3800/1900 as BCLK is @ 107.6 mhz)

:D

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So did you guess correctly ??

The change was simply ClkDrvStr from 20 ohms to 60 ohms (my vipers like 20 ohms for some strange reason).

Also, a difference between how motherboard autodetect DrvStr settings.

My A2s Vipers, CsOdtDrvStr & CkeDrvStr on AUTO are set at 24 ohms, where as these GSkills (unsure regards the PCB type, will post some images later) AUTO settings for CsOdtDrvStr & CkeDrvStr are 20 ohms when ClkDrvStr was on AUTO and defaulting to 24 ohms.

Once I set ClkDrvStr to 60 ohms, CsOdtDrvStr & CkeDrvStr revert to 24 ohms on AUTO.

TM5 reached cycle 5 while typing this, going to stop it now and see what happens with tRCDRD set @14

:p

** EDIT **
ClkDrvStr to 60 ohms, CsOdtDrvStr & CkeDrvStr when on AUTO will flip flop between 20/24 ohms.

Nope tRCDRD not possible at 14/15 with above settings, I am sure with some tweaking I may be able to get there, but seeing these are going into a different motherboard I have a good baseline to work with.

Most important point, all the above is moot if the CPU IOD cannot handle 1900 MHz, seems to be the most important part of the equation. Will see what happens if the B550 motherboard paired with a new 3600x will act similar to my X570 with my 3600 CPU ….

GSkill F4-3200C14D-16GTZR on top, Viper Steel 4400 mhz below

20201205_121559.jpg 20201205_121715.jpg 20201205_121619.jpg 20201205_121645.jpg 20201205_121446.jpg 20201205_121539.jpg
 

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Spent some more time today trying to run 32Gb 3800c14 GDM off with TM5.


View attachment 2467978
Good going!

Have you tested tRDRDSCL/tWRWRSCL @ 4/5 instead of 2/3 with regards to bandwidth in AIDA64 ?

As on my 3600 4/5 is around 200-300 mb better throughput set @ 4/5

With 2 x 8GB at 2/3 the throughput results are flipped.

4 x 8GB better throughput with 4/5
2 x 8GB better throughput with 2/3
 

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Yes they work but not as you would think.
They are likely auto-corrected, probably the 3900XT was doing a very good job at it.
But on the 5900X you are beaten badly by a CL16 profile with RFC all sub-timings much higher.
This means if you do it right then you'll see a sensible improvement.
This 2, 3 times over, the devil is in the detail

:)
 

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This 2, 3 times over, the devil is in the detail

:)
Well still I posted all my settings, can someone change them to what they think is the best.
I just want some help, people showing their settings but most of them are with 32gb. If its autocorrect that makes me run this timings, than it would be awesome to get the timings a bit looser so it doesn't autocorrect and change them. So I maybe gets better results than what I have now.

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