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Nope, not stable at all.

I don't get it man, seems like there is some kind of incompatibilitie issie with my new RAM and system. No matter what speed, voltage or whatever its not stable anymore and it triggers WHE errors...
 

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This is the error i get when stressing with OCCT:

2484042



Yesterday it was good for 1.5 hours of OCCT and today it was "unstable" again.. When testing with TM5 i never find any issues and it passes everything..

Does this mean that my new RAM kit is utter trash or compatibility issues? I mean, with my g.skill FlareX kit i never encountered these issues and it was stable as a rock always..

My new kit should also be B-die but i highly doubt it because if it was why so much issues with only a slight over clock.. Its not the CPU as i could run 3800 MHz on my other RAM kit just fine..

I tried more or less voltage, proc ODT settings. One minute its stable and the other its acting up again.. I tried resetting everything, using the same BIOS as on my FlareX kit but nothing works.. I saved .CMO file so i have exactly the same settings as on the FlareX but no go..

Before i send this RAM kit back i want to know for sure if its the RAM or something else, idk anymore.
 

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@hurricane28 Means you IF is unstable. Either play with the voltages or lower your IF speed. My 3800X could do 1900, this Vermeer I have can only do 1866
 

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That is correct.

There was something wrong with the settings it seems and now its all working well again...

I saved BIOS settings to .CMO file and i could flash it. But it seems that when you flash BIOS settings it "forgets" or simply cannot apply some settings.. I had to search trough them to see that and make it work again. Now everything is good again.
 
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Hey guys, can you help with overclocking Crucial Ballistix 3000mhz CL15 2x8GB (BLS2K8G4D30AESBK) to 3800Mhz?
Im struggling another day to reach 3800Mhz with this kits. Without any problems I reached 3733Mhz following DRAM calculator, 1usmus Techpower guide and github DDR4 OC Guide, but 3800Mhz can't even boot. I tried loosing timings to 18-22-22-42 and tCWL 18 and rest on Auto, 1.5v DRAM, SOC 1.17v, played with ProcODT from 40 to 63Ω, VDDG and VDDP on Auto, even putting all safe timings from DRAM Calculator didnt help. I tried to follow all recommendations from both guides and I still can't boot. Should I play more with VDDG and VDDP (system auto set them to 1.07v and 1.14v AFAIR) or increase more ProcODT?
My comp is: Ryzen 3600 not OC (yet ;p), B450 Tomahawk Max (latest BIOS), very decent case cooling (2x120mm blowing straight on RAM), BIOS loaded with default settings and Micron E-die Crucial Ballistix Sport LT 3000Mhz CL15 2x8GB BLS2K8G4D30AESBK (Rank 1).
Reading comments and posts from around net I thought that it will be easy process to reach 3800Mhz and then struggle a bit with rest settings but I can't even boot, have to clear CMOS everytime :(
 

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@Zeuskk your DIMMs are more than capable, it's the CPU that might be holding you back.

Try desynchronising Infinity Fabric clock from Memory clock. i.e. run your RAM at a lower speed e.g. 3200MHz with loose/XMP timings and only increase your FCLK to 1900MHz. See if you can POST. If not, you'll need to try different Vsoc, VDDG, CLDO_VDDP voltages to stabilize the Infinity Fabric if possible. E.g. try CLDO_VDDP 900mV, VDDG_CCD/IOD 975mV, Vsoc 1.05V.
 

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@Zeuskk your DIMMs are more than capable, it's the CPU that might be holding you back.

Try desynchronising Infinity Fabric clock from Memory clock. i.e. run your RAM at a lower speed e.g. 3200MHz with loose/XMP timings and only increase your FCLK to 1900MHz. See if you can POST. If not, you'll need to try different Vsoc, VDDG, CLDO_VDDP voltages to stabilize the Infinity Fabric if possible. E.g. try CLDO_VDDP 900mV, VDDG_CCD/IOD 975mV, Vsoc 1.05V.
Ye CPU is my limit I guess, tried desynchronising with 3200Mhz loose timings and only increasing FCLK to 1900MHz and I couldn't boot even if I manualy set VDDP, VDDG and SOC to your recommendations and higher. I think the best will be to stay on 3733MHz and find good timings or maybe there is other way that is worth trying?
 

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I still can't figure out what slots to put weakest ram kit in, when doing 4x8. Initial slots or physically closer to the socket?
 

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I still can't figure out what slots to put weakest ram kit in, when doing 4x8. Initial slots or physically closer to the socket?
put weakest ram kit in A2 and B2
 
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I was messing around with ram leaving vsoc on auto when I noticed in zen timings that vsoc voltage bumped from 1.1 to 1.55 upon launching tm5. Was it real or monitoring bug? I'm afraid I fried mem controller a bit and it will never show good results now. For example going from 1.1 to 1.12 gives me tons of errors, not sure if related.
 

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I was messing around with ram leaving vsoc on auto when I noticed in zen timings that vsoc voltage bumped from 1.1 to 1.55 upon launching tm5. Was it real or monitoring bug? I'm afraid I fried mem controller a bit and it will never show good results now. For example going from 1.1 to 1.12 gives me tons of errors, not sure if related.
2486439

Bugs :D
Both actually, readout and requested but never provided
I still can't figure out what slots to put weakest ram kit in, when doing 4x8. Initial slots or physically closer to the socket?
Weakest on the main-master slots, best set (user binned) on the slave set
 

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Such a relief, thank you
There are over 12 protections in place to prevent too high voltage passing through
You can bug out FIT and request 1.55vCore through CTR by accident
Yet even if you do that and it bugs out - as the user used "offset mode on an too early version of CTR"
There are 4-5 more protections left after FIT bugs out.
You can also bug out FIT with the old EDC bug, of 1,2,3 as a value
But then another protection triggers and package throttles the whole CPU including cache

Even if anything leaked in there. The cpu would be slower than 550Mhz , and there 1.6v wouldn't do anything to it
It can request it if all goes haywire and breaks, but at the end even if the VRMs supply it - it will never arrive in that form to the CCDs

The only "user influential" degradation voltage you can use is too high VDDG CCD (beyond 1100+)
or cLDO_VDDP beyond 1.15v

Oor 1.3v SOC with 120ohm procODT
useless stuff like this , would damage it
Ooor running 1.65v for over 30min at beyond 90+ Celsius

Soo don't worry about it
Only keep VDDG voltages lower than 1150mV
well and maybe take a reading through this whole thread

Degradation is hard on these chips. They will throttle on close to every little issue and autocorrect
Really "breaking" them is hard, and bypassing FIT close to impossible
 

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Is 1.125vSOC a little high for 1700/3400 cl14, GDM Disabled 1T ?
 

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Is 1.125vSOC a little high for 1700/3400 cl14, GDM Disabled 1T ?
Could imagine it with dual 64gb dimms at 53ohm procODT
else, just waste of heat :)
Minimum Requirements of VSOC mV @ Frequency
  • 3200 - 980-1000mV
  • 3400 - <1040mV
  • 3600 - <1060mV
  • 3800 - <1075mV
  • 4000 - <1137,5mV
  • 4067 - 1165-1200mV
  • 4200 - 1187,5-1225mV
maximum being 1300mV, while 2100 defaults to 1250mV SOC.
These are GET values , not SET
IMC scales similar to Matisse on low voltages. Maybe a bit better even , just procODT is one step higher than Matisse
Less than 1050mV will run 1700 FCLK ~ when less than 1.1v can run 1900 FCLK

Usually the IMC should be able to run 1800 FCLK at 1.025vSOC ~ but depending on loadline and thermals + memory dimm strain. The limits are subtle bit higher
Also higher because the CPU boosts higher. But on Matisse it certainly does work @ 28ohm procODT
Linking you to the same thread again

Stable a 1060mV-SOC (1900 FCLK)
That's another dual CCD gimped unit, soo nothing single CCD exclusive
 

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Excuse me, is there a guide how to narrow down the search for best values of voltages and impendences? How likely for same motherboards to share same best settings?
It's a long routine in 3 steps/stages:

1st stage (exploring)
  • Use very lose timings you know which will run and have an allcore CO set. Alone -3 is enough as long as all cores reach that same freq
  • figure out what VDDG combinations you need , probably at the same time you also do SOC testing
  • run y-cruncher through it and see if you fail on each of the tests per frequency
  • aida64 confirm that you actually do subtle but positive changes step by step
  • note all this down

2nd stage (undervolting)
  • learn how loadline on your board behaves and check how much is required till you do crash on y-cruncher or refuse to post
  • at this point VDDGs should be fine but you never know, soo be sure it really is y-cruncher stable

3rd stage (benchmarking)
  • after figuring out "random optimals" and "minimum undervolts", use the minimum load as a baseline for aida64 benchmarking & change procODT +1 / -1 , to figure out instabilities ~ 0.3ns variance is instability or an unoptimized OS
  • above should be in an own stage, but keep benchmarking - till you figure out the min/max of vSOC inside your procODT range / the one you've settled down for. Keep benchmarking till the result improves
  • like again one above, scale up freq till you see that either VDDG is not enough, SOC is not enough or procODT is not enough
at this point you should be able to feel what is wrong and what is autocorrecting

Not really a guide, but that's usually it
Benchmarking benchmarking benchmarking.
It needs a high timings foundation for such, and before all that ~ needs a non varying cpu setup. With cache hitting optimal access time on all cores
I can see that 12 threads holding the same stock freq, is easier than 32 threads holding the same stock freq, per core :D
Cache access times:
10.9ns = 4.65 allcore
10.7ns = 4.75 allcore
10.4ns = 4.85 allcore
10.2ns = 4.95 boost on allcores for a short time

I have the unit since so far around 6 months
the post was written after around two months
All sounds easy , but a lot of 12h days went into it exploring how it behaves
Overall the guide is the same

Y-cruncher, SiSoftware Sandra MCE Test, Aida64, HWinfo (CPU Snapshot pooling mode)
Where all you need
OCCT extreme came to existence far later, including all per-core test tools & CTR
Currently it's easier to test things
 

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Any settings I can steal from another owner of same motherboard? :) Or everything, rtt's, cad buses, etc are tied to cpu sample?
If you are willing to downconvert to v1.20 & update to 1.60 from the bios, i can give you a whole rom copy
So you can flash it with flashrom and have all my profiles

It's up to you what you decide then
Either a black-copy of anything till 1866-2033 FCLK
or one that starts from 2033 FCLK and goes till 2167 + 5ghz presets

Maybe i can just export the profile files for you to load from the usb, that could also work
I even think it should compatible across all B550 ASRock boards ~ but somebody has to try
The profiles that are loaded, do also change settings which are in the hidden. For example ones that where exposed in a previous bios but aren't anymore

Current bioses have a flashlock since AGESA 1.2.0.0
Current 1201 is plain bad, but you can normally downgrade
Soo if you go to anything that's lower than 1200 , you can use flashrom to flash the romfile with all profiles in there
=====
If you mean "copy from another owner" in general,
RTTs are depending a bit on the PCB quality, but a lot on the DIMM amount and capacity (dual rank or single rank)

cLDO_VDDP and VDDG are pretty much sample dependent , but it's also architecture dependent
Soo you can copy what people use on the zen 3 sheet

Just don't really run cLDO_VDDP beyond 1020mV, 1050mV as max
It's a bad idea. Also a bad idea is to run VDDG CCD beyond 1050 or IOD beyond 1150mV
SOC can go up till 1.3, but 1.2 is about what you need most of the times
 
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