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Discussion Starter #1
The Volcanic Island 2.0 GPUs coming in the second half of this year will be using HBM 1st gen. Pirate Islands will be using HBM 1st gen, and Pirate Islands 2.0 will be using HBM 2nd gen.





It will be a joint effort between AMD, SK Hynix, GlobalFoundries, Open Silicon, and Amkor.

4 x HBM Gen 1 = 4 GB
3 x HBM Gen 1 = 3 GB
2 x HBM Gen 1 = 2 GB
1 x HBM Gen 1 = 1 GB

4 x HBM Gen 2 = 8 GB/16 GB/32 GB
3 x HBM Gen 2 = 6 GB/12 GB/24 GB
2 x HBM Gen 2 = 4 GB/8 GB/16 GB
1 x HBM Gen 2 = 2 GB/4 GB/8 GB

Edit(May 12): HBM Gen 2 numbers are fixed.
 

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Cant wait! Question is. Pirate Islands 1.0 or 2.0. That is the question.
 

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Discussion Starter #3
Quote:
Originally Posted by Alastair View Post

Cant wait! Question is. Pirate Islands 1.0 or 2.0. That is the question.
VI 2.0: 2014
PI 1.0: 2015
PI 2.0: 2016

Your upgrade pathing awaits your decision.
 

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Quote:
Originally Posted by Seronx View Post

Quote:
Originally Posted by Alastair View Post

Cant wait! Question is. Pirate Islands 1.0 or 2.0. That is the question.
VI 2.0: 2014
PI 1.0: 2015
PI 2.0: 2016

Your upgrade pathing awaits your decision.
Will VI 2.0 just be basically updated Hawaii or will we see some mid range parts?
 

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Discussion Starter #6
Quote:
Originally Posted by Alastair View Post

Will VI 2.0 just be basically updated Hawaii or will we see some mid range parts?
VI 2.0 will be an enhanced Volcanic Islands architecture, with new ACE units and more focus on compute shaders, etc. It will also be the first GPUs for AMD to support HDMI 2.0 and DP 1.3.
Quote:
Originally Posted by heroxoot View Post

But I just got a 290X!
I think AMD's approach for this one is the opposite of previous generations. It will be mid-range first then the high-end range. The 290X will be okay till the end of 1H 2015.

----

-- Edit(May 12th): Roadmap fixed and removal of codenames(since they always change) --
28nm TSMC Q4 2013 : High-end GPU, VI 1.0
28nm GlobalFoundries Q4 2014 : Mid-end GPU and Low-end GPU, VI 2.0
28nm GlobalFoundries Q2 2015 : High-end GPU, VI 2.0
20nm GlobalFoundries Q4 2015 : Mid-end GPU and Low-end GPU, PI 1.0
20nm GlobalFoundries Q2 2016 : High-end GPU, PI 1.0
14nm GlobalFoundries Q4 2016 : Mid-GPU and Low-GPU, PI 2.0
14nm GlobalFoundries Q2 2017 : High-GPU, PI 2.0

There also might not be a significant enhancement between Hawaii and the next high-end GPU.
 

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So r 4xx series will be using stacked dram?then 2015?and the high end chips like pirate islands 2.0 would be a different naming?because bermuda is the equivalent od r9 280x?
 

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Discussion Starter #8
R(x) 3(xx) will be using HBM 1st Gen.
R(x) 4(xx) will be using HBM 1st Gen.
R(x) 5(xx) will be using HBM 2nd Gen.

No nomenclature changes.
 

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Discussion Starter #10
Quote:
Originally Posted by PontiacGTX View Post

I dont think that amd will split pirate islands in2 when nvidia will be releasing 2 different architrctures
It's aggressive node hopping;

Volcanic Islands 1.0 - 28nm TSMC
Volcanic Islands 2.0 - 28nm GlobalFoundries
Pirate Islands 1.0 - 20nm GlobalFoundries
Pirate Islands 2.0 - 14nm GlobalFoundries
 

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Discussion Starter #12
Quote:
Originally Posted by Nemessss View Post

Thx for these infos, have you got any infos for the GeForce GTX 880? Will be out this summer?
I don't know about for Nvidia.

Since they are going to release the GK210, GM104, GK206, GM107, all together.
 

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Mmmm, stacked memory.
yessir.gif
PCBs should be a little smaller/cheaper as well, as VI won't need all those traces for GDDR5, and the memory VRMs can be smaller.

But I wonder if the HBM stacks will create heat issues for the GPU itself. Obviously the bandwidth/power benefits outweigh the negatives, but VI 2.0 might run a little hot for the amount of power it draws.

EDIT: Also, this info was basically reposted by WCCF in the OCN news section. Stacked memory on the next AMD GPUs is a big deal, why hasn't the news spread until now?
 

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So there will be mid volcanic islands parts?
 

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Quote:
Originally Posted by Alastair View Post

So there will be mid volcanic islands parts?
They'll initially be marketed/priced as high-end parts, like the GTX 680. Then the bigger GPUs come out, and the older silicon will probably get rebranded like most of the R9 2xx/GTX 7xx series.
 

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Discussion Starter #16
Quote:
Originally Posted by brucethemoose View Post

But I wonder if the HBM stacks will create heat issues for the GPU itself. Obviously the bandwidth/power benefits outweigh the negatives, but VI 2.0 might run a little hot for the amount of power it draws.
The HBM stacks are not on top of the GPU, they are beside the GPU.

VRAM (GDDR) on the board: Passive Cooled or 2nd Class Heatsink.

VRAM with GDDR5 does not touch copper it only touches the weaker Aluminum part and Fins. In the lower end designs it is passively cooled by the wind no heat sink.

VRAM (HBM) on Si-Interposer; Within a IHS and or direct contact with the main copper Heatsink.
Quote:
Originally Posted by brucethemoose View Post

EDIT: Also, this info was basically reposted by WCCF in the OCN news section. Stacked memory on the next AMD GPUs is a big deal, why hasn't the news spread until now?
Amkor delayed 2.5D but no one looked at the new roadmap. Everyone assumed it was delayed till the 20nm nodes, it wasn't.

Old Roadmap:

New Roadmap:


If you want to notice both images for Si Interposer + Memory + Logic are all AMD+GlobalFoundries tests. These tests were done in 2011 to 2013, so they aren't recent test runs.

From older HBM slides from AMD, they had the HBM interface overclocked to 1.4 GHz. All reference designs should have a clock of 1 GHz but I wouldn't be surprised if there are 1.4+ GHz ones.

1 GHz HBM -> 128 GBps
1.4 GHz HBM -> 179.2 GBps.
 

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Quote:
Originally Posted by Seronx View Post

The HBM stacks are not on top of the GPU, they are beside the GPU.

VRAM (GDDR) on the board: Passive Cooled or 2nd Class Heatsink.

VRAM with GDDR5 does not touch copper it only touches the weaker Aluminum part and Fins. In the lower end designs it is passively cooled by the wind no heat sink.

VRAM (HBM) on Si-Interposer; Within a IHS and or direct contact with the main copper Heatsink.
Amkor delayed 2.5D but no one looked at the new roadmap. Everyone assumed it was delayed till the 20nm nodes, it wasn't.

Old Roadmap:

New Roadmap:


If you want to notice both images for Si Interposer + Memory + Logic are all AMD+GlobalFoundries tests. These tests were done in 2011 to 2013, so they aren't recent test runs.

From older HBM slides from AMD, they had the HBM interface overclocked to 1.4 GHz. All reference designs should have a clock of 1 GHz but I wouldn't be surprised if there are 1.4+ GHz ones.

1 GHz HBM -> 128 GBps
1.4 GHz HBM -> 179.2 GBps.
HBM base clock 1ghz? how varies the frecuency with a staked dram vs a normal dram?nothing? only the bandwidth veries?
 

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Discussion Starter #18
Quote:
Originally Posted by PontiacGTX View Post

HBM base clock 1ghz? how varies the frecuency with a staked dram vs a normal dram?nothing? only the bandwidth veries?
Stacked DRAM can achieve the same clock rates with normal DRAM. While HBM is more of a thicker interface than other DRAM interfaces.

DDR3/4/GDDR5M; you have a few to many 64-bit channels that are ran at speeds between 1.33 GHz to 5.5 GHz.
GDDR5; you have many 32-bit channels that are ran at speeds between 5 GHz to 8 GHz.
HBM; you have eight 128-bit channels that are ran at speeds of 1 GHz.
 

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Quote:
Originally Posted by Seronx View Post

Stacked DRAM can achieve the same clock rates with normal DRAM. While HBM is more of a thicker interface than other DRAM interfaces.

DDR3/4/GDDR5M; you have a few to many 64-bit channels that are ran at speeds between 1.33 GHz to 5.5 GHz.
GDDR5; you have many 32-bit channels that are ran at speeds between 5 GHz to 8 GHz.
HBM; you have eight 128-bit channels that are ran at speeds of 1 GHz.
then a 3GB R9 370X would be using 3 stack of dram for having same quantity of vram chips as a R9 280X, wouldnt it?
 

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Discussion Starter #20
Quote:
Originally Posted by PontiacGTX View Post

then a 3GB R9 370X would be using 3 stack of dram for having same quantity of vram chips as a R9 280X, wouldnt it?
The amount of stacks is dependent on the bandwidth versus ALUs.

2048 ALUs @ ~1 GHz = 2048 GFlops
6 GHz @ 384-bit = 2,304 Gbit/s; 12 (256 MB) chips @ 6 GHz / 3 GB
1 GHz @ 2048-bit = 2048 Gbit/s; 2 stacks with 4 (256 MB) memory dies @ 1 GHz / 2 GB

2304 / 12 = 192 Gbit/s per chip
2048 / 8 = 256 Gbit/s per die or 2048 / 2 = 1,024 Gbit/s per stack.

Also, one factor is how large the HBM physical interface would be but I can't find any measurement of it. So, my gut guess would be one HBM 1024-bit phy_inf would be; ~88 mm² on 28nm SHP. I'm pretty sure I am no where near it but if I find a mm² measurement of HBM, I'll change it.
 
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