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Some manufactures introduced locks after 1900 with most recent updates, they got rid of WHEA at lower settings thou.
I'll read through this voltage recommendations, thank you! Mine are all on auto so far, only thing I did was VDDR SOC line calibration set to 5 (highest) as it made 1.1V flat, previously it was 1.081 and even less stable than now.
you can run 1.075 for 1900 FCLK ~ up to remain voltages
It should be an SMU lock an no manufacture lock
Manufactures just use what they get from AMD and compile it + add some own flair

It might be a microcode thing, but i will investigate where the lock exactly is in SMU / microcode
Because it clearly can run up to 2100FCLK & up to 2067 with 900 VDDP, 940 CCD, 1060 IOD, 1100 SOC
VDDP even on Matisse (same IMC like 2700X) doesn't need more than 900mV
but this depends on procODT state

Have toyed around enough last days, with the Wraith Spire
Time to use good cooling and work on memOC + PBO :coffee:
 

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you can run 1.075 for 1900 FCLK ~ up to remain voltages
It should be an SMU lock an no manufacture lock
Manufactures just use what they get from AMD and compile it + add some own flair
true, my comment was based on my friends experience with MSI boards rather than solid knowledge ;)
they got tons of WHEA, unstable at anything above 3200MHz but they could post at 2000MHz and some even above, and with this new BIOSes they got rock stable up to 1900MHz and no post at 2000MHz
 

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yes, but not only
if you use 4 dimms try higher Clkdrvstr
4 dimms or dual rank can move beyond 60ohm
Zen 3 can post beyond 2000 fabric even with 58ohm procODT
Negative scaling wasnt found yet
2100 will run with 34-58ohm procODT, all off them work

SMU 56.34 is not able to go beyond 1900FCLK
But you run too low SOC
same post as the quote above
voltage stepping - is important
give SOC a bit more like 20mV
or if you stay on auto , try to use global -50mV offset
by default these AGESA's overvolt a bit on SOC
And Zen3 is very SOC hungry :)

you can go up to 1.125v SOC without issues
2100 fabric will require you to run 1.2-1.25v SOC to have a chance of stability,
if you decide to downgrade the bios one step down to AGESA 1.1.0.0 non patch C
Thx !

I’m on auto on vSOC/VDDP/VDDG/ IOD
I have tested 1.125v on VSOC but it did not help.
Will try with your tips with procODT and clkdrvstr.

I’m targeting 1900mhz. More will be too complicated with 4 stick anyway I think.
 

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I have been unable to post over 1900IF with any BIOS so I thought I would try undervolt the SOC.
[email protected] 1.47-1.5VDIMM
VSOC 0.9313V (Offset -0.5) vs Auto 1V
CLDO VDDP 0.8V vs Auto 0.9V
VDDG IOD\CCD 0.8471V (set 0.85V) vs Auto 0.9V

CLDO VDDP would not post at 0.7V and 0.75V was unstable.
Rest may be able to go lower but Veii suggested above that CLDO VDDP should be lower than the rest so I left it at that for now.
2467045
 

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edit: also what you say with 40mV steppings could look like this?

VDDP 0.94
VDDG 1.02
VSOC 1.10
Pretty much yes
although don't ignore VDDG, split it :)
CCD can and should stay low this generation
too high CCD caused crashed for me on y-cruncher
high IOD is what is needed

It's funny,
on one hand this silicon is insanely power efficient
On the other hand also insanely powerhungry :p
Renoir was very similar behaving (sometimes up to 1.3vSOC)
~ seems to be the colour change

Old Matisse days i kept recommending double stepping for VDDP-VDDG and double stepping or SOC
although only because you couln't expect 1v SOC to run 1900

Today, it's rather single stepping for VDDP->VDDG CCD, double stepping for IOD and then another double for SOC
The limits on CCD (1050) IOD (1150) i would continue to hold
VDDP beyond 1050 is damaging, CCD might be pushed to 1100 but already beyond 980mV i saw issues with it
IOD beyond 1100 is already too much for this already vintage 12nm I/O-Die :)

I have been unable to post over 1900IF with any BIOS so I thought I would try undervolt the SOC.
[email protected] 1.47-1.5VDIMM
VSOC 0.9313V (Offset -0.5) vs Auto 1V
CLDO VDDP 0.8V vs Auto 0.9V
VDDG IOD\CCD 0.871V (set 0.85V) vs Auto 0.9V

CLDO VDDP would not post at 0.7V and 0.75V was unstable.
Rest may be able to go lower but Veii suggested above that CLDO VDDP should be lower than the rest so I left it at that for now.
View attachment 2467045
700 should work, we confirmed this on Matisse too
It should have the same voltage running abilities like a 2700X
What does make issues, is high procODT
Try that with 30ohm procODT
30 ohm are enough for 1900FCLK
(well even 28ohm where in the old days ~ but as this one needs more SOC overall, 28ohm is a bit too low)
VSOC 0.9313V (Offset -0.5) vs Auto 1V
This is what i figured and recommend now too
it seems to work perfectly across the whole range of "auto predicted" voltages
from 1800 till 2100FCLK
-------------------------------------------------
Just 2100 is OCP hardlocking on me still
something with proc and CCD is not fin
~ still fighting with it for day #3
might be also just a core voltage thing , i'll figure it out it just needs time

The powerplan research is halfway done
If AMD CBS is open for you guys,
  • disable SMEE
  • enforce 512 Bytes memory interleaving
  • disable memory clear
  • under NBIO -> SMU, enforce both CPPC and CPPC Preferred Cores
  • APBDIS to 0 just for good measure once SOC gets unlocked to be variable again :cautious:

For the rest, we need to see what's open per user
Enforcing -50mV SOC offset seems to work well
I suggest also to watch HWInfo core "quality" sorting
You can "improve" which cores are "golden cores" just by playing either with the global negative vCore offset, or the PBO Curve optimizer option
For me even PBO Scaler x2, already was enough to give it a 40-50mV lift up and then filtered down with a global negative offset
Although global offset and curve optimizer together work better than this scalar
The scalar is a bit too agressive and already at x3 is too strong for me

Oh i also suggest to start with y-cruncher 3 loops in testing voltage stability
And having Aida64 by hand
If memory access latency jumps more than 0.3ns per test
then adjust procODT (first) and then voltages

Vermeer does throttle on many parts to maintain stability,
it's very hard to make it crash, but it's very easy to make it unhappy and deliver "fake" results
 

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Oh i also suggest to start with y-cruncher 3 loops in testing voltage stability
Dam that is even more brutal than p95 small ftt. It goes from ~75c first pass instantly to 90c+ in the second test and the system restarts due to overheat.
Even undervolting CPU\SOC 0.05v doesn't help.
I am running a custom loop with temps lower than a lot of 5800X users.

700 should work, we confirmed this on Matisse too
It should have the same voltage running abilities like a 2700X
What does make issues, is high procODT
Try that with 30ohm procODT
30 ohm are enough for 1900FCLK
30 ohm works nicely but it still fails to post at 700mv CLDO VDDP

  • disable SMEE
  • enforce 512 Bytes memory interleaving
  • disable memory clear
  • under NBIO -> SMU, enforce both CPPC and CPPC Preferred Cores
  • APBDIS to 0 just for good measure once SOC gets unlocked to be variable again
Changed those settings I will have a play around and see if I can notice any change.

Edit: also found a oddity where I can boot at 1900IF tCL15 but it wont post at 1900IF tCL16.
 

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Can anyone with a MSI B550 or X570 board who has Vermeer, confirm for me the max Boost Clock override - Fmax , on their board (PBO Advanced)
If you have beyond 200Mhz, please attach a zentimings screenshot , so i can read out the SMU version :)
Hi, I can go up to 500 MHz offset.
2467096

I am currently trying to get this running at good speeds while keeping low voltages, this constellation withstood AIDA64 cache and memory stress test for 1 hour, TestMem5 anta777 found 4 errors though.
So far I have changed (VDDG) CCD to .94 and IOD to 1.02, following your recommendations. I will do some stress tests with these new settings, further advice is appreciated.
Current VDIMM = 1.4 on 4 x 8GB.
 

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msi mpg B550 gaming edge wifi, 5600X, 3200c14, 2070S FTW 3 ultra, 8200SX pro 2tb nvme
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hello, kinda new..ISH to ram overclocking in which i recently went from a hynix kit J die of 3466oc to 3600cl16 and am now on teamgroup c14 3200 2x8 and am curious as to what i can do to get these timings better besides not leaving most on auto in which i had used dram calc by importing the xmp profile but the kits only rated at 3200 so im unsure if using dram calc would work that way? anyhow here are some screenshots, replying to you in general as i see your name appear the most and yes i know my 3600XT is downclocked, thats just a matter of heat atm and just testing out ram overclocking as i wasnt sure if 4.5ghz cpu oc with 1.3375volts was the cause of a crash or not so i lowered the core clock, but quickly figured out that wasnt the issue have that solved now. but seeing as to how i bought this kit just for this purpose...do you have any suggestions i should try??
2467100
 

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Dam that is even more brutal than p95 small ftt. It goes from ~75c first pass instantly to 90c+ in the second test and the system restarts due to overheat.
Even undervolting CPU\SOC 0.05v doesn't help.
I am running a custom loop with temps lower than a lot of 5800X users.
Lol :)
Yea it's brutal, but it shouldn't be thaat extreme
i remember the 5800X was very interesting
branded as "low tdp" cpu "for gamers"
But once stresstested it instantly exceed 180W but only in all core loads
No idea why EDC was soo extremely high programme - rather the microcode allowing to ouble it's own capabilities
... oh wait you have no 5900X ~ well there is the answer :p

Something on it is designed to exceeds it's capabilities only on multi core loads
I can't get my 5600X beyond 150W while on stock it stays @ 75W
It's really an interesting silicon ~ very efficient but can take soo much current if you let it
Edit: also found a oddity where I can boot at 1900IF tCL15 but it wont post at 1900IF tCL16.
This is strange :D
Yea i had one which it only wanted to post with loaded or change xmp
but not if xmp was never loaded

I will repeat again
"Don't fully open PBO, only limit it slowly. 10W PPT or 5A EDC already do a lot" :)
The same counts also or Matisse
Well written article by our member @polkfan
no need for EC bugs or per CCX OC
PBO finetuned can work even back then very well
no need to get ryzen master - HWInfo already shows all you need to know
But get it as inspiration and tutorial how things work out
AutoOC does work but shifts the boosting curve and messes stuff up on Matisse
Now we have curve optimizer to work against it
Big topic but take a look :)

In order to lower allcore voltages, you need to have EDC peaking at 100%
and TDC near 98%
PPT mostly goes for llight threaded workloads, but you need a powerplan with CPPC , soo cores actually sleep and draw less power
= more boosting headroom with less required voltage
Changed those settings I will have a play around and see if I can notice any change.
That's all i could figure out till i open up more settings on my bios
The cpu is soo variable and sensitive. Each run is unique
Once you have your target FCLK, and target voltage stable under y-cruncher 3+ cycles (3*18min)
Keep memory testing on Aida64 and change procODT across the whole range.Till 90 ohm
Your cache perf and also memory perf will change because your effective boosting will change

Other changes like powerplan starting idle state
(i suggest 7 & 10% on a full idle powersave powerplan ~ WIP)
are visible on SiSandra Multi-Core Efficiency Test (highest latency category)
Lowest latency shows boosting behavior ~ but as every little voltage change affects the outcome
It's too variable and hard to track
Latency Curve visible under "detailed" view.
~ be sure to sort by date and local results only after running one test (refresh button)
Hi, I can go up to 500 MHz offset.
View attachment 2467096
I am currently trying to get this running at good speeds while keeping low voltages, this constellation withstood AIDA64 cache and memory stress test for 1 hour, TestMem5 anta777 found 4 errors though.
So far I have changed (VDDG) CCD to .94 and IOD to 1.02, following your recommendations. I will do some stress tests with these new settings, further advice is appreciated.
Current VDIMM = 1.4 on 4 x 8GB.
This gives hope that AMD might not hardlock us out and repeat the matisse PCIe 4.0 nonsense all over again
Thank you !
I will see if i find anything valuable in this bios to extract and replicate
200Mhz override is not enough
You MSI guys also have 3 PBO profiles which seem to work very well :)
 

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This is the difference between GDM ON & GDM OFF 2T
2T is faster than 1.5T
On top of that it wipes odd primaries autocorrection
Keep working on CAD BUS -> ClkDrvStrength, till you find a strong enough impedance setting for your memory kit to run GDM off :)

2467105
2467106


Lower looking boost ~ but that's the powerplan
Lazy CL16 flat timings @ 1.46v but i've poste them here already to replicate
Still stock boost no special tweaks , ust around it optimisations
Stepped up to humane cooling away from the Wraith Stealth
But i'm again since 22h awake zZZ
Tomorrow the 50ns wall will be gone. Still have a lot of headroom & PBO let to play with
Toyed enough the last couple of days with lame scores on the stock cooler :p
 

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Vei, one thing I did not understand, you suggested to me, that my SOC is too low at 1.08v for 4 sticks (auto value) but you recommend to lower it with a negative offset of -50mv ?

Can you clarify ?

I have just switched from 2x8gb to 4x8Gb 4400c16 @ 3800c14
Main changes are GDM enabled and tWRRD 1 to 2.

View attachment 2467081
Give me some hope to get this 1800FCLK with my Strix X570 and 4 sticks.
 

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will repeat again
"Don't fully open PBO, only limit it slowly. 10W PPT or 5A EDC already do a lot"
That will teach me for thinking if I set my CPU back to stock clocks and default PBO settings that the MB would actually set default power limits.
Running nicely now I have set it manually to stay under 130w 85c.

Thanks a lot for sharing your knowledge\experience with us it is really appreciated.
 

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This is the difference between GDM ON & GDM OFF 2T
2T is faster than 1.5T
On top of that it wipes odd primaries autocorrection
Keep working on CAD BUS -> ClkDrvStrength, till you find a strong enough impedance setting for your memory kit to run GDM off :)

View attachment 2467105 View attachment 2467106

....snip
But "they" dont listen, none of them listen

It seems like having the "better" number is better than having the higher performing number

😂 😂

snip........Edit: also found a oddity where I can boot at 1900IF tCL15 but it wont post at 1900IF tCL16.
When you get such weirdness, have you tried simply going into BIOS and flicking through key timings/settings such as Cmd rate, CPU voltage by just moving the current value up/down one and then putting it back and then saving BIOS and seeing if it boots ??

I have seen such issues in the past, its as if some other settings are being changed in the background but are not showing in the BIOS menu, flicking the values then puts them where they should be....

I have just switched from 2x8gb to 4x8Gb 4400c16 @ 3800c14
Main changes are GDM enabled and tWRRD 1 to 2.

View attachment 2467081
Hi, GDM enabled with 2T is not possible ???

Also, tRDRDSCL/tWRWRSCL have better read throughput on my 3600 when using 4x8GB @4/5 than 2/3 have you test this on the 5000 series ??
 

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Pretty much yes
although don't ignore VDDG, split it :)
CCD can and should stay low this generation
too high CCD caused crashed for me on y-cruncher
high IOD is what is needed

It's funny,
on one hand this silicon is insanely power efficient
On the other hand also insanely powerhungry :p
Renoir was very similar behaving (sometimes up to 1.3vSOC)
~ seems to be the colour change

Old Matisse days i kept recommending double stepping for VDDP-VDDG and double stepping or SOC
although only because you couln't expect 1v SOC to run 1900

Today, it's rather single stepping for VDDP->VDDG CCD, double stepping for IOD and then another double for SOC
The limits on CCD (1050) IOD (1150) i would continue to hold
VDDP beyond 1050 is damaging, CCD might be pushed to 1100 but already beyond 980mV i saw issues with it
IOD beyond 1100 is already too much for this already vintage 12nm I/O-Die :)
Ok to I gave y-cruncher a go, this one is taken a while after 1st pass, it went like this longer, throwing WHEA warring in registry once in a while but test was stable,some of AVX tests pushed my cooling to 90C but chip reacted like it should and test continued stable
2467110


I left VSOC at 1.1 with LLC at 5, which give flat 1.1V all the time (leaving it on auto gives 1.081 and errors appearing faster)
CLDO VDDP - dropped to 0.9V as suggested to have a working room for others
VDDG CCD - moved from auto (0,9V) to 0,94V to separate it from VDDP - I'm not sure if it's good idea
VDDG IOD - left on auto 1,05V


Two questions:
  • seeing machine work, game & stress test stable how crazy I should be about these WHEA warnings?
  • where can I find extra stability, I can try and drop IOD to match double stepping so it'd be
VDDP 0,9V CCD 0,94V IOD 1.02 & then SOC still at 1.1V

Like I wrote a while ago, I can make things worse by adjusting these voltages. Best I got was ~1 WHEA every 4-5 minutes, instead of 4 WHEA ever minute :)
 

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Hi, GDM enabled with 2T is not possible ???

Also, tRDRDSCL/tWRWRSCL have better read throughput on my 3600 when using 4x8GB @4/5 than 2/3 have you test this on the 5000 series ??
I've only had the 2nd 16Gb a day so still woking it out.
2x8Gb I run these settings with GDM disabled but with 32Gb so far it is difficult to post so will spend more time on it.
Will test the tRDRDSCL/tWRWRSCL at the settings you suggested as well.
Thanks for your input.
 

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5600 x
ASUS ROG VIII X570 IMPACT BIOS 2702
CL16 4400 ROYAL (XMP, DOCP) 8X2

CLDO_VDDP 0.900V VDDG_IOD 1.050V VDDG_CCD 0.940 SOC 1.1V

CL14 3800 dream 1.48V
2467123
2467124


2467128



Tested with 40mv 50mv stepping.
Are there any parts to be fixed?
Please advise.
 

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I just installed a 5800x last night on my Aorus Pro Wifi. I am running 4x8 gb Trident Z Neo DJR RAM. I basically used the exact same setting that I used on my 3900x except for the VSOC, VDDP and VDDG values. I took @Veii 's advice and used increments of 40 mv when tuning the voltage values. I ran AUTO on everything just to see what the board would set. Looks like it selected 1.05v VSOC and 0.975 for all the other 3 voltages. It was decently stable, but Memtest stopped working so I had to change some values. I settled on VSOC 1.075v, VDDP 915 mv, VDDG IOD 995 mv and VDDG CCD 955 mv. Metest passed 20 cycles of 1usmus v3 and no WHEA errors! @Veii did I setup the voltages correctly based off of VSOC 1.075v?

Next, on this same BIOS I was able to POST and boot windows at FCLK 2000 (didn't try and push farther) at the default AUTO values above and set RAM at 3800. I really want to try and tune my DJR RAM and try for DDR 4000. What would be some reasonable settings to try?


2467141
2467146
 

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I just installed a 5800x last night on my Aorus Pro Wifi. I am running 4x8 gb Trident Z Neo DJR RAM. I basically used the exact same setting that I used on my 3900x except for the VSOC, VDDP and VDDG values. I took @Veii 's advice and used increments of 40 mv when tuning the voltage values. I ran AUTO on everything just to see what the board would set. Looks like it selected 1.05v VSOC and 0.975 for all the other 3 voltages. It was decently stable, but Memtest stopped working so I had to change some values. I settled on VSOC 1.075v, VDDP 915 mv, VDDG IOD 995 mv and VDDG CCD 955 mv. Metest passed 20 cycles of 1usmus v3 and no WHEA errors! @Veii did I setup the voltages correctly based off of VSOC 1.075v?

Next, on this same BIOS I was able to POST and boot windows at FCLK 2000 (didn't try and push farther) at the default AUTO values above and set RAM at 3800. I really want to try and tune my DJR RAM and try for DDR 4000. What would be some reasonable settings to try?
TM5 shouldn't generate any WHEA errors unless things are really bad, I could do this for hours, it's really good for checking memory subtimings.
Prime95 Large FFTs no AVX will do it within minutes, same with OCCT. Like in my example, I don't get any WHEA in real life scenarios unless I mess the voltages really bad.
I do get them sooner or later when I apply some heavy load & memory/controller stress, yet stress tests don't fail/crash ;)
 

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Samsung C die @3800 FCLK 1900 UCLK 1900 working in progress
 

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