edit: also what you say with 40mV steppings could look like this?
VDDP 0.94
VDDG 1.02
VSOC 1.10
Pretty much yes
although don't ignore VDDG, split it
CCD can and should stay low this generation
too high CCD caused crashed for me on y-cruncher
high IOD is what is needed
It's funny,
on one hand this silicon is insanely power efficient
On the other hand also insanely powerhungry
Renoir was very similar behaving (sometimes up to 1.3vSOC)
~ seems to be the colour change
Old Matisse days i kept recommending double stepping for VDDP-VDDG and double stepping or SOC
although only because you couln't expect 1v SOC to run 1900
Today, it's rather single stepping for VDDP->VDDG CCD, double stepping for IOD and then another double for SOC
The limits on CCD (1050) IOD (1150) i would continue to hold
VDDP beyond 1050 is damaging, CCD might be pushed to 1100 but already beyond 980mV i saw issues with it
IOD beyond 1100 is already too much for this already vintage 12nm I/O-Die
I have been unable to post over 1900IF with any BIOS so I thought I would try undervolt the SOC.
[email protected] 1.47-1.5VDIMM
VSOC 0.9313V (Offset -0.5) vs Auto 1V
CLDO VDDP 0.8V vs Auto 0.9V
VDDG IOD\CCD 0.871V (set 0.85V) vs Auto 0.9V
CLDO VDDP would not post at 0.7V and 0.75V was unstable.
Rest may be able to go lower but
Veii suggested above that CLDO VDDP should be lower than the rest so I left it at that for now.
View attachment 2467045
700 should work, we confirmed this on Matisse too
It should have the same voltage running abilities like a 2700X
What does make issues, is high procODT
Try that with 30ohm procODT
30 ohm are enough for 1900FCLK
(well even 28ohm where in the old days ~ but as this one needs more SOC overall, 28ohm is a bit too low)
VSOC 0.9313V (Offset -0.5) vs Auto 1V
This is what i figured and recommend now too
it seems to work perfectly across the whole range of "auto predicted" voltages
from 1800 till 2100FCLK
-------------------------------------------------
Just 2100 is OCP hardlocking on me still
something with proc and CCD is not fin
~ still fighting with it for day #3
might be also just a core voltage thing , i'll figure it out it just needs time
The powerplan research is halfway done
If AMD CBS is open for you guys,
- disable SMEE
- enforce 512 Bytes memory interleaving
- disable memory clear
- under NBIO -> SMU, enforce both CPPC and CPPC Preferred Cores
- APBDIS to 0 just for good measure once SOC gets unlocked to be variable again
For the rest, we need to see what's open per user
Enforcing -50mV SOC offset seems to work well
I suggest also to watch HWInfo core "quality" sorting
You can "improve" which cores are "golden cores" just by playing either with the global negative vCore offset, or the PBO Curve optimizer option
For me even PBO Scaler x2, already was enough to give it a 40-50mV lift up and then filtered down with a global negative offset
Although global offset and curve optimizer together work better than this scalar
The scalar is a bit too agressive and already at x3 is too strong for me
Oh i also suggest to start with y-cruncher 3 loops in testing voltage stability
And having Aida64 by hand
If memory access latency jumps more than 0.3ns per test
then adjust procODT (first) and then voltages
Vermeer does throttle on many parts to maintain stability,
it's very hard to make it crash, but it's very easy to make it unhappy and deliver "fake" results
