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B550 gaming edge, 5800x, 5600x, 3600xt, 1600AF, 2070S, 4x8 3200c14, 2tb adata 8200sx PRO, 500gb 970e
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@Veii upon further stress testing with 1usmus preset,
errors 9, 11, 13 rose up with 6 cycles. (tCKE 11 where as tCKE 12 had 27 errors within an hour.)

going to check and see what errors these are then do some more testing.. just thought id
share that errors indeed rose aboutz

(EDIT) scratch that, tests were not valid, tRFC 1-2-4 were all default? which do NOT in any
way go side-by-side with the frequency i have currently.

unsure why my b550 gaming edge board did this, but it did. id didnt fail to boot either?
also, FOUND out that there is a "reading" inside bios (on b550 gaming edge wifi) for
CPU VDDP but reads N/A atm. so, my guess is your bios feature unlocking trick mentioned sometime back,
would have worked if i would have tested/tried it.

anyhow, off to retest/redownload the normal config so i know for sure what errors are what.
 

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I do think people need to have access to more than one google timings calculator.
For example Ramad's

Too many people share and use exploit timings, then maybe it doesn't work on their set (RRD, WTR, tRFC , tWR)
and stay clueless as to why it doesn't work or doesn't perform ~ same goes for reviewers out there who share these broken sets

We should get some baseline calculator following JEDEC rules
I see too many exotic sets and many users don't really have any clue why they use it.

Flat timings perform better, unless the exploit ones are correctly in sync.
People see them as "easy to run" and just use them - without putting work in actually lowering primaries (tRCD)
At this point close to everyone here should be able to run a flat CL14-14 set @ 3800 ~ with all the information that's out there in this thread
Later fix RTTs and step up to 3800C13-13-13 in the range of 1.64-1.68v
if frequency can't be pushed higher to for example 4000C14-14-14 or 4200C15-15-15

Don't focus your time on exploits when you aren't even close to 3800CL14-14-14 :)
Just as a suggestion and rant~
I kept thinking about what you said Veii, it's very true. There is a lot of information, for the newest it takes a bit to manage some relationships. But I know I'm going to make it! in fact last night I tried it .. but TM5 gave me countless errors. I think, and maybe I'm wrong, that to achieve it I would need more than 1.6V and I also don't know more about IOD and CCD ... and about the timings, more or less it will be a matter of loosing some more, calculating the tRFCs and then a good combination of RTT and CadBus. But I don't know why I see that the key is to increase the voltage. maybe with 1.57 not reach. Thank you as always for your great help and contribution to all OCN members


Sent from my iPhone using Tapatalk Pro
 

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B550 gaming edge, 5800x, 5600x, 3600xt, 1600AF, 2070S, 4x8 3200c14, 2tb adata 8200sx PRO, 500gb 970e
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Considering im unsure how to post this from another section, this was made by Veii a few months back (8 or so it says)

this will HELP ALL who are trying, are close to stable but not 100% stable

copied and pasted, again this was wrote by @Veii (if you mind me copy/pasting this, simply lmk and ill remove asap)
unsure if the inital data was conducted only by veii, but none the less, credit where its due has been processed.

(will be using this myself, make a bookmark of it new comers itll come in handy quite a bit)


Spoiler
  • tCL 16 up to IC & every 4 steps or 200Mhz +1 tCL
  • tRCD = tCL +2
  • tRP = tRCD
  • tRAS = tCL + tRCD
  • tRC = tRAS+tRP
  • tRFC = (0.35*(MT/s /2)) <- JEDEC, or my method ((tCLns*tRC)*MT/s)/2000.
  • tFAW = 8* tRRD_S. SR= 4-6 . . DR=6-8
  • tWR = tRCD-tRAS <- SR, double (*2) for DR
  • tRTP = tWR/2
  • tWTR_ = 4-12 SR , 6-16 DR
  • tRDWR = tRCD/2+2, tWRRD=1
Stable
Spoiler
  • tCL manual input, user should have run Failsafe first
  • tRCD = tCL +2
  • tRP = tRCD
  • tRAS = tCL+tWR+4
  • tRC = tRP+tRAS
  • tRFC = 8* tRCns
  • tFAW = 4* tRRD_S. SR= 4-6 . . DR=5-7
  • tWR = tRTP*2 ~ SR, *4 for DR
  • tRTP = use tRFC multiplier = always 8
  • tWTR_ = 4-12 SR , 5-14 DR
  • tRDWR = tRCD/2+1, tWRRD=tRCD/4, round down
Fast
Spoiler
  • tCL manual input, round up if GDM is enabled
  • tRCD_RD = tCL if B-die, +1 GDM off, +2 GDM on everything that's not B-die
  • tRCD_WR = ^ _RD-2
  • tRP = tRCD_RD+tRCD_WR / 2 = round up
  • tRAS = tCL+tWR+4
  • tRC = tRCD_WR+tWR+tCWL+4
  • tRFC = tCL/2 * tRCns
  • tFAW = 4* tRRD_S. SR= 4-6 . . DR=5-7
  • tWR = tRTP*2 ~ SR, *4 for DR
  • tRTP = use tRFC multiplier ~ if GDM off round down, if GDM on round up (if 7.5 round to 8)
  • tWTR_S = tRRD_S
  • tWTR_L = tRRD_L * 2
  • tRDWR = tRCD_RD/2 + 1, tWRRD=tRCDavg / 4, round down
Extreme
Spoiler
  • tCL manual input, round up if GDM is enabled
  • tRCD_RD = tCL if B-die, +1 GDM off, +2 GDM on everything that's not B-die
  • tRCD_WR = ^ _RD-4
  • tRP = tRCD_RD+tRCD_WR / 2 = round up
  • tRAS = tCL+tWR+4
  • tRC = tRCD_WR+tWR+tCWL+4
  • tRFC = 6 * tRCns
  • tFAW = 4* tRRD_S. SR= 4-4 . . DR=4-6
  • tRTP = use tRFC multiplier ~ if GDM off round down, if GDM on round up (if 7.5 round to 8)
  • tWR = tRTP*2 ~ SR, *4 for DR
  • tWTR_S = tRRD_S
  • tWTR_L = tRRD_S * 2
  • tRDWR = tRCD_RD/2, tWRRD=4*SCL, round down
 

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B550 AORUS MASTER, 5800X, 16GB (2×8GB) TEAMGROUP UD4-4000 DDR4 memory, XFX RX 5500 XT
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If anyone is interested I found an amazing review by Reous which tests the performance benefit of tightening each timing. Why bother running some timings at the bleeding edge of stability when it doesn't really increase performance much?

You go step by step :)

Doing too many changes, puts you in a rabbit hole situation

Where you just don't know where you've messed up

Increasing frequency , increasing resistance, changing procODT

all can lead to a startover with timings creation

Soo you lower stuff step by step and see where it fails

after all every kit is unique - only the "baseline" is calculable

Tightening it more is from kit to kit unique , and even from the same model number unique :)

The benchmark [#y-cruncher], will end after all tests are done - but it's considerable to loop it twice at least
SiSandra is a valid benchmark to notice timing differences ^^'

In the configuration setup there is a toggle for "stop on error" But if no errors found, it [#y-cruncher] will loop continuously until you stop it.
It [#y-cruncher] behaves very similar to LinpackXtreme

It will loop forever :)

A stresstest after all
Just test everything :) [#y-cruncher]

All of the tests use different instruction sets and so applied current voltage will differ

You want to run stresstest mode and select all tests

Time to pass, are results times ~ usually it takes 2-3min each test for about 8 tests

Passing two times the whole set of tests is usually enough, but likely we can optimize that in the future better

First 3 tests will always fail if there is an issue with fabric clock :)

Some ryzen chips fail that on stock, but usually non should fail this
Error 11 seems to be related to timings. [#TM5]
@pikmin define passed

6 rounds or 20 rounds [#TM5]

some errors like bad tRFC appears only after 19 rounds - about 1:30h exactly before TM5 20 rounds end

Another good testing tool is passing y-cruncher the first 3 tests couple of times

As they will fail when the memory controller fails

^ which are then more voltage related by still go hand in hand with memory OC
EDIT:

You run SerJ's config on TM5

Results on that one don't matter

What you want is the 1usmus_v3 config 20 rounds, which is 1:30h for 16GB or 3h for 32GB

I've attached my TM on it, if you don't want to search, but yes - you load the wrong config for the test

VDDG should be at least 50mV lower than the SOC voltage (which goes up to 1.1V "safely") => max VDDG = 1.050V
found GDM needed 0.01v/0.02v more DRAM voltage than 2t for some reason, if GDM is throwing errors in testmem5 then that's what's probably caused it to benchmark worse too.
Ryzen master shows the correct SOC/VDDG/VDDP voltages, if you set the SOC/VDD voltages under the AMB CBS/Overclocking menu in bios. I have to have my motherboard SOC voltage control on auto for that to work though.
Anyways, it's a precharge delay issue, on a small burst test

If 1.53v doesn't resolve that, you rly have to change timings a bit

EDIT: Having low tRP needs higher voltage soo current remains a bit
VDDP might be uselessly that high , could try cutting 25mV on it too ~ might be even 50mV away

As 950mV cLDO_VDDP, 1025mV cLODO_VDDG and same 1.1v vSOC

if VDDP is too low, your procODT is a bit too high

work with CAD_BUS against it to fix it - the first value
Error test 10 is under a simple test size 8mb, it's a burst test / mostly voltage related, more delay related on cell precharge

Test 11 error is a normal delay for 16mb block size, this is rather timings related

I can imagine it's copy, error, read error, copy error - what happened here

tRP is either to low, tWR too low or you lowered vDIMM voltage

anyhow, somewhere you choke on a burst write and read test :)

But it's not a chargeback error, else test 9 would error with a blocksize of 4mb

(that is rather a SOC voltage or too low vDIMM error)

Error 6 and 12 belong to the memory controller

which come together, first error 6 size 1mb that is initialization error , either 4-5 times error 6=BSOD or 6,12

Error on test 12 is blocksize 32mb error

Very often just resistance choke, either by too low vSOC or too high procODT/cad_BUS

rly depends on the amount of errors followed one after another

This current one is more a burst test error, which is either delay or voltage related

mostly precharge delay, because of error 11 which is more a writeback error after test 10

EDIT:

As it either is delay or tRP/voltage related - try to push tWRRD to 3 instead of two

Or put tRP higher
Can't say at what point Samsung B-dies require maxmem , but it should be near that value

afterwards it needs to drop to 2gb per IC - in order to use voltages like 1.6 or 1.72v

an architectural flaw on b-dies

Don't entirely know 20nm degradation point, except 1.5v is known as the widespread JEDEC max spec for 24/7 operation on this nm nodesize

haven't had a dead memory kit so far to say what's absolute max :D

But it's known that near 1.56-1.58v it will require maxmem 4096mb in order to even post to windows
You are at 3800MT/s

CL15 is no joke on this speed :)

Some need 1.56v on 3600MT/s to hit CL14

1.5v on very good kits can run 3800CL14

not unexpected to need 1.48v for very low tRFC and low timings :)

1.46v is about the sweetspot for bad and good b-dies, 1.48v only for good binns of b-dies

the bad ones don't like over 1.46v
Sorry to be clear this is for solving memory holes, not issues with FCLK not posting. The only suggestion I have on that front is to try booting at 1867MHz, setting 1.15V SOC and 1.95V PLL (might be called 1P8 if you have an MSI board) and rebooting (still at 1867MHz) then setting 1900MHz FCLK and rebooting. This is because some voltages seem to be modified later in the boot process than the FCLK clock is set, so I always modify voltages THEN set FCLK.

Some of you have been asking for the spreadsheet that I use to calculate timings. I made it more user friendly for you with 4 input fields. You can fill the first 3 fields (1-3) and ignore the fourth field if you don't want to use tRC_Page option in the BIOS (set to 0 in the BIOS).

How to use:

There are 4 fields that can be used, the rest of the spreadsheet is locked, to prevent mistyping that can lead to miscalculating. The 4 input fields that can be used are colored light green and are marked Input 1 to Input 4.

Input 1: in MT/s is used to calculate the required primary and subtimings.

Input 2: in MT/s is used to calculate IMC timings.

Input 3: in MT/s is used to calculate tRFC, tRFC/2 and tRFC/4 timings.

Input 4: chose 200, 300, 400, 500, 600 or 700 to calculate tRC_PAGE timing.

Example:

I want to run my RAM at 3800MT/s and want tighter timings than default 380MT/s timings. I choose to use 2133MT/s or 2400MT/s...etc. timings for my RAM that is to run at 3800MT/s. This is how it's done:

Input 1: Write 2133
Input 2: Write 3800
Input 3: Write 3800
Input 4: Write 200 (that is 200K). You don't have to fil this field if you don't want to activate tRC_PAGE function in the BIOS, 0 in the BIOS means that tRC_PAGE is deactivated.
The spreadsheet will display the following result :

2486942

My RAM dies have a density of 8Gb (gigabit), so I will be using 8Gb tRFC timings and 1KB values for tRRD_S, tRRD_L and tFAW.

Rounding up:

The calculated timings must be rounded up, i.e. 3.04CK = 4CK, 13.75CK = 14CK and 5.5 = 6CK.

IMC timings:

These are based on my experience with Zen and Zen+, your IMC may be able to tolerate tighter timings or require looser timings, that's up to the quality of the silicone.

tRC_PAGE:

AMD provides 2 methods to calculate tRC_PAGE:

Approximation: tRC_PAGE = tMAW/MAC

Exact: tRC_PAGE = (tMAW - tRFC*(tMAW/tREFI))/MAC

The results of the calculations above will be in [ns] that is required to be converted to clock cycles.

Note:

tMAW = 64ms.

tREFI = 7.8us.

MAC: number of accessible rows.

I hope that find this tool useful. :)

Link: DDR4 Timings for AMD ZEN

(SHA256: F2A6B863109FAD9D2A2F75A5F209D4B12FB6B230C55A5A45A349EE5A469CBA00)
Yes, this tRFC was not possible he got errors - not even with factoring in tSTAG to lower it, it was far to low and needs tRFC 40 at least

or minimum 42, 44 was far too high for it ~ 240 works on lower timings but not on this set

tRFC 240 would be 126.3157895ns with tRC 40

It would make more sense to use something like this set:

Where 140ns update time is less harsh to the chips, than going <130ns update cycle

EDIT:

You can optionally use that for 32gb Dimms, or also go even further down to tRAS 26

- but tBL 4 won't work with this set, it's based on tBL 2

You will need to go tWR 10 for that in order to get tRAS formular right

And in order to go tWR 10, it needs to be tRAS-tRCD which works only with tRCD RD 6 + tCL 12

tRCD RD 8, WR 14 results in 12 average

26 tRAS - 12 tRCD = 12 tWR not 10 tWR

and tRRD_S+tWTR_S = 8 tWR not 10

It's complicated :D

If you push tWTR_S/L as 6-6 , this formula might work to run tRAS 26 :rolleyes:

Else we need bios-mods allowing to use tWR 8 :ninja:
TRTP needs to be at least half of TWR on my kit or it wont post. Try TRPT of 10 with TWR of 20, or 8/16.
Two things

get tRFC2 and tRFC4 correct because you use GDM

soo tCKE will work too

if you already did , then try to scale up tCKE to 6 slowly

and even if at 6 it doesn't do anything

try tRRDL on 5

Unsure about tWTRL on 8, 3-10 would it be or 4-12
Your optimal tWR is between 10,12,14, at least tRAS-tRCD is 14 or 16

Yes 16 can run well but try to change for now tWRRD to 3

If that doesn't work it's tWR to 16 try - if it doesn't post, you have to keep it 14 or lower

if you use 14, better use tRTP 8 not 6

Else tWR 12
tWR should be in sync with tRFC if possible , if not possible at least tRTP has to be

Preferable to keep tWR in sync and see if how tRTP behaves, if 6 is possible else just half of current tWR

I am pretty sure with tSTAG inside the tRFC calculation , it will show what of both has to be a perfect half

But i have the suspension, it doesn't matter here that much

Because in order for it to matter a lot, timings have to be turned into ns and the math being done

there is too much variability on whole virtual values to predict perfect results :)

At worst the board does autocorrect anyways, but try to keep it a divider if you can

It's no "has to be" rule - it's a strong recommendation for tWR to be a divider of tRFC

The less wasted latency you have across the remain timings, the less it would matter if it's a tiny tiny bit offsync ~ as it's corrected anyways
tWR is optimally near the 8ns which is 8*MT/s divided by 2000

(8*3734)/2000= 14.936ns, 15 would be the optimal - BUT

according to 1usmus's research is lower tWR still beneficial

I'm doubting that formular a bit as write recovery depends on more than just running frequeuncy

It depends on tCL and tRTP , but i have no perfect formular for it - 1usmus knows more

Lowest tWR=

tRRDS+tWTRS

Highest tWR=

tCL + tRTP

Alternative Option:

tRAS-tRCD (Biggest)

Recommended is value between lowest tWR

And Alt. - one in between, should be mostly lowest tWR +2, or Alt tWR -2

tWR has to be an even value, but as there is more to it than 8ns of x Frequency, use the math formular above only to orient yourself where you want to be

For 3200MT/s for example 8*3200/2000=12.8 and tWR 12 runs wonderfully there

Divided by 2000 is for turning virtual values into nanosecounds

tCL 16 = 8.57ns

((8,57*3734)/2000)= 16,00019

To be more accurate, tCL 16 = 8.56989823245849ns

Soo you can see why boards do autocorrect :p

Starting with 3734MT/s being more like 3733,333336 - which is a fundamental error in getting perfect timings

The DDR frequency is already rounded down which causes math errors, and tRFC accuracy does suffer from that

tRDWR & tWRRD has no perfect rule, only one that is trial and error


It's flawed and depends on dual or single ranked, but it's functional and usable

We noticed tCWL = tCL , for this ruleset

If it's lower, it will prevent low tRDWR to post
1-1-1 1-1-1 was an alternative when you use awkward timings, it does lower performance but is more stable
SLC you have to drop to at least 3, tRDWR might be workable with

and then maybe something 16-14-14-16 can run in the future with lower tRAS and tRC

You need to go methodological on it

First is lowering SLC and testing how low you can get tRFC before the kits start to choke by too high latency from the main 3 timings (tCL,tRCD,tRP)

Later you lower tRCD and at the same time always finetune tRDWR & tWRRD

Then you check how low tRP can go with your voltage and at best and last try if you can lower tCL

tCL goes at last
tRFC is lower than usual because tRC is already -2

-4 is about the max i've seen, but i didn't see a testing rabbit to explore what it negatively affects by going that low in tRC

surely messes up something :)

-2 on dual rank is hard, but on single rank kits it's easy to do and let's you use very low tRFC

but tRAS has to stay as a clean transition or on slow ICs with (like you mentioned) added artificial delay

Although, just increasing tRP instead tRAS does work too - at the end both will influence tRC

* depends really if recharge after write was too slow or just globally everything was too harsh soo tRP bump would help
low tRAS only results in a wait-for-command-completion-before-action scenario

It does nothing than just slow down things and at worst error out memory tests for mysterious reasons :D

Appearing that often, makes me think it's some guide somewhere

tRAS can only be lower than tCL+tRTC if you abuse memory heterogeneity ~ which i doubt many read

And that tCL+tWR+tBL method for it, would nearly always cause trouble if the rest is not as tight as possible :eek:
Seen this issue today for the 3rd time already

minimum tRAS for you is not 28 - it's far to low

30 or 32 is your value

tRC doesn't have to be a clean perfect math, but tRAS has to be, else it waits the whole time for commands to pass

Put tRAS to 30 and at best & increase tWR to 14

only memory voltage is preventing you to boot CL15 , but you can try later adding tWRRD 3 if it changes stability

But it will lower timing efficiency

Else next step is lowering SCL to 3

EDIT:

Will this post under 1.48vDIMM

tCL 16 up to IC & every 4 steps or 200Mhz +1 tCL
tRCD = tCL +2
tRP = tRCD
tRAS = tCL + tRCD
tRC = tRAS+tRP
tRFC = (0.35*(MT/s /2)) <- JEDEC, or my method ((tCLns*tRC)*MT/s)/2000.
tFAW = 8* tRRD_S. SR= 4-6 . . DR=6-8
tWR = tRCD-tRAS <- SR, double (*2) for DR
tRTP = tWR/2
tWTR_ = 4-12 SR , 6-16 DR
tRDWR = tRCD/2+2, tWRRD=1
tCL manual input, user should have run Failsafe first
tRCD = tCL +2
tRP = tRCD
tRAS = tCL+tWR+4
tRC = tRP+tRAS
tRFC = 8* tRCns
tFAW = 4* tRRD_S. SR= 4-6 . . DR=5-7
tWR = tRTP*2 ~ SR, *4 for DR
tRTP = use tRFC multiplier = always 8
tWTR_ = 4-12 SR , 5-14 DR
tRDWR = tRCD/2+1, tWRRD=tRCD/4, round down
tCL manual input, round up if GDM is enabled
tRCD_RD = tCL if B-die, +1 GDM off, +2 GDM on everything that's not B-die
tRCD_WR = ^ _RD-2
tRP = tRCD_RD+tRCD_WR / 2 = round up
tRAS = tCL+tWR+4
tRC = tRCD_WR+tWR+tCWL+4
tRFC = tCL/2 * tRCns
tFAW = 4* tRRD_S. SR= 4-6 . . DR=5-7
tWR = tRTP*2 ~ SR, *4 for DR
tRTP = use tRFC multiplier ~ if GDM off round down, if GDM on round up (if 7.5 round to 8)
tWTR_S = tRRD_S
tWTR_L = tRRD_L * 2
tRDWR = tRCD_RD/2 + 1
tWRRD = (tRCD_RD + tRCD_WR) ÷ 4 (round down)
tCL ---> lowest stable value (round up to the next highest even value if GDM is set to Enabled)
tRCD_RD ---> = tCL (if equipped with Samsung B-die, set = tCL + 1 [GDM set to Disabled], everything not equipped with B-die, set = tCL + 2 [or B-die with GDM set to Enabled])
tRCD_WRtRCD_RD - 4
tRP = (tRCD_RD + tRCD_WR) ÷ 2 (round up)
tRAS = tCL + tWR + 4
tRC
= tRCD_WR + tWR + tCWL + 4
tRFC
= tRC (in ns) × 6
tFAW
= tRRD_S × 4
tRTP
= tRFC multiplier (round down if GDM is set to Disabled, up if GDM is set to Enabled)
tWR = tRTP × 2 (SR); × 4 (DR)
tWTR_S = tRRD_S
tWTR_L
= tRRD_S × 2
tRDWR
= tRCD_RD ÷ 2
tWRRD
= SCL(s) × 2 (round down)
 
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Registered
Overclocking - latest technology
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369 Posts
Considering im unsure how to post this from another section, this was made by Veii a few months back (8 or so it says)

this will HELP ALL who are trying, are close to stable but not 100% stable

copied and pasted, again this was wrote by @Veii (if you mind me copy/pasting this, simply lmk and ill remove asap)
unsure if the inital data was conducted only by veii, but none the less, credit where its due has been processed.

(will be using this myself, make a bookmark of it new comers itll come in handy quite a bit)


Spoiler
  • tCL 16 up to IC & every 4 steps or 200Mhz +1 tCL
  • tRCD = tCL +2
  • tRP = tRCD
  • tRAS = tCL + tRCD
  • tRC = tRAS+tRP
  • tRFC = (0.35*(MT/s /2)) s)/2000.
  • tFAW = 8* tRRD_S. SR= 4-6 . . DR=6-8
  • tWR = tRCD-tRAS
  • tRTP = tWR/2
  • tWTR_ = 4-12 SR , 6-16 DR
  • tRDWR = tRCD/2+2, tWRRD=1
Stable
Spoiler
  • tCL manual input, user should have run Failsafe first
  • tRCD = tCL +2
  • tRP = tRCD
  • tRAS = tCL+tWR+4
  • tRC = tRP+tRAS
  • tRFC = 8* tRCns
  • tFAW = 4* tRRD_S. SR= 4-6 . . DR=5-7
  • tWR = tRTP*2 ~ SR, *4 for DR
  • tRTP = use tRFC multiplier = always 8
  • tWTR_ = 4-12 SR , 5-14 DR
  • tRDWR = tRCD/2+1, tWRRD=tRCD/4, round down
Fast
Spoiler
  • tCL manual input, round up if GDM is enabled
  • tRCD_RD = tCL if B-die, +1 GDM off, +2 GDM on everything that's not B-die
  • tRCD_WR = ^ _RD-2
  • tRP = tRCD_RD+tRCD_WR / 2 = round up
  • tRAS = tCL+tWR+4
  • tRC = tRCD_WR+tWR+tCWL+4
  • tRFC = tCL/2 * tRCns
  • tFAW = 4* tRRD_S. SR= 4-6 . . DR=5-7
  • tWR = tRTP*2 ~ SR, *4 for DR
  • tRTP = use tRFC multiplier ~ if GDM off round down, if GDM on round up (if 7.5 round to 8)
  • tWTR_S = tRRD_S
  • tWTR_L = tRRD_L * 2
  • tRDWR = tRCD_RD/2 + 1, tWRRD=tRCDavg / 4, round down
Extreme
Spoiler
  • tCL manual input, round up if GDM is enabled
  • tRCD_RD = tCL if B-die, +1 GDM off, +2 GDM on everything that's not B-die
  • tRCD_WR = ^ _RD-4
  • tRP = tRCD_RD+tRCD_WR / 2 = round up
  • tRAS = tCL+tWR+4
  • tRC = tRCD_WR+tWR+tCWL+4
  • tRFC = 6 * tRCns
  • tFAW = 4* tRRD_S. SR= 4-4 . . DR=4-6
  • tRTP = use tRFC multiplier ~ if GDM off round down, if GDM on round up (if 7.5 round to 8)
  • tWR = tRTP*2 ~ SR, *4 for DR
  • tWTR_S = tRRD_S
  • tWTR_L = tRRD_S * 2
  • tRDWR = tRCD_RD/2, tWRRD=4*SCL, round down
Great summary! It will help us a lot!! Thanks


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Hi! I was trying to lower the primaries and take the opportunity as a reference to copy the values from the Igors Lab review. Adapt some values, adjust, release, however I don’t see much difference with my previous values that I made with the help of @Veii where the times were looser, and it used 1.5V of VDIMM vs the new ones more adjusted to 1.55v. I must be at the limit of performance, and for the results I would stay with the previous values, due to the lower voltage and also because I did many stability tests, not so with the copy of Igor's I thought that with flat values 14-14-14 24 would be better, or maybe I should raise the tRAS to 28 and try ..
View attachment 2486668
AIDA timings
View attachment 2486669
everything there both results are margin of error choose the stable one call it a day if is less voltage even better you aint going to win vs the hard cap of IF
only IF you can do more than 1900 thats that
 

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everything there both results are margin of error choose the stable one call it a day if is less voltage even better you aint going to win vs the hard cap of IF
only IF you can do more than 1900 thats that
It's not really a good comparison since I never really got 3800-14-14-14. Although it managed to boot into windows, in TM5 it was full of errors. Today I spent about 6 hours reading and testing .. TM5 gave me 6 errors in the first 1usmus test and sometimes it gave me 3 zeros and 3 sixes, so reading the errors and their events from Veii's worksheet, check the SCL values, the tWRRD, then when it only had 6 continuous errors .. then it also looked for the voltage .. I got to VDIMM of 1.6 .. I followed all the rules that I could but I couldn't. It can't be that hard, I know I'm close so I'll keep reading and trying. Always with the caution of use a weak RTTs so as not to have problems with high voltage. I'll do it, it's not that easy. And of course the results of the bench that I shared are not reliable since with so many errors it must be auto correcting everything .. so I will continue another day.

I see that many achieve it with memories of 3200 or 3600, and these that are a new model 3800CL14 should be easier, but it is not! at least for me.
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It can't be that hard......

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😂😂😂

Good luck with that, I really mean it, as the reality shows that 3800/1900 using flat 14s is extremely difficult to achieve otherwise we would seen many users posting legitimate results under memory subsystem stresstests, but we dont see this!

You either need to have tremendous fortune in having hardware that can do it from the get go, or you need to start binning memory modules and CPUs and maybe even motherboards to get to those flat 14s, no amount of tweaking is going to get you there unless the hardware is capable.

The killer is tRCDRD, ive spent many hours trying, often return to it every once in the while after learning something "new" but only to have the same results, failure.

Also you need to be aware, although we have rulesets, what these dont take into account is the differenence in electrical characteristics of the PCBs that the memory modules sit on, my experience when dealing with this issue is that voltage is only going to get you so far, many times you need to reduce voltage and tweak other values such as Rtt's and drive strength values, but ofcourse this also changes depending on the frequency/timings you are aiming for.

Example 4133/2067 using flat 16s will error out using 1.52v for vDIMM but works fine using 1.47v !
 
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Good luck with that, I really mean it, as the reality shows that 3800/1900 using flat 14s is extremely difficult to achieve otherwise we would seen many users posting legitimate results under memory subsystem stresstests, but we dont see this!

You either need to have tremendous fortune in having hardware that can do it from the get go, or you need to start binning memory modules and CPUs and maybe even motherboards to get to those flat 14s, no amount of tweaking is going to get you there unless the hardware is capable.

The killer is tRCDRD, ive spent many hours trying, often return to it every once in the while after learning something "new" but only to have the same results, failure.

Also you need to be aware, although we have rulesets, what these dont take into account is the differenence in electrical characteristics of the PCBs that the memory modules sit on, my experience when dealing with this issue is that voltage is only going to get you so far, many times you need to reduce voltage and tweak other values such as Rtt's and drive strength values, but ofcourse this also changes depending on the frequency/timings you are aiming for.

Example 4133/2067 using flat 16s will error out using 1.52v for vDIMM but works fine using 1.47v !
Well yeah I'm a little tired but then Veii appears and says let's go! Anyone could do it with all the information in this forum. Also, I had an expectation about this new 380CL14 native memory, maybe it's just marketing. But I paid what would be 2 kits of some ballistixs easily. That leads me to continue. Also, I saw Igor's lab review and all the timings are there but, as Veii mentioned, some seem to be wrong. I must admit that my timings that I achieved with the help of Veii are incredible. Good bandwidth. Low latency. I should leave everything like this. He also helps me with the curve, and I have a very good PBO2 curve, the only thins is the latest BIOS that seems to have something broken. But so far I’m extremely happy with my results.


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Big thanks to Veii and Kedarwolf....

Ive been a long time lurker here and im only just delving into ryzen dram timings

Progress so far...



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Considering im unsure how to post this from another section, this was made by Veii a few months back (8 or so it says)

this will HELP ALL who are trying, are close to stable but not 100% stable

copied and pasted, again this was wrote by @Veii (if you mind me copy/pasting this, simply lmk and ill remove asap)
unsure if the inital data was conducted only by veii, but none the less, credit where its due has been processed.

(will be using this myself, make a bookmark of it new comers itll come in handy quite a bit)


Spoiler
  • tCL 16 up to IC & every 4 steps or 200Mhz +1 tCL
  • tRCD = tCL +2
  • tRP = tRCD
  • tRAS = tCL + tRCD
  • tRC = tRAS+tRP
  • tRFC = (0.35*(MT/s /2)) <- JEDEC, or my method ((tCLns*tRC)*MT/s)/2000.
  • tFAW = 8* tRRD_S. SR= 4-6 . . DR=6-8
  • tWR = tRCD-tRAS <- SR, double (*2) for DR
  • tRTP = tWR/2
  • tWTR_ = 4-12 SR , 6-16 DR
  • tRDWR = tRCD/2+2, tWRRD=1
Stable
Spoiler
  • tCL manual input, user should have run Failsafe first
  • tRCD = tCL +2
  • tRP = tRCD
  • tRAS = tCL+tWR+4
  • tRC = tRP+tRAS
  • tRFC = 8* tRCns
  • tFAW = 4* tRRD_S. SR= 4-6 . . DR=5-7
  • tWR = tRTP*2 ~ SR, *4 for DR
  • tRTP = use tRFC multiplier = always 8
  • tWTR_ = 4-12 SR , 5-14 DR
  • tRDWR = tRCD/2+1, tWRRD=tRCD/4, round down
Fast
Spoiler
  • tCL manual input, round up if GDM is enabled
  • tRCD_RD = tCL if B-die, +1 GDM off, +2 GDM on everything that's not B-die
  • tRCD_WR = ^ _RD-2
  • tRP = tRCD_RD+tRCD_WR / 2 = round up
  • tRAS = tCL+tWR+4
  • tRC = tRCD_WR+tWR+tCWL+4
  • tRFC = tCL/2 * tRCns
  • tFAW = 4* tRRD_S. SR= 4-6 . . DR=5-7
  • tWR = tRTP*2 ~ SR, *4 for DR
  • tRTP = use tRFC multiplier ~ if GDM off round down, if GDM on round up (if 7.5 round to 8)
  • tWTR_S = tRRD_S
  • tWTR_L = tRRD_L * 2
  • tRDWR = tRCD_RD/2 + 1, tWRRD=tRCDavg / 4, round down
Extreme
Spoiler
  • tCL manual input, round up if GDM is enabled
  • tRCD_RD = tCL if B-die, +1 GDM off, +2 GDM on everything that's not B-die
  • tRCD_WR = ^ _RD-4
  • tRP = tRCD_RD+tRCD_WR / 2 = round up
  • tRAS = tCL+tWR+4
  • tRC = tRCD_WR+tWR+tCWL+4
  • tRFC = 6 * tRCns
  • tFAW = 4* tRRD_S. SR= 4-4 . . DR=4-6
  • tRTP = use tRFC multiplier ~ if GDM off round down, if GDM on round up (if 7.5 round to 8)
  • tWR = tRTP*2 ~ SR, *4 for DR
  • tWTR_S = tRRD_S
  • tWTR_L = tRRD_S * 2
  • tRDWR = tRCD_RD/2, tWRRD=4*SCL, round down
so for my DR kit 2x16gb tWR need tRTP*4 ?
 

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Alright, I think I'm damn near finished working up a "2T/GDM Disabled" timing set... I guess we'll see once the TM5 cycles are all completed

Second to last iteration of tuning/testing for stability (passed 60× cycles of TM5 with 1usmus config file)
2486930

Current iteration of tuning/testing for stability, I'm liking the lesser temps
2486931
 

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Some of you have been asking for the spreadsheet that I use to calculate timings. I made it more user friendly for you with 4 input fields. You can fill the first 3 fields (1-3) and ignore the fourth field if you don't want to use tRC_Page option in the BIOS (set to 0 in the BIOS).

How to use:

There are 4 fields that can be used, the rest of the spreadsheet is locked, to prevent mistyping that can lead to miscalculating. The 4 input fields that can be used are colored light green and are marked Input 1 to Input 4.

Input 1: in MT/s is used to calculate the required primary and subtimings.
Input 2: in MT/s is used to calculate IMC timings.
Input 3: in MT/s is used to calculate tRFC, tRFC/2 and tRFC/4 timings.
Input 4: chose 200, 300, 400, 500, 600 or 700 to calculate tRC_PAGE timing.

Example:
I want to run my RAM at 3800MT/s and want tighter timings than default 380MT/s timings. I choose to use 2133MT/s or 2400MT/s...etc. timings for my RAM that is to run at 3800MT/s. This is how it's done:

  • Input 1: Write 2133
  • Input 2: Write 3800
  • Input 3: Write 3800
  • Input 4: Write 200 (that is 200K). You don't have to fil this field if you don't want to activate tRC_PAGE function in the BIOS, 0 in the BIOS means that tRC_PAGE is deactivated.
The spreadsheet will display the following result :

2486942


My RAM dies have a density of 8Gb (gigabit), so I will be using 8Gb tRFC timings and 1KB values for tRRD_S, tRRD_L and tFAW.

Rounding up:
The calculated timings must be rounded up, i.e. 3.04CK = 4CK, 13.75CK = 14CK and 5.5 = 6CK.

IMC timings:
These are based on my experience with Zen and Zen+, your IMC may be able to tolerate tighter timings or require looser timings, that's up to the quality of the silicone.

tRC_PAGE:
AMD provides 2 methods to calculate tRC_PAGE:

Approximation: tRC_PAGE = tMAW/MAC
Exact: tRC_PAGE = (tMAW - tRFC*(tMAW/tREFI))/MAC


The results of the calculations above will be in [ns] that is required to be converted to clock cycles.

Note:
tMAW =
64ms.
tREFI = 7.8us.
MAC: number of accessible rows.

I hope that find this tool useful. :)

Link: DDR4 Timings for AMD ZEN
(SHA256: F2A6B863109FAD9D2A2F75A5F209D4B12FB6B230C55A5A45A349EE5A469CBA00)
 

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Guys, I have an issue with TestMem5, 1usmus_v3 profile. Sometimes the test would stop (randomly) and just hangs, looks like in between the cycles. The memory is deallocated, and it says <number> mS/Gb and the current test number isn't marked blue anymore. The config seems to be stable, other tests show no erros. Anyone happen to have the same issue?

 

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Some of you have been asking for the spreadsheet that I use to calculate timings. I made it more user friendly for you with 4 input fields. You can fill the first 3 fields (1-3) and ignore the fourth field if you don't want to use tRC_Page option in the BIOS (set to 0 in the BIOS). I will be adding a short "how to use" guide in this post.

Link: DDR4 Timings for AMD ZEN
(SHA256: F2A6B863109FAD9D2A2F75A5F209D4B12FB6B230C55A5A45A349EE5A469CBA00)
It just says the sheet is protected if I try and change anything?
 

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Guys, I have an issue with TestMem5, 1usmus_v3 profile. Sometimes the test would stop (randomly) and just hangs, looks like in between the cycles. The memory is deallocated, and it says mS/Gb and the current test number isn't marked blue anymore. The config seems to be stable, other tests show no erros. Anyone happen to have the same issue?
Yes, the same things happens to me but with Anta777. I don’t know why. I installed a new copy.. because it’s the last one but sometimes it’s stop.



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😂😂😂

Good luck with that, I really mean it, as the reality shows that 3800/1900 using flat 14s is extremely difficult to achieve otherwise we would seen many users posting legitimate results under memory subsystem stresstests, but we dont see this!

You either need to have tremendous fortune in having hardware that can do it from the get go, or you need to start binning memory modules and CPUs and maybe even motherboards to get to those flat 14s, no amount of tweaking is going to get you there unless the hardware is capable.

The killer is tRCDRD, ive spent many hours trying, often return to it every once in the while after learning something "new" but only to have the same results, failure.

Also you need to be aware, although we have rulesets, what these dont take into account is the differenence in electrical characteristics of the PCBs that the memory modules sit on, my experience when dealing with this issue is that voltage is only going to get you so far, many times you need to reduce voltage and tweak other values such as Rtt's and drive strength values, but ofcourse this also changes depending on the frequency/timings you are aiming for.

Example 4133/2067 using flat 16s will error out using 1.52v for vDIMM but works fine using 1.47v !
Everything is possible if you shove enough Volts at it.

I've been running true 1T 3800c14 (RD 14 tRP 13) since Zen 2 era, when I first got my bdie SR kit (3600c16 Dark Pros so nothing amazing).
Eventhough I agree RD is sometimes the stability killer due to IMC's ****ting themselves, doing flat 14's isn't hard.

I've helped so many people tune their ram and have never encountered an issue with running flat 14 primaries...

I've done this on Unify X, Bazooka, B450 board, Dark Hero, so many different boards...
 

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Everything is possible if you shove enough Volts at it.

I've been running true 1T 3800c14 (RD 14 tRP 13) since Zen 2 era, when I first got my bdie SR kit (3600c16 Dark Pros so nothing amazing).
Eventhough I agree RD is sometimes the stability killer due to IMC's ****ting themselves, doing flat 14's isn't hard.

I've helped so many people tune their ram and have never encountered an issue with running flat 14 primaries...

I've done this on Unify X, Bazooka, B450 board, Dark Hero, so many different boards...
Hey! It would be great tour advise. I learnt that 1T GDM disabled it doesn’t work with dual rank. And also, 3800-14 flat with dual rank it’s a little bit harder.. a least in 2x16GB. I will share you my results and advances so you can give some advise to try. I ended up following @Veii best timings for 3800 flat using the exploit. I started lowering TRDS fro 16 to 15.. and some errors appear, but with 14 TM5 gave a. Lot of 6 en the first test so I had to rebuild my RTTs and ProcOCT, and see voltages values. In a couple of hours when I’m staying at home I’ll share you my work. I know is hard but I want to thing with it could be achieve
These are the @Veii timings for 3800 flat

My doubts here are what are the VDIMM he’s running because of RTTPARK 6 that maybe he is running above 1.62V. Besides the VSOC value seems to be high. And then the exploit of tRAS +1 and TFAW same as tRRDL. I don’t remember if he’s RAM is single rank. Maybe I just have to tweak more being mines DR
Thanks!


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Yes, the same things happens to me but with Anta777. I don’t know why. I installed a new copy.. because it’s the last one but sometimes it’s stop.



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I've contacted the guys at overclockers ru at the place where anta777 hangs out and other guys discussing this TestMem5. I'll let you know if they know of a fix.
 
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