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I did an experiment on my own 5800X and Unify X running SR 2*8GB bdie.

1900 works out of the box no adjusments to VSOC, VDDGs, etc.

1900 scales positively with reduction to VDDG IOD, namely, below 1V it keeps scaling positively until it stops booting at <0.9V. Higher than 1V makes it go from 1 WHEA per 5 min to 1 WHEA per second.

Increasing VSOC past 1.1V also brings no noticeable improvement and so doesn't reducing procODT as far as I could measure.

This scaling is observed until 2000 fCLK. After 2000 fCLK, you start to see strange behaviours from the throttling mentioned here I guess, cpu boost gets lower and latency higher.
I am able to boot at until 2200 synced. Haven't tried higher with newer AGESA/BIOs.

MSI doesn't expose PLL voltage although I think it's 1P8 voltage but not sure. Also, I've used LN2 mode in Zen 2 era to boot and stabilize 1 tick higher fCLK however on Zen 3 on this board, enabling LN2 actually fails post/boot.
 

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Likely fine in a 5900X but not so easy on a 5600X
120(122A) EDC cap is just too low for 2100 SOC requirements
Yeah, exactly what I experienced when tested mine @2100. All scales well up to (and icluding) 2066 (with a few caveats). At 2100 AIDA latency is fine, but something' starts to eat up power too much

98-ish vs 95-ish seconds (2100 vs 2033) with easy preset in membench, and throttling a lot according to GB5 multicore.
 

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B550 AORUS MASTER, 3700X, 32GB g.Skill DDR4-3200 (@3800MT/s; 14-14-14-28), XFX RX 5500 XT
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I made another attempt to pull 14s flat and here are my results... They're... Not flat 😂😂😂😂😂

I'm so confused on how to move forward I just tried silly stuff... Dunno if setup timings work (or tCKE) for Matisse or if my profile is just me setting future me up for when I finally get around to obtaining a 5800X

2488916

This just spewed errors #0, #12, and #6 within a minute of starting TM5
2488917

2488918

2488999

2489000

2489009

Edit: I just now purchased another F4-3200C14-8GTZR (8GB, SR) kit so I'll be adding two more DIMMs on the 5th of May... If I hate it I'll prolly just pull em and use em in another system until I'm upgraded to Zen 3 and I've completed assembly of the watercooling loop...

@Veii
If you're not too busy traveling and making music would you mind taking a look at the screenshots I've got posted above and tell me what I should do to improve the efficacy of my efforts here? Please and thank you always
 

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A0's usually "should" fail beyond 4133 (4000 in reality) which is why many board partners beyond 4000 swap PCBs or make a custom design
* A1 should be similar 4133+ is A2 zone
Except for when you adjust RTTs
Please remember to adapt RTTs beyond 1.51v/1.52v, for the health of thekits
I'll take a shot of the PCB when I put on the heatsinks for the waterblock.
Probably going to be rude with this kit :p
But I'll keep in mind your advice about the RTT.

What do you think about running ClkDrvStr at 120 Ohm?

I managed to run my DR kit at 1T without setup timings.
Only using this crazy high ClkDrvStr; but the RTT and ProcODT is very mild.

It's just a tad better in latency than with setup timings.
But maybe for CPUs with a single CCD that can go very low in latency it makes a big difference.

2488940
2488941
 
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I did an experiment on my own 5800X and Unify X running SR 2*8GB bdie.

1900 works out of the box no adjusments to VSOC, VDDGs, etc.

1900 scales positively with reduction to VDDG IOD, namely, below 1V it keeps scaling positively until it stops booting at <0.9V. Higher than 1V makes it go from 1 WHEA per 5 min to 1 WHEA per second.

Increasing VSOC past 1.1V also brings no noticeable improvement and so doesn't reducing procODT as far as I could measure.

This scaling is observed until 2000 fCLK. After 2000 fCLK, you start to see strange behaviours from the throttling mentioned here I guess, cpu boost gets lower and latency higher.
I am able to boot at until 2200 synced. Haven't tried higher with newer AGESA/BIOs.

MSI doesn't expose PLL voltage although I think it's 1P8 voltage but not sure. Also, I've used LN2 mode in Zen 2 era to boot and stabilize 1 tick higher fCLK however on Zen 3 on this board, enabling LN2 actually fails post/boot.
What do you mean by "scaling" when lowering iod? You mean like latency benefits or somthing else?
 

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You should increase RRD_ to 5-7-20
This have completely ruined performance, +5 seconds in membench 1.7.3 Rtt_nom off just doesn't boot, I have 4x8 sticks and I thought 7/3/1 is default for that? So I'm left with lowering vdimm and proc, I guess, but no luck so far.
 

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2489013


2489011


Code:
SiSoftware Sandra

Benchmark Results
Aggregate Inter-Thread Bandwidth : 176GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Average Inter-Thread Latency : 39.9ns (9.5ns - 61.4ns)
Inter-Thread (same Core) Latency : 9.8ns
Inter-Core (same Module) Latency : 21.0ns
Inter-Module (same Package) Latency : 58.4ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 5.5GB/s
No. Threads : 32
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 105.00W
Aggregate Inter-Thread Bandwidth : 1716.17MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 3.80ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 707.05kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 36.22MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 0.08ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
U0-M0C0T0 <> U2-M0C1T0 Data Latency : 22.2ns
U0-M0C0T0 <> U4-M0C2T0 Data Latency : 19.6ns
U0-M0C0T0 <> U6-M0C3T0 Data Latency : 20.1ns
U0-M0C0T0 <> U8-M0C4T0 Data Latency : 19.9ns
U0-M0C0T0 <> U10-M0C5T0 Data Latency : 20.4ns
U0-M0C0T0 <> U12-M0C6T0 Data Latency : 20.8ns
U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.5ns
U0-M0C0T0 <> U16-M1C0T0 Data Latency : 56.9ns
U0-M0C0T0 <> U18-M1C1T0 Data Latency : 56.6ns
U0-M0C0T0 <> U20-M1C2T0 Data Latency : 56.9ns
U0-M0C0T0 <> U22-M1C3T0 Data Latency : 57.3ns
U0-M0C0T0 <> U24-M1C4T0 Data Latency : 58.0ns
U0-M0C0T0 <> U26-M1C5T0 Data Latency : 57.5ns
U0-M0C0T0 <> U28-M1C6T0 Data Latency : 58.1ns
U0-M0C0T0 <> U30-M1C7T0 Data Latency : 58.1ns
U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.6ns
U0-M0C0T0 <> U3-M0C1T1 Data Latency : 19.5ns
U0-M0C0T0 <> U5-M0C2T1 Data Latency : 19.5ns
U0-M0C0T0 <> U7-M0C3T1 Data Latency : 20.0ns
U0-M0C0T0 <> U9-M0C4T1 Data Latency : 19.8ns
U0-M0C0T0 <> U11-M0C5T1 Data Latency : 20.5ns
U0-M0C0T0 <> U13-M0C6T1 Data Latency : 20.8ns
U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.5ns
U0-M0C0T0 <> U17-M1C0T1 Data Latency : 56.9ns
U0-M0C0T0 <> U19-M1C1T1 Data Latency : 56.4ns
U0-M0C0T0 <> U21-M1C2T1 Data Latency : 56.9ns
U0-M0C0T0 <> U23-M1C3T1 Data Latency : 57.3ns
U0-M0C0T0 <> U25-M1C4T1 Data Latency : 58.0ns
U0-M0C0T0 <> U27-M1C5T1 Data Latency : 57.5ns
U0-M0C0T0 <> U29-M1C6T1 Data Latency : 58.1ns
U0-M0C0T0 <> U31-M1C7T1 Data Latency : 58.1ns
U2-M0C1T0 <> U4-M0C2T0 Data Latency : 19.2ns
U2-M0C1T0 <> U6-M0C3T0 Data Latency : 20.8ns
U2-M0C1T0 <> U8-M0C4T0 Data Latency : 19.7ns
U2-M0C1T0 <> U10-M0C5T0 Data Latency : 21.4ns
U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.5ns
U2-M0C1T0 <> U14-M0C7T0 Data Latency : 21.0ns
U2-M0C1T0 <> U16-M1C0T0 Data Latency : 56.8ns
U2-M0C1T0 <> U18-M1C1T0 Data Latency : 57.0ns
U2-M0C1T0 <> U20-M1C2T0 Data Latency : 57.1ns
U2-M0C1T0 <> U22-M1C3T0 Data Latency : 60.9ns
U2-M0C1T0 <> U24-M1C4T0 Data Latency : 61.0ns
U2-M0C1T0 <> U26-M1C5T0 Data Latency : 60.8ns
U2-M0C1T0 <> U28-M1C6T0 Data Latency : 60.5ns
U2-M0C1T0 <> U30-M1C7T0 Data Latency : 60.3ns
U2-M0C1T0 <> U1-M0C0T1 Data Latency : 22.2ns
U2-M0C1T0 <> U3-M0C1T1 Data Latency : 10.0ns
U2-M0C1T0 <> U5-M0C2T1 Data Latency : 21.9ns
U2-M0C1T0 <> U7-M0C3T1 Data Latency : 23.0ns
U2-M0C1T0 <> U9-M0C4T1 Data Latency : 21.1ns
U2-M0C1T0 <> U11-M0C5T1 Data Latency : 22.3ns
U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.6ns
U2-M0C1T0 <> U15-M0C7T1 Data Latency : 21.8ns
U2-M0C1T0 <> U17-M1C0T1 Data Latency : 61.4ns
U2-M0C1T0 <> U19-M1C1T1 Data Latency : 61.1ns
U2-M0C1T0 <> U21-M1C2T1 Data Latency : 61.2ns
U2-M0C1T0 <> U23-M1C3T1 Data Latency : 60.9ns
U2-M0C1T0 <> U25-M1C4T1 Data Latency : 61.1ns
U2-M0C1T0 <> U27-M1C5T1 Data Latency : 60.8ns
U2-M0C1T0 <> U29-M1C6T1 Data Latency : 60.5ns
U2-M0C1T0 <> U31-M1C7T1 Data Latency : 60.3ns
U4-M0C2T0 <> U6-M0C3T0 Data Latency : 21.3ns
U4-M0C2T0 <> U8-M0C4T0 Data Latency : 20.6ns
U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.5ns
U4-M0C2T0 <> U12-M0C6T0 Data Latency : 19.9ns
U4-M0C2T0 <> U14-M0C7T0 Data Latency : 19.8ns
U4-M0C2T0 <> U16-M1C0T0 Data Latency : 60.3ns
U4-M0C2T0 <> U18-M1C1T0 Data Latency : 60.7ns
U4-M0C2T0 <> U20-M1C2T0 Data Latency : 60.2ns
U4-M0C2T0 <> U22-M1C3T0 Data Latency : 60.6ns
U4-M0C2T0 <> U24-M1C4T0 Data Latency : 59.7ns
U4-M0C2T0 <> U26-M1C5T0 Data Latency : 60.4ns
U4-M0C2T0 <> U28-M1C6T0 Data Latency : 59.6ns
U4-M0C2T0 <> U30-M1C7T0 Data Latency : 60.0ns
U4-M0C2T0 <> U1-M0C0T1 Data Latency : 22.0ns
U4-M0C2T0 <> U3-M0C1T1 Data Latency : 22.2ns
U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.8ns
U4-M0C2T0 <> U7-M0C3T1 Data Latency : 21.2ns
U4-M0C2T0 <> U9-M0C4T1 Data Latency : 20.6ns
U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.5ns
U4-M0C2T0 <> U13-M0C6T1 Data Latency : 19.9ns
U4-M0C2T0 <> U15-M0C7T1 Data Latency : 19.8ns
U4-M0C2T0 <> U17-M1C0T1 Data Latency : 60.4ns
U4-M0C2T0 <> U19-M1C1T1 Data Latency : 60.8ns
U4-M0C2T0 <> U21-M1C2T1 Data Latency : 60.1ns
U4-M0C2T0 <> U23-M1C3T1 Data Latency : 60.5ns
U4-M0C2T0 <> U25-M1C4T1 Data Latency : 59.7ns
U4-M0C2T0 <> U27-M1C5T1 Data Latency : 60.4ns
U4-M0C2T0 <> U29-M1C6T1 Data Latency : 59.6ns
U4-M0C2T0 <> U31-M1C7T1 Data Latency : 60.1ns
U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.6ns
U6-M0C3T0 <> U10-M0C5T0 Data Latency : 21.7ns
U6-M0C3T0 <> U12-M0C6T0 Data Latency : 19.9ns
U6-M0C3T0 <> U14-M0C7T0 Data Latency : 21.1ns
U6-M0C3T0 <> U16-M1C0T0 Data Latency : 61.1ns
U6-M0C3T0 <> U18-M1C1T0 Data Latency : 60.9ns
U6-M0C3T0 <> U20-M1C2T0 Data Latency : 60.9ns
U6-M0C3T0 <> U22-M1C3T0 Data Latency : 60.4ns
U6-M0C3T0 <> U24-M1C4T0 Data Latency : 60.4ns
U6-M0C3T0 <> U26-M1C5T0 Data Latency : 60.5ns
U6-M0C3T0 <> U28-M1C6T0 Data Latency : 60.2ns
U6-M0C3T0 <> U30-M1C7T0 Data Latency : 60.1ns
U6-M0C3T0 <> U1-M0C0T1 Data Latency : 21.9ns
U6-M0C3T0 <> U3-M0C1T1 Data Latency : 23.2ns
U6-M0C3T0 <> U5-M0C2T1 Data Latency : 21.4ns
U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.9ns
U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.7ns
U6-M0C3T0 <> U11-M0C5T1 Data Latency : 21.7ns
U6-M0C3T0 <> U13-M0C6T1 Data Latency : 19.9ns
U6-M0C3T0 <> U15-M0C7T1 Data Latency : 21.2ns
U6-M0C3T0 <> U17-M1C0T1 Data Latency : 57.0ns
U6-M0C3T0 <> U19-M1C1T1 Data Latency : 57.0ns
U6-M0C3T0 <> U21-M1C2T1 Data Latency : 57.3ns
U6-M0C3T0 <> U23-M1C3T1 Data Latency : 57.5ns
U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.0ns
U6-M0C3T0 <> U27-M1C5T1 Data Latency : 58.2ns
U6-M0C3T0 <> U29-M1C6T1 Data Latency : 58.6ns
U6-M0C3T0 <> U31-M1C7T1 Data Latency : 58.3ns
U8-M0C4T0 <> U10-M0C5T0 Data Latency : 21.0ns
U8-M0C4T0 <> U12-M0C6T0 Data Latency : 22.8ns
U8-M0C4T0 <> U14-M0C7T0 Data Latency : 21.7ns
U8-M0C4T0 <> U16-M1C0T0 Data Latency : 57.7ns
U8-M0C4T0 <> U18-M1C1T0 Data Latency : 57.2ns
U8-M0C4T0 <> U20-M1C2T0 Data Latency : 58.0ns
U8-M0C4T0 <> U22-M1C3T0 Data Latency : 57.8ns
U8-M0C4T0 <> U24-M1C4T0 Data Latency : 58.6ns
U8-M0C4T0 <> U26-M1C5T0 Data Latency : 58.4ns
U8-M0C4T0 <> U28-M1C6T0 Data Latency : 58.9ns
U8-M0C4T0 <> U30-M1C7T0 Data Latency : 58.8ns
U8-M0C4T0 <> U1-M0C0T1 Data Latency : 20.7ns
U8-M0C4T0 <> U3-M0C1T1 Data Latency : 19.9ns
U8-M0C4T0 <> U5-M0C2T1 Data Latency : 21.8ns
U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.5ns
U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.5ns
U8-M0C4T0 <> U11-M0C5T1 Data Latency : 21.0ns
U8-M0C4T0 <> U13-M0C6T1 Data Latency : 22.9ns
U8-M0C4T0 <> U15-M0C7T1 Data Latency : 21.7ns
U8-M0C4T0 <> U17-M1C0T1 Data Latency : 57.7ns
U8-M0C4T0 <> U19-M1C1T1 Data Latency : 57.2ns
U8-M0C4T0 <> U21-M1C2T1 Data Latency : 57.9ns
U8-M0C4T0 <> U23-M1C3T1 Data Latency : 57.8ns
U8-M0C4T0 <> U25-M1C4T1 Data Latency : 58.6ns
U8-M0C4T0 <> U27-M1C5T1 Data Latency : 58.4ns
U8-M0C4T0 <> U29-M1C6T1 Data Latency : 58.8ns
U8-M0C4T0 <> U31-M1C7T1 Data Latency : 58.7ns
U10-M0C5T0 <> U12-M0C6T0 Data Latency : 21.7ns
U10-M0C5T0 <> U14-M0C7T0 Data Latency : 21.7ns
U10-M0C5T0 <> U16-M1C0T0 Data Latency : 57.4ns
U10-M0C5T0 <> U18-M1C1T0 Data Latency : 57.1ns
U10-M0C5T0 <> U20-M1C2T0 Data Latency : 57.6ns
U10-M0C5T0 <> U22-M1C3T0 Data Latency : 57.8ns
U10-M0C5T0 <> U24-M1C4T0 Data Latency : 58.4ns
U10-M0C5T0 <> U26-M1C5T0 Data Latency : 58.3ns
U10-M0C5T0 <> U28-M1C6T0 Data Latency : 58.9ns
U10-M0C5T0 <> U30-M1C7T0 Data Latency : 58.2ns
U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.3ns
U10-M0C5T0 <> U3-M0C1T1 Data Latency : 20.9ns
U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.5ns
U10-M0C5T0 <> U7-M0C3T1 Data Latency : 21.5ns
U10-M0C5T0 <> U9-M0C4T1 Data Latency : 20.9ns
U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.8ns
U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.7ns
U10-M0C5T0 <> U15-M0C7T1 Data Latency : 21.7ns
U10-M0C5T0 <> U17-M1C0T1 Data Latency : 57.4ns
U10-M0C5T0 <> U19-M1C1T1 Data Latency : 57.2ns
U10-M0C5T0 <> U21-M1C2T1 Data Latency : 57.6ns
U10-M0C5T0 <> U23-M1C3T1 Data Latency : 57.6ns
U10-M0C5T0 <> U25-M1C4T1 Data Latency : 58.4ns
U10-M0C5T0 <> U27-M1C5T1 Data Latency : 58.3ns
U10-M0C5T0 <> U29-M1C6T1 Data Latency : 58.8ns
U10-M0C5T0 <> U31-M1C7T1 Data Latency : 58.3ns
U12-M0C6T0 <> U14-M0C7T0 Data Latency : 22.4ns
U12-M0C6T0 <> U16-M1C0T0 Data Latency : 58.4ns
U12-M0C6T0 <> U18-M1C1T0 Data Latency : 57.8ns
U12-M0C6T0 <> U20-M1C2T0 Data Latency : 58.5ns
U12-M0C6T0 <> U22-M1C3T0 Data Latency : 58.7ns
U12-M0C6T0 <> U24-M1C4T0 Data Latency : 59.1ns
U12-M0C6T0 <> U26-M1C5T0 Data Latency : 59.0ns
U12-M0C6T0 <> U28-M1C6T0 Data Latency : 59.7ns
U12-M0C6T0 <> U30-M1C7T0 Data Latency : 59.8ns
U12-M0C6T0 <> U1-M0C0T1 Data Latency : 21.6ns
U12-M0C6T0 <> U3-M0C1T1 Data Latency : 20.7ns
U12-M0C6T0 <> U5-M0C2T1 Data Latency : 22.4ns
U12-M0C6T0 <> U7-M0C3T1 Data Latency : 21.3ns
U12-M0C6T0 <> U9-M0C4T1 Data Latency : 22.9ns
U12-M0C6T0 <> U11-M0C5T1 Data Latency : 21.8ns
U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.9ns
U12-M0C6T0 <> U15-M0C7T1 Data Latency : 22.5ns
U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.4ns
U12-M0C6T0 <> U19-M1C1T1 Data Latency : 58.0ns
U12-M0C6T0 <> U21-M1C2T1 Data Latency : 58.5ns
U12-M0C6T0 <> U23-M1C3T1 Data Latency : 58.6ns
U12-M0C6T0 <> U25-M1C4T1 Data Latency : 59.1ns
U12-M0C6T0 <> U27-M1C5T1 Data Latency : 59.0ns
U12-M0C6T0 <> U29-M1C6T1 Data Latency : 59.7ns
U12-M0C6T0 <> U31-M1C7T1 Data Latency : 59.7ns
U14-M0C7T0 <> U16-M1C0T0 Data Latency : 58.0ns
U14-M0C7T0 <> U18-M1C1T0 Data Latency : 57.6ns
U14-M0C7T0 <> U20-M1C2T0 Data Latency : 58.1ns
U14-M0C7T0 <> U22-M1C3T0 Data Latency : 58.1ns
U14-M0C7T0 <> U24-M1C4T0 Data Latency : 59.1ns
U14-M0C7T0 <> U26-M1C5T0 Data Latency : 58.5ns
U14-M0C7T0 <> U28-M1C6T0 Data Latency : 59.6ns
U14-M0C7T0 <> U30-M1C7T0 Data Latency : 59.1ns
U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.6ns
U14-M0C7T0 <> U3-M0C1T1 Data Latency : 20.8ns
U14-M0C7T0 <> U5-M0C2T1 Data Latency : 21.3ns
U14-M0C7T0 <> U7-M0C3T1 Data Latency : 21.4ns
U14-M0C7T0 <> U9-M0C4T1 Data Latency : 21.7ns
U14-M0C7T0 <> U11-M0C5T1 Data Latency : 21.9ns
U14-M0C7T0 <> U13-M0C6T1 Data Latency : 22.3ns
U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.8ns
U14-M0C7T0 <> U17-M1C0T1 Data Latency : 57.9ns
U14-M0C7T0 <> U19-M1C1T1 Data Latency : 57.5ns
U14-M0C7T0 <> U21-M1C2T1 Data Latency : 58.1ns
U14-M0C7T0 <> U23-M1C3T1 Data Latency : 58.2ns
U14-M0C7T0 <> U25-M1C4T1 Data Latency : 59.0ns
U14-M0C7T0 <> U27-M1C5T1 Data Latency : 58.5ns
U14-M0C7T0 <> U29-M1C6T1 Data Latency : 59.5ns
U14-M0C7T0 <> U31-M1C7T1 Data Latency : 59.1ns
U16-M1C0T0 <> U18-M1C1T0 Data Latency : 19.2ns
U16-M1C0T0 <> U20-M1C2T0 Data Latency : 20.0ns
U16-M1C0T0 <> U22-M1C3T0 Data Latency : 19.7ns
U16-M1C0T0 <> U24-M1C4T0 Data Latency : 20.9ns
U16-M1C0T0 <> U26-M1C5T0 Data Latency : 20.3ns
U16-M1C0T0 <> U28-M1C6T0 Data Latency : 21.5ns
U16-M1C0T0 <> U30-M1C7T0 Data Latency : 20.5ns
U16-M1C0T0 <> U1-M0C0T1 Data Latency : 57.1ns
U16-M1C0T0 <> U3-M0C1T1 Data Latency : 56.9ns
U16-M1C0T0 <> U5-M0C2T1 Data Latency : 57.0ns
U16-M1C0T0 <> U7-M0C3T1 Data Latency : 57.4ns
U16-M1C0T0 <> U9-M0C4T1 Data Latency : 57.6ns
U16-M1C0T0 <> U11-M0C5T1 Data Latency : 57.6ns
U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.2ns
U16-M1C0T0 <> U15-M0C7T1 Data Latency : 58.0ns
U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.8ns
U16-M1C0T0 <> U19-M1C1T1 Data Latency : 19.2ns
U16-M1C0T0 <> U21-M1C2T1 Data Latency : 20.1ns
U16-M1C0T0 <> U23-M1C3T1 Data Latency : 19.7ns
U16-M1C0T0 <> U25-M1C4T1 Data Latency : 20.9ns
U16-M1C0T0 <> U27-M1C5T1 Data Latency : 20.3ns
U16-M1C0T0 <> U29-M1C6T1 Data Latency : 21.5ns
U16-M1C0T0 <> U31-M1C7T1 Data Latency : 20.5ns
U18-M1C1T0 <> U20-M1C2T0 Data Latency : 18.9ns
U18-M1C1T0 <> U22-M1C3T0 Data Latency : 19.9ns
U18-M1C1T0 <> U24-M1C4T0 Data Latency : 19.7ns
U18-M1C1T0 <> U26-M1C5T0 Data Latency : 20.5ns
U18-M1C1T0 <> U28-M1C6T0 Data Latency : 20.5ns
U18-M1C1T0 <> U30-M1C7T0 Data Latency : 20.4ns
U18-M1C1T0 <> U1-M0C0T1 Data Latency : 56.1ns
U18-M1C1T0 <> U3-M0C1T1 Data Latency : 56.8ns
U18-M1C1T0 <> U5-M0C2T1 Data Latency : 56.9ns
U18-M1C1T0 <> U7-M0C3T1 Data Latency : 57.1ns
U18-M1C1T0 <> U9-M0C4T1 Data Latency : 57.0ns
U18-M1C1T0 <> U11-M0C5T1 Data Latency : 57.1ns
U18-M1C1T0 <> U13-M0C6T1 Data Latency : 57.7ns
U18-M1C1T0 <> U15-M0C7T1 Data Latency : 57.3ns
U18-M1C1T0 <> U17-M1C0T1 Data Latency : 19.2ns
U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.8ns
U18-M1C1T0 <> U21-M1C2T1 Data Latency : 18.9ns
U18-M1C1T0 <> U23-M1C3T1 Data Latency : 19.9ns
U18-M1C1T0 <> U25-M1C4T1 Data Latency : 19.7ns
U18-M1C1T0 <> U27-M1C5T1 Data Latency : 20.5ns
U18-M1C1T0 <> U29-M1C6T1 Data Latency : 20.4ns
U18-M1C1T0 <> U31-M1C7T1 Data Latency : 20.4ns
U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.6ns
U20-M1C2T0 <> U24-M1C4T0 Data Latency : 21.6ns
U20-M1C2T0 <> U26-M1C5T0 Data Latency : 20.4ns
U20-M1C2T0 <> U28-M1C6T0 Data Latency : 22.0ns
U20-M1C2T0 <> U30-M1C7T0 Data Latency : 21.1ns
U20-M1C2T0 <> U1-M0C0T1 Data Latency : 57.1ns
U20-M1C2T0 <> U3-M0C1T1 Data Latency : 57.7ns
U20-M1C2T0 <> U5-M0C2T1 Data Latency : 57.4ns
U20-M1C2T0 <> U7-M0C3T1 Data Latency : 57.6ns
U20-M1C2T0 <> U9-M0C4T1 Data Latency : 57.7ns
U20-M1C2T0 <> U11-M0C5T1 Data Latency : 58.2ns
U20-M1C2T0 <> U13-M0C6T1 Data Latency : 58.3ns
U20-M1C2T0 <> U15-M0C7T1 Data Latency : 58.2ns
U20-M1C2T0 <> U17-M1C0T1 Data Latency : 20.1ns
U20-M1C2T0 <> U19-M1C1T1 Data Latency : 19.0ns
U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.8ns
U20-M1C2T0 <> U23-M1C3T1 Data Latency : 19.5ns
U20-M1C2T0 <> U25-M1C4T1 Data Latency : 21.6ns
U20-M1C2T0 <> U27-M1C5T1 Data Latency : 20.4ns
U20-M1C2T0 <> U29-M1C6T1 Data Latency : 22.0ns
U20-M1C2T0 <> U31-M1C7T1 Data Latency : 21.1ns
U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.4ns
U22-M1C3T0 <> U26-M1C5T0 Data Latency : 21.3ns
U22-M1C3T0 <> U28-M1C6T0 Data Latency : 21.0ns
U22-M1C3T0 <> U30-M1C7T0 Data Latency : 20.9ns
U22-M1C3T0 <> U1-M0C0T1 Data Latency : 57.0ns
U22-M1C3T0 <> U3-M0C1T1 Data Latency : 57.7ns
U22-M1C3T0 <> U5-M0C2T1 Data Latency : 57.4ns
U22-M1C3T0 <> U7-M0C3T1 Data Latency : 57.7ns
U22-M1C3T0 <> U9-M0C4T1 Data Latency : 57.6ns
U22-M1C3T0 <> U11-M0C5T1 Data Latency : 57.9ns
U22-M1C3T0 <> U13-M0C6T1 Data Latency : 58.3ns
U22-M1C3T0 <> U15-M0C7T1 Data Latency : 58.1ns
U22-M1C3T0 <> U17-M1C0T1 Data Latency : 19.6ns
U22-M1C3T0 <> U19-M1C1T1 Data Latency : 20.0ns
U22-M1C3T0 <> U21-M1C2T1 Data Latency : 19.4ns
U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.8ns
U22-M1C3T0 <> U25-M1C4T1 Data Latency : 20.4ns
U22-M1C3T0 <> U27-M1C5T1 Data Latency : 21.3ns
U22-M1C3T0 <> U29-M1C6T1 Data Latency : 21.0ns
U22-M1C3T0 <> U31-M1C7T1 Data Latency : 20.9ns
U24-M1C4T0 <> U26-M1C5T0 Data Latency : 21.2ns
U24-M1C4T0 <> U28-M1C6T0 Data Latency : 22.9ns
U24-M1C4T0 <> U30-M1C7T0 Data Latency : 21.9ns
U24-M1C4T0 <> U1-M0C0T1 Data Latency : 57.9ns
U24-M1C4T0 <> U3-M0C1T1 Data Latency : 58.3ns
U24-M1C4T0 <> U5-M0C2T1 Data Latency : 58.1ns
U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.3ns
U24-M1C4T0 <> U9-M0C4T1 Data Latency : 58.7ns
U24-M1C4T0 <> U11-M0C5T1 Data Latency : 58.9ns
U24-M1C4T0 <> U13-M0C6T1 Data Latency : 59.3ns
U24-M1C4T0 <> U15-M0C7T1 Data Latency : 59.1ns
U24-M1C4T0 <> U17-M1C0T1 Data Latency : 21.1ns
U24-M1C4T0 <> U19-M1C1T1 Data Latency : 19.8ns
U24-M1C4T0 <> U21-M1C2T1 Data Latency : 21.7ns
U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.5ns
U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.9ns
U24-M1C4T0 <> U27-M1C5T1 Data Latency : 21.3ns
U24-M1C4T0 <> U29-M1C6T1 Data Latency : 22.9ns
U24-M1C4T0 <> U31-M1C7T1 Data Latency : 21.9ns
U26-M1C5T0 <> U28-M1C6T0 Data Latency : 21.6ns
U26-M1C5T0 <> U30-M1C7T0 Data Latency : 21.7ns
U26-M1C5T0 <> U1-M0C0T1 Data Latency : 57.4ns
U26-M1C5T0 <> U3-M0C1T1 Data Latency : 58.2ns
U26-M1C5T0 <> U5-M0C2T1 Data Latency : 57.9ns
U26-M1C5T0 <> U7-M0C3T1 Data Latency : 58.2ns
U26-M1C5T0 <> U9-M0C4T1 Data Latency : 58.2ns
U26-M1C5T0 <> U11-M0C5T1 Data Latency : 58.3ns
U26-M1C5T0 <> U13-M0C6T1 Data Latency : 58.9ns
U26-M1C5T0 <> U15-M0C7T1 Data Latency : 58.7ns
U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.3ns
U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.6ns
U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.2ns
U26-M1C5T0 <> U23-M1C3T1 Data Latency : 21.3ns
U26-M1C5T0 <> U25-M1C4T1 Data Latency : 21.1ns
U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.8ns
U26-M1C5T0 <> U29-M1C6T1 Data Latency : 21.6ns
U26-M1C5T0 <> U31-M1C7T1 Data Latency : 21.7ns
U28-M1C6T0 <> U30-M1C7T0 Data Latency : 22.3ns
U28-M1C6T0 <> U1-M0C0T1 Data Latency : 58.4ns
U28-M1C6T0 <> U3-M0C1T1 Data Latency : 58.7ns
U28-M1C6T0 <> U5-M0C2T1 Data Latency : 58.8ns
U28-M1C6T0 <> U7-M0C3T1 Data Latency : 59.1ns
U28-M1C6T0 <> U9-M0C4T1 Data Latency : 58.9ns
U28-M1C6T0 <> U11-M0C5T1 Data Latency : 59.2ns
U28-M1C6T0 <> U13-M0C6T1 Data Latency : 59.6ns
U28-M1C6T0 <> U15-M0C7T1 Data Latency : 59.5ns
U28-M1C6T0 <> U17-M1C0T1 Data Latency : 21.6ns
U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.4ns
U28-M1C6T0 <> U21-M1C2T1 Data Latency : 22.2ns
U28-M1C6T0 <> U23-M1C3T1 Data Latency : 21.1ns
U28-M1C6T0 <> U25-M1C4T1 Data Latency : 23.0ns
U28-M1C6T0 <> U27-M1C5T1 Data Latency : 21.7ns
U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.8ns
U28-M1C6T0 <> U31-M1C7T1 Data Latency : 22.3ns
U30-M1C7T0 <> U1-M0C0T1 Data Latency : 58.0ns
U30-M1C7T0 <> U3-M0C1T1 Data Latency : 58.4ns
U30-M1C7T0 <> U5-M0C2T1 Data Latency : 58.4ns
U30-M1C7T0 <> U7-M0C3T1 Data Latency : 58.8ns
U30-M1C7T0 <> U9-M0C4T1 Data Latency : 58.7ns
U30-M1C7T0 <> U11-M0C5T1 Data Latency : 58.6ns
U30-M1C7T0 <> U13-M0C6T1 Data Latency : 59.5ns
U30-M1C7T0 <> U15-M0C7T1 Data Latency : 59.2ns
U30-M1C7T0 <> U17-M1C0T1 Data Latency : 20.6ns
U30-M1C7T0 <> U19-M1C1T1 Data Latency : 20.6ns
U30-M1C7T0 <> U21-M1C2T1 Data Latency : 21.1ns
U30-M1C7T0 <> U23-M1C3T1 Data Latency : 21.2ns
U30-M1C7T0 <> U25-M1C4T1 Data Latency : 21.9ns
U30-M1C7T0 <> U27-M1C5T1 Data Latency : 22.0ns
U30-M1C7T0 <> U29-M1C6T1 Data Latency : 22.2ns
U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.8ns
U1-M0C0T1 <> U3-M0C1T1 Data Latency : 19.4ns
U1-M0C0T1 <> U5-M0C2T1 Data Latency : 20.2ns
U1-M0C0T1 <> U7-M0C3T1 Data Latency : 19.9ns
U1-M0C0T1 <> U9-M0C4T1 Data Latency : 20.6ns
U1-M0C0T1 <> U11-M0C5T1 Data Latency : 20.2ns
U1-M0C0T1 <> U13-M0C6T1 Data Latency : 21.5ns
U1-M0C0T1 <> U15-M0C7T1 Data Latency : 20.5ns
U1-M0C0T1 <> U17-M1C0T1 Data Latency : 56.9ns
U1-M0C0T1 <> U19-M1C1T1 Data Latency : 56.3ns
U1-M0C0T1 <> U21-M1C2T1 Data Latency : 57.0ns
U1-M0C0T1 <> U23-M1C3T1 Data Latency : 57.1ns
U1-M0C0T1 <> U25-M1C4T1 Data Latency : 57.9ns
U1-M0C0T1 <> U27-M1C5T1 Data Latency : 57.6ns
U1-M0C0T1 <> U29-M1C6T1 Data Latency : 58.3ns
U1-M0C0T1 <> U31-M1C7T1 Data Latency : 57.9ns
U3-M0C1T1 <> U5-M0C2T1 Data Latency : 19.4ns
U3-M0C1T1 <> U7-M0C3T1 Data Latency : 20.3ns
U3-M0C1T1 <> U9-M0C4T1 Data Latency : 19.9ns
U3-M0C1T1 <> U11-M0C5T1 Data Latency : 20.8ns
U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.8ns
U3-M0C1T1 <> U15-M0C7T1 Data Latency : 20.7ns
U3-M0C1T1 <> U17-M1C0T1 Data Latency : 57.0ns
U3-M0C1T1 <> U19-M1C1T1 Data Latency : 56.8ns
U3-M0C1T1 <> U21-M1C2T1 Data Latency : 57.2ns
U3-M0C1T1 <> U23-M1C3T1 Data Latency : 57.2ns
U3-M0C1T1 <> U25-M1C4T1 Data Latency : 57.8ns
U3-M0C1T1 <> U27-M1C5T1 Data Latency : 57.7ns
U3-M0C1T1 <> U29-M1C6T1 Data Latency : 58.7ns
U3-M0C1T1 <> U31-M1C7T1 Data Latency : 58.1ns
U5-M0C2T1 <> U7-M0C3T1 Data Latency : 19.8ns
U5-M0C2T1 <> U9-M0C4T1 Data Latency : 21.7ns
U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.6ns
U5-M0C2T1 <> U13-M0C6T1 Data Latency : 22.3ns
U5-M0C2T1 <> U15-M0C7T1 Data Latency : 21.3ns
U5-M0C2T1 <> U17-M1C0T1 Data Latency : 57.3ns
U5-M0C2T1 <> U19-M1C1T1 Data Latency : 57.2ns
U5-M0C2T1 <> U21-M1C2T1 Data Latency : 57.4ns
U5-M0C2T1 <> U23-M1C3T1 Data Latency : 57.7ns
U5-M0C2T1 <> U25-M1C4T1 Data Latency : 58.2ns
U5-M0C2T1 <> U27-M1C5T1 Data Latency : 58.3ns
U5-M0C2T1 <> U29-M1C6T1 Data Latency : 58.7ns
U5-M0C2T1 <> U31-M1C7T1 Data Latency : 58.6ns
U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.5ns
U7-M0C3T1 <> U11-M0C5T1 Data Latency : 21.6ns
U7-M0C3T1 <> U13-M0C6T1 Data Latency : 21.3ns
U7-M0C3T1 <> U15-M0C7T1 Data Latency : 21.2ns
U7-M0C3T1 <> U17-M1C0T1 Data Latency : 57.0ns
U7-M0C3T1 <> U19-M1C1T1 Data Latency : 57.1ns
U7-M0C3T1 <> U21-M1C2T1 Data Latency : 57.1ns
U7-M0C3T1 <> U23-M1C3T1 Data Latency : 57.5ns
U7-M0C3T1 <> U25-M1C4T1 Data Latency : 57.9ns
U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.1ns
U7-M0C3T1 <> U29-M1C6T1 Data Latency : 58.7ns
U7-M0C3T1 <> U31-M1C7T1 Data Latency : 58.2ns
U9-M0C4T1 <> U11-M0C5T1 Data Latency : 21.0ns
U9-M0C4T1 <> U13-M0C6T1 Data Latency : 22.9ns
U9-M0C4T1 <> U15-M0C7T1 Data Latency : 21.7ns
U9-M0C4T1 <> U17-M1C0T1 Data Latency : 57.7ns
U9-M0C4T1 <> U19-M1C1T1 Data Latency : 57.3ns
U9-M0C4T1 <> U21-M1C2T1 Data Latency : 58.0ns
U9-M0C4T1 <> U23-M1C3T1 Data Latency : 57.8ns
U9-M0C4T1 <> U25-M1C4T1 Data Latency : 58.6ns
U9-M0C4T1 <> U27-M1C5T1 Data Latency : 58.4ns
U9-M0C4T1 <> U29-M1C6T1 Data Latency : 58.9ns
U9-M0C4T1 <> U31-M1C7T1 Data Latency : 58.9ns
U11-M0C5T1 <> U13-M0C6T1 Data Latency : 21.7ns
U11-M0C5T1 <> U15-M0C7T1 Data Latency : 21.7ns
U11-M0C5T1 <> U17-M1C0T1 Data Latency : 57.4ns
U11-M0C5T1 <> U19-M1C1T1 Data Latency : 57.3ns
U11-M0C5T1 <> U21-M1C2T1 Data Latency : 57.6ns
U11-M0C5T1 <> U23-M1C3T1 Data Latency : 57.8ns
U11-M0C5T1 <> U25-M1C4T1 Data Latency : 58.5ns
U11-M0C5T1 <> U27-M1C5T1 Data Latency : 58.4ns
U11-M0C5T1 <> U29-M1C6T1 Data Latency : 58.9ns
U11-M0C5T1 <> U31-M1C7T1 Data Latency : 58.4ns
U13-M0C6T1 <> U15-M0C7T1 Data Latency : 22.9ns
U13-M0C6T1 <> U17-M1C0T1 Data Latency : 58.4ns
U13-M0C6T1 <> U19-M1C1T1 Data Latency : 57.9ns
U13-M0C6T1 <> U21-M1C2T1 Data Latency : 58.5ns
U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.6ns
U13-M0C6T1 <> U25-M1C4T1 Data Latency : 59.0ns
U13-M0C6T1 <> U27-M1C5T1 Data Latency : 59.0ns
U13-M0C6T1 <> U29-M1C6T1 Data Latency : 59.7ns
U13-M0C6T1 <> U31-M1C7T1 Data Latency : 59.8ns
U15-M0C7T1 <> U17-M1C0T1 Data Latency : 57.9ns
U15-M0C7T1 <> U19-M1C1T1 Data Latency : 57.6ns
U15-M0C7T1 <> U21-M1C2T1 Data Latency : 58.1ns
U15-M0C7T1 <> U23-M1C3T1 Data Latency : 58.2ns
U15-M0C7T1 <> U25-M1C4T1 Data Latency : 59.0ns
U15-M0C7T1 <> U27-M1C5T1 Data Latency : 58.6ns
U15-M0C7T1 <> U29-M1C6T1 Data Latency : 59.5ns
U15-M0C7T1 <> U31-M1C7T1 Data Latency : 59.2ns
U17-M1C0T1 <> U19-M1C1T1 Data Latency : 19.2ns
U17-M1C0T1 <> U21-M1C2T1 Data Latency : 20.0ns
U17-M1C0T1 <> U23-M1C3T1 Data Latency : 19.7ns
U17-M1C0T1 <> U25-M1C4T1 Data Latency : 20.9ns
U17-M1C0T1 <> U27-M1C5T1 Data Latency : 20.4ns
U17-M1C0T1 <> U29-M1C6T1 Data Latency : 21.5ns
U17-M1C0T1 <> U31-M1C7T1 Data Latency : 20.5ns
U19-M1C1T1 <> U21-M1C2T1 Data Latency : 18.9ns
U19-M1C1T1 <> U23-M1C3T1 Data Latency : 19.9ns
U19-M1C1T1 <> U25-M1C4T1 Data Latency : 19.7ns
U19-M1C1T1 <> U27-M1C5T1 Data Latency : 20.5ns
U19-M1C1T1 <> U29-M1C6T1 Data Latency : 20.4ns
U19-M1C1T1 <> U31-M1C7T1 Data Latency : 20.4ns
U21-M1C2T1 <> U23-M1C3T1 Data Latency : 19.6ns
U21-M1C2T1 <> U25-M1C4T1 Data Latency : 21.6ns
U21-M1C2T1 <> U27-M1C5T1 Data Latency : 20.4ns
U21-M1C2T1 <> U29-M1C6T1 Data Latency : 22.0ns
U21-M1C2T1 <> U31-M1C7T1 Data Latency : 21.1ns
U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.4ns
U23-M1C3T1 <> U27-M1C5T1 Data Latency : 21.3ns
U23-M1C3T1 <> U29-M1C6T1 Data Latency : 21.0ns
U23-M1C3T1 <> U31-M1C7T1 Data Latency : 21.0ns
U25-M1C4T1 <> U27-M1C5T1 Data Latency : 21.3ns
U25-M1C4T1 <> U29-M1C6T1 Data Latency : 23.0ns
U25-M1C4T1 <> U31-M1C7T1 Data Latency : 21.9ns
U27-M1C5T1 <> U29-M1C6T1 Data Latency : 21.6ns
U27-M1C5T1 <> U31-M1C7T1 Data Latency : 21.7ns
U29-M1C6T1 <> U31-M1C7T1 Data Latency : 22.2ns
1x 64bytes Blocks Bandwidth : 26GB/s
4x 64bytes Blocks Bandwidth : 28.76GB/s
4x 256bytes Blocks Bandwidth : 96.46GB/s
4x 1kB Blocks Bandwidth : 321.1GB/s
4x 4kB Blocks Bandwidth : 507GB/s
16x 4kB Blocks Bandwidth : 726.56GB/s
4x 64kB Blocks Bandwidth : 995.61GB/s
16x 64kB Blocks Bandwidth : 598.29GB/s
8x 256kB Blocks Bandwidth : 602.17GB/s
4x 1MB Blocks Bandwidth : 608.9GB/s
16x 1MB Blocks Bandwidth : 24.7GB/s
8x 4MB Blocks Bandwidth : 19.17GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 5GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
Microcode : A20F10-1009
Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
Platform Compliance : x64
No. Threads : 32
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5950X 16-Core Processor
URL : https://www.amd.com
Speed : 5GHz
Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 5GHz
Modules per Processor : 2 Unit(s)
Cores per Processor : 8 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : A20F10-1009
L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
Rated Power (TDP) : 105.00W

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.
 

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View attachment 2489013

View attachment 2489011

Code:
SiSoftware Sandra

Benchmark Results
Aggregate Inter-Thread Bandwidth : 176GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Average Inter-Thread Latency : 39.9ns (9.5ns - 61.4ns)
Inter-Thread (same Core) Latency : 9.8ns
Inter-Core (same Module) Latency : 21.0ns
Inter-Module (same Package) Latency : 58.4ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 5.5GB/s
No. Threads : 32
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 105.00W
Aggregate Inter-Thread Bandwidth : 1716.17MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 3.80ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 707.05kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 36.22MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 0.08ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
U0-M0C0T0 <> U2-M0C1T0 Data Latency : 22.2ns
U0-M0C0T0 <> U4-M0C2T0 Data Latency : 19.6ns
U0-M0C0T0 <> U6-M0C3T0 Data Latency : 20.1ns
U0-M0C0T0 <> U8-M0C4T0 Data Latency : 19.9ns
U0-M0C0T0 <> U10-M0C5T0 Data Latency : 20.4ns
U0-M0C0T0 <> U12-M0C6T0 Data Latency : 20.8ns
U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.5ns
U0-M0C0T0 <> U16-M1C0T0 Data Latency : 56.9ns
U0-M0C0T0 <> U18-M1C1T0 Data Latency : 56.6ns
U0-M0C0T0 <> U20-M1C2T0 Data Latency : 56.9ns
U0-M0C0T0 <> U22-M1C3T0 Data Latency : 57.3ns
U0-M0C0T0 <> U24-M1C4T0 Data Latency : 58.0ns
U0-M0C0T0 <> U26-M1C5T0 Data Latency : 57.5ns
U0-M0C0T0 <> U28-M1C6T0 Data Latency : 58.1ns
U0-M0C0T0 <> U30-M1C7T0 Data Latency : 58.1ns
U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.6ns
U0-M0C0T0 <> U3-M0C1T1 Data Latency : 19.5ns
U0-M0C0T0 <> U5-M0C2T1 Data Latency : 19.5ns
U0-M0C0T0 <> U7-M0C3T1 Data Latency : 20.0ns
U0-M0C0T0 <> U9-M0C4T1 Data Latency : 19.8ns
U0-M0C0T0 <> U11-M0C5T1 Data Latency : 20.5ns
U0-M0C0T0 <> U13-M0C6T1 Data Latency : 20.8ns
U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.5ns
U0-M0C0T0 <> U17-M1C0T1 Data Latency : 56.9ns
U0-M0C0T0 <> U19-M1C1T1 Data Latency : 56.4ns
U0-M0C0T0 <> U21-M1C2T1 Data Latency : 56.9ns
U0-M0C0T0 <> U23-M1C3T1 Data Latency : 57.3ns
U0-M0C0T0 <> U25-M1C4T1 Data Latency : 58.0ns
U0-M0C0T0 <> U27-M1C5T1 Data Latency : 57.5ns
U0-M0C0T0 <> U29-M1C6T1 Data Latency : 58.1ns
U0-M0C0T0 <> U31-M1C7T1 Data Latency : 58.1ns
U2-M0C1T0 <> U4-M0C2T0 Data Latency : 19.2ns
U2-M0C1T0 <> U6-M0C3T0 Data Latency : 20.8ns
U2-M0C1T0 <> U8-M0C4T0 Data Latency : 19.7ns
U2-M0C1T0 <> U10-M0C5T0 Data Latency : 21.4ns
U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.5ns
U2-M0C1T0 <> U14-M0C7T0 Data Latency : 21.0ns
U2-M0C1T0 <> U16-M1C0T0 Data Latency : 56.8ns
U2-M0C1T0 <> U18-M1C1T0 Data Latency : 57.0ns
U2-M0C1T0 <> U20-M1C2T0 Data Latency : 57.1ns
U2-M0C1T0 <> U22-M1C3T0 Data Latency : 60.9ns
U2-M0C1T0 <> U24-M1C4T0 Data Latency : 61.0ns
U2-M0C1T0 <> U26-M1C5T0 Data Latency : 60.8ns
U2-M0C1T0 <> U28-M1C6T0 Data Latency : 60.5ns
U2-M0C1T0 <> U30-M1C7T0 Data Latency : 60.3ns
U2-M0C1T0 <> U1-M0C0T1 Data Latency : 22.2ns
U2-M0C1T0 <> U3-M0C1T1 Data Latency : 10.0ns
U2-M0C1T0 <> U5-M0C2T1 Data Latency : 21.9ns
U2-M0C1T0 <> U7-M0C3T1 Data Latency : 23.0ns
U2-M0C1T0 <> U9-M0C4T1 Data Latency : 21.1ns
U2-M0C1T0 <> U11-M0C5T1 Data Latency : 22.3ns
U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.6ns
U2-M0C1T0 <> U15-M0C7T1 Data Latency : 21.8ns
U2-M0C1T0 <> U17-M1C0T1 Data Latency : 61.4ns
U2-M0C1T0 <> U19-M1C1T1 Data Latency : 61.1ns
U2-M0C1T0 <> U21-M1C2T1 Data Latency : 61.2ns
U2-M0C1T0 <> U23-M1C3T1 Data Latency : 60.9ns
U2-M0C1T0 <> U25-M1C4T1 Data Latency : 61.1ns
U2-M0C1T0 <> U27-M1C5T1 Data Latency : 60.8ns
U2-M0C1T0 <> U29-M1C6T1 Data Latency : 60.5ns
U2-M0C1T0 <> U31-M1C7T1 Data Latency : 60.3ns
U4-M0C2T0 <> U6-M0C3T0 Data Latency : 21.3ns
U4-M0C2T0 <> U8-M0C4T0 Data Latency : 20.6ns
U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.5ns
U4-M0C2T0 <> U12-M0C6T0 Data Latency : 19.9ns
U4-M0C2T0 <> U14-M0C7T0 Data Latency : 19.8ns
U4-M0C2T0 <> U16-M1C0T0 Data Latency : 60.3ns
U4-M0C2T0 <> U18-M1C1T0 Data Latency : 60.7ns
U4-M0C2T0 <> U20-M1C2T0 Data Latency : 60.2ns
U4-M0C2T0 <> U22-M1C3T0 Data Latency : 60.6ns
U4-M0C2T0 <> U24-M1C4T0 Data Latency : 59.7ns
U4-M0C2T0 <> U26-M1C5T0 Data Latency : 60.4ns
U4-M0C2T0 <> U28-M1C6T0 Data Latency : 59.6ns
U4-M0C2T0 <> U30-M1C7T0 Data Latency : 60.0ns
U4-M0C2T0 <> U1-M0C0T1 Data Latency : 22.0ns
U4-M0C2T0 <> U3-M0C1T1 Data Latency : 22.2ns
U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.8ns
U4-M0C2T0 <> U7-M0C3T1 Data Latency : 21.2ns
U4-M0C2T0 <> U9-M0C4T1 Data Latency : 20.6ns
U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.5ns
U4-M0C2T0 <> U13-M0C6T1 Data Latency : 19.9ns
U4-M0C2T0 <> U15-M0C7T1 Data Latency : 19.8ns
U4-M0C2T0 <> U17-M1C0T1 Data Latency : 60.4ns
U4-M0C2T0 <> U19-M1C1T1 Data Latency : 60.8ns
U4-M0C2T0 <> U21-M1C2T1 Data Latency : 60.1ns
U4-M0C2T0 <> U23-M1C3T1 Data Latency : 60.5ns
U4-M0C2T0 <> U25-M1C4T1 Data Latency : 59.7ns
U4-M0C2T0 <> U27-M1C5T1 Data Latency : 60.4ns
U4-M0C2T0 <> U29-M1C6T1 Data Latency : 59.6ns
U4-M0C2T0 <> U31-M1C7T1 Data Latency : 60.1ns
U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.6ns
U6-M0C3T0 <> U10-M0C5T0 Data Latency : 21.7ns
U6-M0C3T0 <> U12-M0C6T0 Data Latency : 19.9ns
U6-M0C3T0 <> U14-M0C7T0 Data Latency : 21.1ns
U6-M0C3T0 <> U16-M1C0T0 Data Latency : 61.1ns
U6-M0C3T0 <> U18-M1C1T0 Data Latency : 60.9ns
U6-M0C3T0 <> U20-M1C2T0 Data Latency : 60.9ns
U6-M0C3T0 <> U22-M1C3T0 Data Latency : 60.4ns
U6-M0C3T0 <> U24-M1C4T0 Data Latency : 60.4ns
U6-M0C3T0 <> U26-M1C5T0 Data Latency : 60.5ns
U6-M0C3T0 <> U28-M1C6T0 Data Latency : 60.2ns
U6-M0C3T0 <> U30-M1C7T0 Data Latency : 60.1ns
U6-M0C3T0 <> U1-M0C0T1 Data Latency : 21.9ns
U6-M0C3T0 <> U3-M0C1T1 Data Latency : 23.2ns
U6-M0C3T0 <> U5-M0C2T1 Data Latency : 21.4ns
U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.9ns
U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.7ns
U6-M0C3T0 <> U11-M0C5T1 Data Latency : 21.7ns
U6-M0C3T0 <> U13-M0C6T1 Data Latency : 19.9ns
U6-M0C3T0 <> U15-M0C7T1 Data Latency : 21.2ns
U6-M0C3T0 <> U17-M1C0T1 Data Latency : 57.0ns
U6-M0C3T0 <> U19-M1C1T1 Data Latency : 57.0ns
U6-M0C3T0 <> U21-M1C2T1 Data Latency : 57.3ns
U6-M0C3T0 <> U23-M1C3T1 Data Latency : 57.5ns
U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.0ns
U6-M0C3T0 <> U27-M1C5T1 Data Latency : 58.2ns
U6-M0C3T0 <> U29-M1C6T1 Data Latency : 58.6ns
U6-M0C3T0 <> U31-M1C7T1 Data Latency : 58.3ns
U8-M0C4T0 <> U10-M0C5T0 Data Latency : 21.0ns
U8-M0C4T0 <> U12-M0C6T0 Data Latency : 22.8ns
U8-M0C4T0 <> U14-M0C7T0 Data Latency : 21.7ns
U8-M0C4T0 <> U16-M1C0T0 Data Latency : 57.7ns
U8-M0C4T0 <> U18-M1C1T0 Data Latency : 57.2ns
U8-M0C4T0 <> U20-M1C2T0 Data Latency : 58.0ns
U8-M0C4T0 <> U22-M1C3T0 Data Latency : 57.8ns
U8-M0C4T0 <> U24-M1C4T0 Data Latency : 58.6ns
U8-M0C4T0 <> U26-M1C5T0 Data Latency : 58.4ns
U8-M0C4T0 <> U28-M1C6T0 Data Latency : 58.9ns
U8-M0C4T0 <> U30-M1C7T0 Data Latency : 58.8ns
U8-M0C4T0 <> U1-M0C0T1 Data Latency : 20.7ns
U8-M0C4T0 <> U3-M0C1T1 Data Latency : 19.9ns
U8-M0C4T0 <> U5-M0C2T1 Data Latency : 21.8ns
U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.5ns
U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.5ns
U8-M0C4T0 <> U11-M0C5T1 Data Latency : 21.0ns
U8-M0C4T0 <> U13-M0C6T1 Data Latency : 22.9ns
U8-M0C4T0 <> U15-M0C7T1 Data Latency : 21.7ns
U8-M0C4T0 <> U17-M1C0T1 Data Latency : 57.7ns
U8-M0C4T0 <> U19-M1C1T1 Data Latency : 57.2ns
U8-M0C4T0 <> U21-M1C2T1 Data Latency : 57.9ns
U8-M0C4T0 <> U23-M1C3T1 Data Latency : 57.8ns
U8-M0C4T0 <> U25-M1C4T1 Data Latency : 58.6ns
U8-M0C4T0 <> U27-M1C5T1 Data Latency : 58.4ns
U8-M0C4T0 <> U29-M1C6T1 Data Latency : 58.8ns
U8-M0C4T0 <> U31-M1C7T1 Data Latency : 58.7ns
U10-M0C5T0 <> U12-M0C6T0 Data Latency : 21.7ns
U10-M0C5T0 <> U14-M0C7T0 Data Latency : 21.7ns
U10-M0C5T0 <> U16-M1C0T0 Data Latency : 57.4ns
U10-M0C5T0 <> U18-M1C1T0 Data Latency : 57.1ns
U10-M0C5T0 <> U20-M1C2T0 Data Latency : 57.6ns
U10-M0C5T0 <> U22-M1C3T0 Data Latency : 57.8ns
U10-M0C5T0 <> U24-M1C4T0 Data Latency : 58.4ns
U10-M0C5T0 <> U26-M1C5T0 Data Latency : 58.3ns
U10-M0C5T0 <> U28-M1C6T0 Data Latency : 58.9ns
U10-M0C5T0 <> U30-M1C7T0 Data Latency : 58.2ns
U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.3ns
U10-M0C5T0 <> U3-M0C1T1 Data Latency : 20.9ns
U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.5ns
U10-M0C5T0 <> U7-M0C3T1 Data Latency : 21.5ns
U10-M0C5T0 <> U9-M0C4T1 Data Latency : 20.9ns
U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.8ns
U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.7ns
U10-M0C5T0 <> U15-M0C7T1 Data Latency : 21.7ns
U10-M0C5T0 <> U17-M1C0T1 Data Latency : 57.4ns
U10-M0C5T0 <> U19-M1C1T1 Data Latency : 57.2ns
U10-M0C5T0 <> U21-M1C2T1 Data Latency : 57.6ns
U10-M0C5T0 <> U23-M1C3T1 Data Latency : 57.6ns
U10-M0C5T0 <> U25-M1C4T1 Data Latency : 58.4ns
U10-M0C5T0 <> U27-M1C5T1 Data Latency : 58.3ns
U10-M0C5T0 <> U29-M1C6T1 Data Latency : 58.8ns
U10-M0C5T0 <> U31-M1C7T1 Data Latency : 58.3ns
U12-M0C6T0 <> U14-M0C7T0 Data Latency : 22.4ns
U12-M0C6T0 <> U16-M1C0T0 Data Latency : 58.4ns
U12-M0C6T0 <> U18-M1C1T0 Data Latency : 57.8ns
U12-M0C6T0 <> U20-M1C2T0 Data Latency : 58.5ns
U12-M0C6T0 <> U22-M1C3T0 Data Latency : 58.7ns
U12-M0C6T0 <> U24-M1C4T0 Data Latency : 59.1ns
U12-M0C6T0 <> U26-M1C5T0 Data Latency : 59.0ns
U12-M0C6T0 <> U28-M1C6T0 Data Latency : 59.7ns
U12-M0C6T0 <> U30-M1C7T0 Data Latency : 59.8ns
U12-M0C6T0 <> U1-M0C0T1 Data Latency : 21.6ns
U12-M0C6T0 <> U3-M0C1T1 Data Latency : 20.7ns
U12-M0C6T0 <> U5-M0C2T1 Data Latency : 22.4ns
U12-M0C6T0 <> U7-M0C3T1 Data Latency : 21.3ns
U12-M0C6T0 <> U9-M0C4T1 Data Latency : 22.9ns
U12-M0C6T0 <> U11-M0C5T1 Data Latency : 21.8ns
U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.9ns
U12-M0C6T0 <> U15-M0C7T1 Data Latency : 22.5ns
U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.4ns
U12-M0C6T0 <> U19-M1C1T1 Data Latency : 58.0ns
U12-M0C6T0 <> U21-M1C2T1 Data Latency : 58.5ns
U12-M0C6T0 <> U23-M1C3T1 Data Latency : 58.6ns
U12-M0C6T0 <> U25-M1C4T1 Data Latency : 59.1ns
U12-M0C6T0 <> U27-M1C5T1 Data Latency : 59.0ns
U12-M0C6T0 <> U29-M1C6T1 Data Latency : 59.7ns
U12-M0C6T0 <> U31-M1C7T1 Data Latency : 59.7ns
U14-M0C7T0 <> U16-M1C0T0 Data Latency : 58.0ns
U14-M0C7T0 <> U18-M1C1T0 Data Latency : 57.6ns
U14-M0C7T0 <> U20-M1C2T0 Data Latency : 58.1ns
U14-M0C7T0 <> U22-M1C3T0 Data Latency : 58.1ns
U14-M0C7T0 <> U24-M1C4T0 Data Latency : 59.1ns
U14-M0C7T0 <> U26-M1C5T0 Data Latency : 58.5ns
U14-M0C7T0 <> U28-M1C6T0 Data Latency : 59.6ns
U14-M0C7T0 <> U30-M1C7T0 Data Latency : 59.1ns
U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.6ns
U14-M0C7T0 <> U3-M0C1T1 Data Latency : 20.8ns
U14-M0C7T0 <> U5-M0C2T1 Data Latency : 21.3ns
U14-M0C7T0 <> U7-M0C3T1 Data Latency : 21.4ns
U14-M0C7T0 <> U9-M0C4T1 Data Latency : 21.7ns
U14-M0C7T0 <> U11-M0C5T1 Data Latency : 21.9ns
U14-M0C7T0 <> U13-M0C6T1 Data Latency : 22.3ns
U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.8ns
U14-M0C7T0 <> U17-M1C0T1 Data Latency : 57.9ns
U14-M0C7T0 <> U19-M1C1T1 Data Latency : 57.5ns
U14-M0C7T0 <> U21-M1C2T1 Data Latency : 58.1ns
U14-M0C7T0 <> U23-M1C3T1 Data Latency : 58.2ns
U14-M0C7T0 <> U25-M1C4T1 Data Latency : 59.0ns
U14-M0C7T0 <> U27-M1C5T1 Data Latency : 58.5ns
U14-M0C7T0 <> U29-M1C6T1 Data Latency : 59.5ns
U14-M0C7T0 <> U31-M1C7T1 Data Latency : 59.1ns
U16-M1C0T0 <> U18-M1C1T0 Data Latency : 19.2ns
U16-M1C0T0 <> U20-M1C2T0 Data Latency : 20.0ns
U16-M1C0T0 <> U22-M1C3T0 Data Latency : 19.7ns
U16-M1C0T0 <> U24-M1C4T0 Data Latency : 20.9ns
U16-M1C0T0 <> U26-M1C5T0 Data Latency : 20.3ns
U16-M1C0T0 <> U28-M1C6T0 Data Latency : 21.5ns
U16-M1C0T0 <> U30-M1C7T0 Data Latency : 20.5ns
U16-M1C0T0 <> U1-M0C0T1 Data Latency : 57.1ns
U16-M1C0T0 <> U3-M0C1T1 Data Latency : 56.9ns
U16-M1C0T0 <> U5-M0C2T1 Data Latency : 57.0ns
U16-M1C0T0 <> U7-M0C3T1 Data Latency : 57.4ns
U16-M1C0T0 <> U9-M0C4T1 Data Latency : 57.6ns
U16-M1C0T0 <> U11-M0C5T1 Data Latency : 57.6ns
U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.2ns
U16-M1C0T0 <> U15-M0C7T1 Data Latency : 58.0ns
U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.8ns
U16-M1C0T0 <> U19-M1C1T1 Data Latency : 19.2ns
U16-M1C0T0 <> U21-M1C2T1 Data Latency : 20.1ns
U16-M1C0T0 <> U23-M1C3T1 Data Latency : 19.7ns
U16-M1C0T0 <> U25-M1C4T1 Data Latency : 20.9ns
U16-M1C0T0 <> U27-M1C5T1 Data Latency : 20.3ns
U16-M1C0T0 <> U29-M1C6T1 Data Latency : 21.5ns
U16-M1C0T0 <> U31-M1C7T1 Data Latency : 20.5ns
U18-M1C1T0 <> U20-M1C2T0 Data Latency : 18.9ns
U18-M1C1T0 <> U22-M1C3T0 Data Latency : 19.9ns
U18-M1C1T0 <> U24-M1C4T0 Data Latency : 19.7ns
U18-M1C1T0 <> U26-M1C5T0 Data Latency : 20.5ns
U18-M1C1T0 <> U28-M1C6T0 Data Latency : 20.5ns
U18-M1C1T0 <> U30-M1C7T0 Data Latency : 20.4ns
U18-M1C1T0 <> U1-M0C0T1 Data Latency : 56.1ns
U18-M1C1T0 <> U3-M0C1T1 Data Latency : 56.8ns
U18-M1C1T0 <> U5-M0C2T1 Data Latency : 56.9ns
U18-M1C1T0 <> U7-M0C3T1 Data Latency : 57.1ns
U18-M1C1T0 <> U9-M0C4T1 Data Latency : 57.0ns
U18-M1C1T0 <> U11-M0C5T1 Data Latency : 57.1ns
U18-M1C1T0 <> U13-M0C6T1 Data Latency : 57.7ns
U18-M1C1T0 <> U15-M0C7T1 Data Latency : 57.3ns
U18-M1C1T0 <> U17-M1C0T1 Data Latency : 19.2ns
U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.8ns
U18-M1C1T0 <> U21-M1C2T1 Data Latency : 18.9ns
U18-M1C1T0 <> U23-M1C3T1 Data Latency : 19.9ns
U18-M1C1T0 <> U25-M1C4T1 Data Latency : 19.7ns
U18-M1C1T0 <> U27-M1C5T1 Data Latency : 20.5ns
U18-M1C1T0 <> U29-M1C6T1 Data Latency : 20.4ns
U18-M1C1T0 <> U31-M1C7T1 Data Latency : 20.4ns
U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.6ns
U20-M1C2T0 <> U24-M1C4T0 Data Latency : 21.6ns
U20-M1C2T0 <> U26-M1C5T0 Data Latency : 20.4ns
U20-M1C2T0 <> U28-M1C6T0 Data Latency : 22.0ns
U20-M1C2T0 <> U30-M1C7T0 Data Latency : 21.1ns
U20-M1C2T0 <> U1-M0C0T1 Data Latency : 57.1ns
U20-M1C2T0 <> U3-M0C1T1 Data Latency : 57.7ns
U20-M1C2T0 <> U5-M0C2T1 Data Latency : 57.4ns
U20-M1C2T0 <> U7-M0C3T1 Data Latency : 57.6ns
U20-M1C2T0 <> U9-M0C4T1 Data Latency : 57.7ns
U20-M1C2T0 <> U11-M0C5T1 Data Latency : 58.2ns
U20-M1C2T0 <> U13-M0C6T1 Data Latency : 58.3ns
U20-M1C2T0 <> U15-M0C7T1 Data Latency : 58.2ns
U20-M1C2T0 <> U17-M1C0T1 Data Latency : 20.1ns
U20-M1C2T0 <> U19-M1C1T1 Data Latency : 19.0ns
U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.8ns
U20-M1C2T0 <> U23-M1C3T1 Data Latency : 19.5ns
U20-M1C2T0 <> U25-M1C4T1 Data Latency : 21.6ns
U20-M1C2T0 <> U27-M1C5T1 Data Latency : 20.4ns
U20-M1C2T0 <> U29-M1C6T1 Data Latency : 22.0ns
U20-M1C2T0 <> U31-M1C7T1 Data Latency : 21.1ns
U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.4ns
U22-M1C3T0 <> U26-M1C5T0 Data Latency : 21.3ns
U22-M1C3T0 <> U28-M1C6T0 Data Latency : 21.0ns
U22-M1C3T0 <> U30-M1C7T0 Data Latency : 20.9ns
U22-M1C3T0 <> U1-M0C0T1 Data Latency : 57.0ns
U22-M1C3T0 <> U3-M0C1T1 Data Latency : 57.7ns
U22-M1C3T0 <> U5-M0C2T1 Data Latency : 57.4ns
U22-M1C3T0 <> U7-M0C3T1 Data Latency : 57.7ns
U22-M1C3T0 <> U9-M0C4T1 Data Latency : 57.6ns
U22-M1C3T0 <> U11-M0C5T1 Data Latency : 57.9ns
U22-M1C3T0 <> U13-M0C6T1 Data Latency : 58.3ns
U22-M1C3T0 <> U15-M0C7T1 Data Latency : 58.1ns
U22-M1C3T0 <> U17-M1C0T1 Data Latency : 19.6ns
U22-M1C3T0 <> U19-M1C1T1 Data Latency : 20.0ns
U22-M1C3T0 <> U21-M1C2T1 Data Latency : 19.4ns
U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.8ns
U22-M1C3T0 <> U25-M1C4T1 Data Latency : 20.4ns
U22-M1C3T0 <> U27-M1C5T1 Data Latency : 21.3ns
U22-M1C3T0 <> U29-M1C6T1 Data Latency : 21.0ns
U22-M1C3T0 <> U31-M1C7T1 Data Latency : 20.9ns
U24-M1C4T0 <> U26-M1C5T0 Data Latency : 21.2ns
U24-M1C4T0 <> U28-M1C6T0 Data Latency : 22.9ns
U24-M1C4T0 <> U30-M1C7T0 Data Latency : 21.9ns
U24-M1C4T0 <> U1-M0C0T1 Data Latency : 57.9ns
U24-M1C4T0 <> U3-M0C1T1 Data Latency : 58.3ns
U24-M1C4T0 <> U5-M0C2T1 Data Latency : 58.1ns
U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.3ns
U24-M1C4T0 <> U9-M0C4T1 Data Latency : 58.7ns
U24-M1C4T0 <> U11-M0C5T1 Data Latency : 58.9ns
U24-M1C4T0 <> U13-M0C6T1 Data Latency : 59.3ns
U24-M1C4T0 <> U15-M0C7T1 Data Latency : 59.1ns
U24-M1C4T0 <> U17-M1C0T1 Data Latency : 21.1ns
U24-M1C4T0 <> U19-M1C1T1 Data Latency : 19.8ns
U24-M1C4T0 <> U21-M1C2T1 Data Latency : 21.7ns
U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.5ns
U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.9ns
U24-M1C4T0 <> U27-M1C5T1 Data Latency : 21.3ns
U24-M1C4T0 <> U29-M1C6T1 Data Latency : 22.9ns
U24-M1C4T0 <> U31-M1C7T1 Data Latency : 21.9ns
U26-M1C5T0 <> U28-M1C6T0 Data Latency : 21.6ns
U26-M1C5T0 <> U30-M1C7T0 Data Latency : 21.7ns
U26-M1C5T0 <> U1-M0C0T1 Data Latency : 57.4ns
U26-M1C5T0 <> U3-M0C1T1 Data Latency : 58.2ns
U26-M1C5T0 <> U5-M0C2T1 Data Latency : 57.9ns
U26-M1C5T0 <> U7-M0C3T1 Data Latency : 58.2ns
U26-M1C5T0 <> U9-M0C4T1 Data Latency : 58.2ns
U26-M1C5T0 <> U11-M0C5T1 Data Latency : 58.3ns
U26-M1C5T0 <> U13-M0C6T1 Data Latency : 58.9ns
U26-M1C5T0 <> U15-M0C7T1 Data Latency : 58.7ns
U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.3ns
U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.6ns
U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.2ns
U26-M1C5T0 <> U23-M1C3T1 Data Latency : 21.3ns
U26-M1C5T0 <> U25-M1C4T1 Data Latency : 21.1ns
U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.8ns
U26-M1C5T0 <> U29-M1C6T1 Data Latency : 21.6ns
U26-M1C5T0 <> U31-M1C7T1 Data Latency : 21.7ns
U28-M1C6T0 <> U30-M1C7T0 Data Latency : 22.3ns
U28-M1C6T0 <> U1-M0C0T1 Data Latency : 58.4ns
U28-M1C6T0 <> U3-M0C1T1 Data Latency : 58.7ns
U28-M1C6T0 <> U5-M0C2T1 Data Latency : 58.8ns
U28-M1C6T0 <> U7-M0C3T1 Data Latency : 59.1ns
U28-M1C6T0 <> U9-M0C4T1 Data Latency : 58.9ns
U28-M1C6T0 <> U11-M0C5T1 Data Latency : 59.2ns
U28-M1C6T0 <> U13-M0C6T1 Data Latency : 59.6ns
U28-M1C6T0 <> U15-M0C7T1 Data Latency : 59.5ns
U28-M1C6T0 <> U17-M1C0T1 Data Latency : 21.6ns
U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.4ns
U28-M1C6T0 <> U21-M1C2T1 Data Latency : 22.2ns
U28-M1C6T0 <> U23-M1C3T1 Data Latency : 21.1ns
U28-M1C6T0 <> U25-M1C4T1 Data Latency : 23.0ns
U28-M1C6T0 <> U27-M1C5T1 Data Latency : 21.7ns
U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.8ns
U28-M1C6T0 <> U31-M1C7T1 Data Latency : 22.3ns
U30-M1C7T0 <> U1-M0C0T1 Data Latency : 58.0ns
U30-M1C7T0 <> U3-M0C1T1 Data Latency : 58.4ns
U30-M1C7T0 <> U5-M0C2T1 Data Latency : 58.4ns
U30-M1C7T0 <> U7-M0C3T1 Data Latency : 58.8ns
U30-M1C7T0 <> U9-M0C4T1 Data Latency : 58.7ns
U30-M1C7T0 <> U11-M0C5T1 Data Latency : 58.6ns
U30-M1C7T0 <> U13-M0C6T1 Data Latency : 59.5ns
U30-M1C7T0 <> U15-M0C7T1 Data Latency : 59.2ns
U30-M1C7T0 <> U17-M1C0T1 Data Latency : 20.6ns
U30-M1C7T0 <> U19-M1C1T1 Data Latency : 20.6ns
U30-M1C7T0 <> U21-M1C2T1 Data Latency : 21.1ns
U30-M1C7T0 <> U23-M1C3T1 Data Latency : 21.2ns
U30-M1C7T0 <> U25-M1C4T1 Data Latency : 21.9ns
U30-M1C7T0 <> U27-M1C5T1 Data Latency : 22.0ns
U30-M1C7T0 <> U29-M1C6T1 Data Latency : 22.2ns
U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.8ns
U1-M0C0T1 <> U3-M0C1T1 Data Latency : 19.4ns
U1-M0C0T1 <> U5-M0C2T1 Data Latency : 20.2ns
U1-M0C0T1 <> U7-M0C3T1 Data Latency : 19.9ns
U1-M0C0T1 <> U9-M0C4T1 Data Latency : 20.6ns
U1-M0C0T1 <> U11-M0C5T1 Data Latency : 20.2ns
U1-M0C0T1 <> U13-M0C6T1 Data Latency : 21.5ns
U1-M0C0T1 <> U15-M0C7T1 Data Latency : 20.5ns
U1-M0C0T1 <> U17-M1C0T1 Data Latency : 56.9ns
U1-M0C0T1 <> U19-M1C1T1 Data Latency : 56.3ns
U1-M0C0T1 <> U21-M1C2T1 Data Latency : 57.0ns
U1-M0C0T1 <> U23-M1C3T1 Data Latency : 57.1ns
U1-M0C0T1 <> U25-M1C4T1 Data Latency : 57.9ns
U1-M0C0T1 <> U27-M1C5T1 Data Latency : 57.6ns
U1-M0C0T1 <> U29-M1C6T1 Data Latency : 58.3ns
U1-M0C0T1 <> U31-M1C7T1 Data Latency : 57.9ns
U3-M0C1T1 <> U5-M0C2T1 Data Latency : 19.4ns
U3-M0C1T1 <> U7-M0C3T1 Data Latency : 20.3ns
U3-M0C1T1 <> U9-M0C4T1 Data Latency : 19.9ns
U3-M0C1T1 <> U11-M0C5T1 Data Latency : 20.8ns
U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.8ns
U3-M0C1T1 <> U15-M0C7T1 Data Latency : 20.7ns
U3-M0C1T1 <> U17-M1C0T1 Data Latency : 57.0ns
U3-M0C1T1 <> U19-M1C1T1 Data Latency : 56.8ns
U3-M0C1T1 <> U21-M1C2T1 Data Latency : 57.2ns
U3-M0C1T1 <> U23-M1C3T1 Data Latency : 57.2ns
U3-M0C1T1 <> U25-M1C4T1 Data Latency : 57.8ns
U3-M0C1T1 <> U27-M1C5T1 Data Latency : 57.7ns
U3-M0C1T1 <> U29-M1C6T1 Data Latency : 58.7ns
U3-M0C1T1 <> U31-M1C7T1 Data Latency : 58.1ns
U5-M0C2T1 <> U7-M0C3T1 Data Latency : 19.8ns
U5-M0C2T1 <> U9-M0C4T1 Data Latency : 21.7ns
U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.6ns
U5-M0C2T1 <> U13-M0C6T1 Data Latency : 22.3ns
U5-M0C2T1 <> U15-M0C7T1 Data Latency : 21.3ns
U5-M0C2T1 <> U17-M1C0T1 Data Latency : 57.3ns
U5-M0C2T1 <> U19-M1C1T1 Data Latency : 57.2ns
U5-M0C2T1 <> U21-M1C2T1 Data Latency : 57.4ns
U5-M0C2T1 <> U23-M1C3T1 Data Latency : 57.7ns
U5-M0C2T1 <> U25-M1C4T1 Data Latency : 58.2ns
U5-M0C2T1 <> U27-M1C5T1 Data Latency : 58.3ns
U5-M0C2T1 <> U29-M1C6T1 Data Latency : 58.7ns
U5-M0C2T1 <> U31-M1C7T1 Data Latency : 58.6ns
U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.5ns
U7-M0C3T1 <> U11-M0C5T1 Data Latency : 21.6ns
U7-M0C3T1 <> U13-M0C6T1 Data Latency : 21.3ns
U7-M0C3T1 <> U15-M0C7T1 Data Latency : 21.2ns
U7-M0C3T1 <> U17-M1C0T1 Data Latency : 57.0ns
U7-M0C3T1 <> U19-M1C1T1 Data Latency : 57.1ns
U7-M0C3T1 <> U21-M1C2T1 Data Latency : 57.1ns
U7-M0C3T1 <> U23-M1C3T1 Data Latency : 57.5ns
U7-M0C3T1 <> U25-M1C4T1 Data Latency : 57.9ns
U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.1ns
U7-M0C3T1 <> U29-M1C6T1 Data Latency : 58.7ns
U7-M0C3T1 <> U31-M1C7T1 Data Latency : 58.2ns
U9-M0C4T1 <> U11-M0C5T1 Data Latency : 21.0ns
U9-M0C4T1 <> U13-M0C6T1 Data Latency : 22.9ns
U9-M0C4T1 <> U15-M0C7T1 Data Latency : 21.7ns
U9-M0C4T1 <> U17-M1C0T1 Data Latency : 57.7ns
U9-M0C4T1 <> U19-M1C1T1 Data Latency : 57.3ns
U9-M0C4T1 <> U21-M1C2T1 Data Latency : 58.0ns
U9-M0C4T1 <> U23-M1C3T1 Data Latency : 57.8ns
U9-M0C4T1 <> U25-M1C4T1 Data Latency : 58.6ns
U9-M0C4T1 <> U27-M1C5T1 Data Latency : 58.4ns
U9-M0C4T1 <> U29-M1C6T1 Data Latency : 58.9ns
U9-M0C4T1 <> U31-M1C7T1 Data Latency : 58.9ns
U11-M0C5T1 <> U13-M0C6T1 Data Latency : 21.7ns
U11-M0C5T1 <> U15-M0C7T1 Data Latency : 21.7ns
U11-M0C5T1 <> U17-M1C0T1 Data Latency : 57.4ns
U11-M0C5T1 <> U19-M1C1T1 Data Latency : 57.3ns
U11-M0C5T1 <> U21-M1C2T1 Data Latency : 57.6ns
U11-M0C5T1 <> U23-M1C3T1 Data Latency : 57.8ns
U11-M0C5T1 <> U25-M1C4T1 Data Latency : 58.5ns
U11-M0C5T1 <> U27-M1C5T1 Data Latency : 58.4ns
U11-M0C5T1 <> U29-M1C6T1 Data Latency : 58.9ns
U11-M0C5T1 <> U31-M1C7T1 Data Latency : 58.4ns
U13-M0C6T1 <> U15-M0C7T1 Data Latency : 22.9ns
U13-M0C6T1 <> U17-M1C0T1 Data Latency : 58.4ns
U13-M0C6T1 <> U19-M1C1T1 Data Latency : 57.9ns
U13-M0C6T1 <> U21-M1C2T1 Data Latency : 58.5ns
U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.6ns
U13-M0C6T1 <> U25-M1C4T1 Data Latency : 59.0ns
U13-M0C6T1 <> U27-M1C5T1 Data Latency : 59.0ns
U13-M0C6T1 <> U29-M1C6T1 Data Latency : 59.7ns
U13-M0C6T1 <> U31-M1C7T1 Data Latency : 59.8ns
U15-M0C7T1 <> U17-M1C0T1 Data Latency : 57.9ns
U15-M0C7T1 <> U19-M1C1T1 Data Latency : 57.6ns
U15-M0C7T1 <> U21-M1C2T1 Data Latency : 58.1ns
U15-M0C7T1 <> U23-M1C3T1 Data Latency : 58.2ns
U15-M0C7T1 <> U25-M1C4T1 Data Latency : 59.0ns
U15-M0C7T1 <> U27-M1C5T1 Data Latency : 58.6ns
U15-M0C7T1 <> U29-M1C6T1 Data Latency : 59.5ns
U15-M0C7T1 <> U31-M1C7T1 Data Latency : 59.2ns
U17-M1C0T1 <> U19-M1C1T1 Data Latency : 19.2ns
U17-M1C0T1 <> U21-M1C2T1 Data Latency : 20.0ns
U17-M1C0T1 <> U23-M1C3T1 Data Latency : 19.7ns
U17-M1C0T1 <> U25-M1C4T1 Data Latency : 20.9ns
U17-M1C0T1 <> U27-M1C5T1 Data Latency : 20.4ns
U17-M1C0T1 <> U29-M1C6T1 Data Latency : 21.5ns
U17-M1C0T1 <> U31-M1C7T1 Data Latency : 20.5ns
U19-M1C1T1 <> U21-M1C2T1 Data Latency : 18.9ns
U19-M1C1T1 <> U23-M1C3T1 Data Latency : 19.9ns
U19-M1C1T1 <> U25-M1C4T1 Data Latency : 19.7ns
U19-M1C1T1 <> U27-M1C5T1 Data Latency : 20.5ns
U19-M1C1T1 <> U29-M1C6T1 Data Latency : 20.4ns
U19-M1C1T1 <> U31-M1C7T1 Data Latency : 20.4ns
U21-M1C2T1 <> U23-M1C3T1 Data Latency : 19.6ns
U21-M1C2T1 <> U25-M1C4T1 Data Latency : 21.6ns
U21-M1C2T1 <> U27-M1C5T1 Data Latency : 20.4ns
U21-M1C2T1 <> U29-M1C6T1 Data Latency : 22.0ns
U21-M1C2T1 <> U31-M1C7T1 Data Latency : 21.1ns
U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.4ns
U23-M1C3T1 <> U27-M1C5T1 Data Latency : 21.3ns
U23-M1C3T1 <> U29-M1C6T1 Data Latency : 21.0ns
U23-M1C3T1 <> U31-M1C7T1 Data Latency : 21.0ns
U25-M1C4T1 <> U27-M1C5T1 Data Latency : 21.3ns
U25-M1C4T1 <> U29-M1C6T1 Data Latency : 23.0ns
U25-M1C4T1 <> U31-M1C7T1 Data Latency : 21.9ns
U27-M1C5T1 <> U29-M1C6T1 Data Latency : 21.6ns
U27-M1C5T1 <> U31-M1C7T1 Data Latency : 21.7ns
U29-M1C6T1 <> U31-M1C7T1 Data Latency : 22.2ns
1x 64bytes Blocks Bandwidth : 26GB/s
4x 64bytes Blocks Bandwidth : 28.76GB/s
4x 256bytes Blocks Bandwidth : 96.46GB/s
4x 1kB Blocks Bandwidth : 321.1GB/s
4x 4kB Blocks Bandwidth : 507GB/s
16x 4kB Blocks Bandwidth : 726.56GB/s
4x 64kB Blocks Bandwidth : 995.61GB/s
16x 64kB Blocks Bandwidth : 598.29GB/s
8x 256kB Blocks Bandwidth : 602.17GB/s
4x 1MB Blocks Bandwidth : 608.9GB/s
16x 1MB Blocks Bandwidth : 24.7GB/s
8x 4MB Blocks Bandwidth : 19.17GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 5GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
Microcode : A20F10-1009
Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
Platform Compliance : x64
No. Threads : 32
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5950X 16-Core Processor
URL : https://www.amd.com
Speed : 5GHz
Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 5GHz
Modules per Processor : 2 Unit(s)
Cores per Processor : 8 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : A20F10-1009
L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
Rated Power (TDP) : 105.00W

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.
Hi @KedarWolf, I´d like your timings. I just testing it with my 3800CL14, that seems to be the same memory type (Mine shows A2: F4-3800CL14-16TGNZ (16GB, DR). I´m a liitle tired to try tRCDRD in 15. A quick question, how did you calculate your TRP to 19 and tRAS 21? Then the tWR at 10 and tRTP 6? Shouln´t be tWRT 12? I should have to think outside the rulesets :)

At last, I am new using SiSandra, its a powerful tool, however no s intuitive yet, how did you export the text output below your graph? I tried to make some report.. also the export options but only allos to export to XML, CSV....

I let you know how my test with your timings results.

Thanks!
 

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Hi , I would like to know if any of you are using any High Performance Plan by BIOS. I´m actually using SMU 56.45 and I want to lower some version to try above 4000 Freq without WHEAs. I read from Veii that Patch B, not C, would perform well abobe 4000 Freq. Some time ago I read a post from 1Usmus that recommended certain parameters in the BIOS and since I am optimizing my memory overclocking I would like to know if any of these parameters could help or perhaps thet are complicating my OC . Among them I had set these options:

  1. Global C-state Control = Enabled (Advanced\AMD CBS). I set ti to disable to prevent Reboots under idle. However I was reading that rising IOD Voltage above 1.05V would prevent reboots. Is that right?
  2. DF CStates = Disabled (Advanced\AMD CBS\NBIO Common Options\SMU Common Options\DF Cstates = Disabled)
    This setting does not allow for Infinity Fabric to go to a low-power state when the processor has entered Cx states..
  3. PPC Adjustment = PState 0. Two settings below:
    (Advanced\AMD CBS\NBIO Common Options\SMU Common Options\APBDIS = 1
    AND

    (Advanced\AMD CBS\NBIO Common Options\SMU Common Options\Fixed SOC Pstate = P0)
    4. CPPC = Enabled (Advanced\AMD CBS\NBIO Common Options\SMU Common Options)
    5. CPPC Preferred Cores = Enabled (Advanced\AMD CBS\NBIO Common Options\SMU Common Options)
    6. Power Supply Idle Control = Low Current Idle (Advanced\AMD CBS\CPU Common Options) Here I had set it to "Typical Power Idle" however it suggest Low Current, do you know what would be better?
  4. PBO: Enable Precision Boost Overdrive in UEFI BIOS. Allow it to run from the BIOS/Motherboard control. This is much easier than setting in AMD Ryzen Master manually in Windows; just enable these BIOS Options and don't mess with Ryzen Master in Windows except to experiment. PBO: Ai Tweaker or Extreme Tweaker on Asus mobo's\Precision Boost Overdrive, Accept\Precision Boost Overdrive = Enabled; Advanced\AMD Overclocking, Accept\Precision Boost Overdrive = Enabled, . PBO: Advanced\AMD CBS\NBIO Common Options, Accept\XFR Enhancement, Accept\ Precision Boost Overdrive = Enabled. Does it necessary to enable in all of the BIOS options? I only set it on Advanced Overclokng. All the rest values I leave in AUTO
  5. PBO FMax Enhancer: Ai Tweaker or Extreme Tweaker on Asus mobo's\Precision Boost Overdrive, Accept\PBO Fmax Enhancer = Enabled ***Many people report they get better results with this option set it to DISABLED. Try it both ways to see which gives the better score It appears to not be needed (set to Disable) on Ryzen 5000/Zen 3 CPU's and effects scores negatively.. (I set to Disable)
And also enable to improve L3 Cache, but it is not improving it much, it should be above 650GB / s flat with 10.4 sec latency
  • "SOC Uncore = Enable"
  • cTDP = 400
  • Package Power Liimit 400 (CBS-SMU)
  • Then DPM LCLK to 2-1-1-1-2-1-1-1
  • And also Enabled PMU Training until Phy Configuration (CBS\DDR4 Common Options); DFE, FFE both enabled ad PMU Pattern Bits Control to "A"
And also disable SB Clock Spread Spectrum, and set VTTDDR Voltage = VDIMM /2 . What I dont know what is VPP_MEM, anybody knows?

All of this to have a @high performance power plan. Maybe some settings would be an overkill.

And I take the opportunity to validate if my External DIGI + Power Control (on ASUS..but it´s LLC config) are fine, I set it to:
  • Voltage Monitor = Die Sense
  • CPU LLC Auto (I know Level 3 woud be better, but If I leave to Auto I got a better CB Score, maybe it rise automatically to Level 4
  • CPU Current Capabiliy to 120%
  • CPU VRM Switching Freq to Manual and I set 500 KHz
  • CPU Power Duty Control = T. Probe
  • CPU: Pwer Phase Control to Optimizd
  • CPU Power thermal Control to 120
  • VDDSOC LLC = Level 4
  • VDDSCO Switching Freq to 500 also
  • VDDSOC: Power Phase Response and Manual Adjustment to FAST and
  • DRAM Current Capability 110%
  • DRAM Power Phase Control = Leave it as Extreme
  • DRAM Switching Freq Manual Fix it to 300.
Would it be right for MEM OC?

Could my PBO Settings + Curve Optimizer impact in Mem OC? I also set to default, just enable it, and other test was to set only PBO Limits to motherboard.. and then I left with my best tight value that is 300/235/400 with CO -28 -26 -26 -28 -25 (my best 1st core), -24 (my 2nd best core), then CCD2, -28, -25- 24 -28 - 30 -30 with +100 Boost Clock Override.. I´m not using scalar. I read that it might degrade the CPU with some spikes.. and Platform Thermal Throttle Limit to 85. I think I would try set to All Core negative to -24 that is my lowest curve value, maybe the PBO algorithm perform better that setting per core values, and perhaps I should add a little + VCore Offset. My default CPU Core Voltage is around 1.425~1457. I see it a little bit low, because if I remember correctly, it was 1.5..very high. Por some reason the reading now is a little low, even If I clear CMOS and start over from scratch,

I hope you can advise me if these values are you using , if some would be overkill or I should adjust some of them, and if you have any other recommendation about the values of my PBO, maybe I could try All Cores but my question is how much the Offset value would be. I know that much voltage is not good.

Thanks!
 

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This have completely ruined performance, +5 seconds in membench 1.7.3 Rtt_nom off just doesn't boot, I have 4x8 sticks and I thought 7/3/1 is default for that? So I'm left with lowering vdimm and proc, I guess, but no luck so far.
Isnt the goal to get it stable in the first place
They are slower, but its not that extreme ~ as i run them at 7-9-28
Maybe the instability got worse, but they play together with SD-DDs

Depends what you've tried
Would RTT_NOM disabled post if you increase RTT_PARK to /2 with at least 40 or higher ClkDrvStr (CAD_BUS first value)

The RTT values that where shared for Matisse as easy to run options, are not optimal anymore
Vermeer works a bit different that Matisse
Since the recent 1201 and 1202 update, my settings fully bricked
Was initially running 6/3/6 , but i had to go down to 5/3/7 or even 6/3/0 worked

Something changed with the IMC, and i'm still testing around
Compared to 1200 , but IPC increased nicely
5-23% according to geekbench
Just it spills random 2's out for some random reason
@Veii
If you're not too busy traveling and making music would you mind taking a look at the screenshots I've got posted above and tell me what I should do to improve the efficacy of my efforts here? Please and thank you always
This just spewed errors #0, #12, and #6 within a minute of starting TM5
2488916
Is this TM5 profile based upon 1usmus_v3 ?
Because for example Anta's profile , the error numbers differ fully and mean something completely different
CsOdtDrvStr got a bump between 30-40ohm , in order to work against the broken memory training since AGESA 1.1.0.0A
After Patch C , it got worse and worse / this was about the correct option, to get it towards a useable setting
It's not fitting for Matisse.
There the hard work of 1usmus from the DRAM calculator works blindly

ClkDrvStr bump still is a good method to help lowering procODT and getting GDM off
Which btw is too high for you
in combination with high ClkDrvStr, it might be too much for the PCB and you can "PCB Crash" - IF the errors mean the same which they do on Yuri's preset

Matisse's procODT range was:
28-32ohm for 2x8GB SR
34-36ohm for Dual Rank or 4x8Gb
34~ for Rev.E or Micron B-Die
30-32 for Hynix-MFR or AFR (CJR should be fine within 30)
Overall it's too high.

The minimum & optimal value at 900-950-1050 (1900FCLK) on Matisse was 28ohm with B-dies, and anything else a tad higher.
But not 3 steps higher like you do run atm.
It also needed the UncoreOC flag inside AMD OVERCLOCKING enabled, else FIT was autocorrecting the voltage you set and ignore it fully
(a long story with buggy Dynamic FCLK & Dynamic SOC)

Another thing is that you run tRAS+2.
If you want to move inside JEDEC's range, you need to use +4 for SR ~ or don' follow it and run tRCD+tRCD (28)
tRC "technically optimally" would remain that 32+tRP.
That under *8 multiplier from my anchor's would be 368-273-168, with tWR 16 (8.421111....to the infinite)

But JEDEC up to which revision out of the 30+ , you refer to - doesn't always define what has to work.
It's not recommend to follow it like a holy book. Especially when this holy book had over 30 revisions :)

I'm also a bit conflicted with your tWRRD & tWTR set
4-12 should run, but i can't recommend stuff blindly without double-testing SD,DD relationship here.
Try to get it stable under SLC 4-4 , with your current setting and bump up tRRD & tWTR (5-14) , till you have something that passes at least 20 cycles TM5
(or anything that takes longer than 1h to test ~ soo you hit thermal equilibrium & still have a full cycle to test)

RTT 7/0/6 is a bit special
Combine it please with tCKE 9
It does work also for Matisse, but CAD_BUS SETUP timings could missmatch
I think what you surely want, is to drop VDDG IOD a bit near that 1v range or even 950mV with procODT max 32ohm
32ohm shouldn't allow you to run VDDG IOD to 950mV but 28ohm will !
ClkDrvStr doesn't care about it, you can keep running 40 or 60ohm there ~ just have in your backhead, that it is a (A) multiplier , soo if you want to increase RTT_PARK strengthness for example /6 or /5, lower it down to 40ohm instead of 60 (for single rank) . Or lower VDIMM down :)

About Matisse,
24-20-20-24 is what works , similar for Zen 1
24-20-24-24 should be used on lower quality PCBs to prevent cold boot issues, but higher than 24 is not needed on any board for Matisse and lower
30-20-20-24 is fine, same as 40-20-20-24 is fine
60-20-20-24 is a bit conflicting but can work out , it's just a bit harsh . You may need 60-20-20-20, but you'll figure it out

SOC beyond 1.1v here has bad effects and increases procODT requirements.
Up till 1.15v is usually the range after when negative scaling begins
But i want to remind, that 1900 FCLK on Matisse was hard and it still suffered from bad signal integrity ranges
Soo lower procODT = higher FCLK (1900 lock, but 1900 didn't run on every CPU)
Focus on that 28ohm range, and stay at 900mV cLDO_VDDP
950mV is not fine with 28ohm proc, same as beyond 1.1v is not fine with it.
1900 FCLK bruteforce settings are 32ohm proc, 950-1050-1100-1150 (cLDO_VDDP, VDDG CCD , VDDG IOD, VSOC [GET])
* stepping on Matisse was 50mV on stock or 75mV on extreme bruteforce settings
More about it here:
Buttom part of the message
AMDs minimum limits are 42-43mV (ty The Stilt) , but you want to have at least 48mV difference between the GET settings between VDDP, VDDG and VSOC
@RonLazer you did it! Of cuurse I need to run more test, but the big issue I guess was the TWR to slow. Reading Veii's post for last year I found that tWR is 8ns and to calculate it we should use freq * 8/2000, so 3800*8/2000 is 15.2 but should be an even number. so 16 did the work. And tRFC / tWR, 252/16 is 15.75ns.
I have a bit of an issue with anytype of "fixed real world timed" values
There was a ruleset out there spreading on the Intel MemOC thread, about tWR being a 8ns value as absolute minimum
This can not work. Memory is logarithmic and works on integers
No real world timed value is correct - as it scales up and down depending on set MCLK and the Command Rate state (PowerDown and GDM rounding included)

This is not optimal, and i strongly try to skip math that considers any type of fixed ns value. This can not work and won't work.
Rounding decimal numbers is also not optimal, same as focusing on fixed ns tRFC value is strongly not considerable
Been through this, and one of the reasons that tRFC mini module exists

Technically tRAS + XYZ (4,8) or tRC+1,2,4,8
used as integer values of tRC as a whole (half cycle, 1/8th of a cycle and so on) - was an option for stability and matching up things.
But it's also not optimal to do math that way
No XYZ + fixed ns value , is optimal
It works when you use added "memory timing" value, as it will turn at the end still to a .xxxxxxx (11 decimals) value
But if we speak about ns math, that's not a good method
Every little rounding stacks ~ beginning with board manufactures and IMC firmware developer rounding 3733.33333333337 MT/s, values
The math breaks, the more you round and tRFC 2 and 4 do fully break if you do it with the /1.346 & /2.1875 math
* reason why tRFC mini module exists, against Yuri's DRAM Calculator method, it always got tRFC2 & 4 wrong but it wasn't his fault but the user who inputs the wrong ns value
Even the windows calculator doesn't function beyond 11 decimals, while google docs ends at 13 decimals

I need to sit with you and write a book about everything that's wrong with how we scale MCLK and boards predict values
But trust me that a lot of thought went into "tRFC Mini" , and the way that it functions at version v2.31. It had undergone many revisions since v0.1 & yet is not perfect, because i can not generate tSTAG out of thin air, to match it better & have no statistic range for temperature to ns delay failure.

We'll talk someday about the reason i abandoned fully anything JEDEC related.
Because this holy book did not follow reality
A fantastic description was this post by an older dram engineer
137,438,953,472 memory cells won't always follow perfect tRC (tRAS+tRP) math, it's not possible to follow it blindly
But it's still a good indicator if the "transition" is "clean" or not, on a users set ~ or it needs work somewhere else, as tRC added delay does mask issues :)
* need to answer Ron too, but it requires another big wall of text, soo someday later
What do you think about running ClkDrvStr at 120 Ohm?
Not such a good idea
I mean it runs, but this combined with high voltage beyond 1.6 - i don't know what to think about it

Like mentioned a bit further up on the post,
AMD did something to their IMC firmware since 1201 and 1202.
I move between RTT_PARK /7 and /Disabled right now ~ instead of 6/3/6
But still face issues. They 100% did something with RZQ , but i can not achieve stability yet
Soo i can not say much more right now. I think some hidden CBS value changed, considering over 5% IPC bump & if i load my old profiles - it disables 4 of my USB 3.0 ports
Also considering something adds 0.5ns to it (L3 cache stayed the same no change there, but Geekbench reports 5-23% improvement ~ single and multi)

Overall if you use high ClkDrvStr
Lower RTT_PARK and RTT_NOM,
CKE high & CKE low will move differently and be more bursty
Any impedance value acts as a current multiplier , even if it's used as termination impedance (acts as resistance)

VDIMM, ClkDrvStr, procODT, and RTT_PARK go hand in hand
They need balancing
tCKE and SETUP timings are just control options, but i couldn't find something usable at 4200MT/s yet. It doesn't work well with DynamicODT (RTT_WR)
But tCKE does still work well, soo that's a plus point :)
I managed to run my DR kit at 1T without setup timings.
Only using this crazy high ClkDrvStr; but the RTT and ProcODT is very mild.
Dual Rank dimms can run 60-120, that's fine
but it's not soo fine for 8gb single rank :)
 

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Overclock the World
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Hi , I would like to know if any of you are using any High Performance Plan by BIOS. I´m actually using SMU 56.45 and I want to lower some version to try above 4000 Freq without WHEAs. I read from Veii that Patch B, not C, would perform well abobe 4000 Freq. Some time ago I read a post from 1Usmus that recommended certain parameters in the BIOS and since I am optimizing my memory overclocking I would like to know if any of these parameters could help or perhaps thet are complicating my OC . Among them I had set these options:

  1. Global C-state Control = Enabled (Advanced\AMD CBS). I set ti to disable to prevent Reboots under idle. However I was reading that rising IOD Voltage above 1.05V would prevent reboots. Is that right?
  2. DF CStates = Disabled (Advanced\AMD CBS\NBIO Common Options\SMU Common Options\DF Cstates = Disabled)
    This setting does not allow for Infinity Fabric to go to a low-power state when the processor has entered Cx states..
  3. PPC Adjustment = PState 0. Two settings below:
    (Advanced\AMD CBS\NBIO Common Options\SMU Common Options\APBDIS = 1
    AND

    (Advanced\AMD CBS\NBIO Common Options\SMU Common Options\Fixed SOC Pstate = P0)
Please don't take it as rude, if i give a bit of critique too this writeup :)
All 3 options are strange and first two misunderstood

Global C-States, does allow the per-core c-states to function and dLDO to function (speedstep , nothing to do with suspended cores)
This means, it allows the cpu to go down to 550Mhz P3/P4 state
This is important to have it enabled.
In combination with CPPC , it allows windows to lower frequency on worse cores and accept dLDO_injector , to smooth the voltage differentiation between cores ~ where each of the little core modules

Credits for the shot to Fritzchen's Fritz AMD/Zen3/Ryzen/Vermeer | Flickr
It needs to be enabled, soo cores can adjust and Vermeer can adjust inside the powerbudget

DF-States are controlling the suspension and also the wake-up from hibernation , triggers the overboosting bug , which causes an "idle to wake-up" crash by badly designed powerplans from AMD & Microsoft, without Peak frequency boosts
This has to be disabled till it get's fixed on 1202 or 1202ABCD :p
* i need to test if it's still an issue on 1202 , after figuring out what the hello kitty is wrong with RZQ and why IMC behaviour is now completely exotic and wrong/broken
~ after the PMTable rewrite & 3 new activated sensors inside FIT

2489039

Whole Source
PPC Adjustment = PState 0. Two settings below:
(Advanced\AMD CBS\NBIO Common Options\SMU Common Options\APBDIS = 1
AND

(Advanced\AMD CBS\NBIO Common Options\SMU Common Options\Fixed SOC Pstate = P0)
This is what you described as Infinity Fabric Scaling "disabled"
It's on FW level disabled & does nothing from the surface viewpoint (maybe does something internally if you keep it functioning at misson-mode = 0)
and if you ask any engineer about Dynamic FCLK and variable SOC - they will cut the contact with you
I think this topic is under NDA , 4 engineers refused to answer and cut the chat after asking more about ABPDIS and why Dynamic FCLK is disabled internally


You can keep it at 0 mission mode
it won't function except for Renoir & Cezanne, which have STAMP control and are build upon this. Same for ryzen U & G series notebooks ~ there it functions
For Matisse and Vermeer it's disabled since mid of the lifespan of Matisse & Matisse has an 1900 FCLK lock - like Vermeer was attempted to get after Patch C, gladly this nonsense was stopped after Patch D
Then DPM LCLK to 2-1-1-1-2-1-1-1
Before 1200 , soo 1191/1181 and lower, you can run this
1202 seems to set internally X-X-X-2-X-X-X-2
SMU debug shows on 1200 and lower that 2-1-X-X-2-1-X-X is used
One 600mhz link with one 300mhz one. Level 2 and Level 3 where not readable , but 2-2-1 was not accepted by SMU
Currently i test 2-1-1-2/2-1-1-2, as Level3/4 (the last link) is set at 600mhz and used (by FW alone, i had them at auto)
probably 2-1-1-2 could be good, but we'll see, test in progress AGESA 1.2.0.2 is awkward & did a lot of changes

The rest is fine
You can include opening PBO EDC to 400A
It still allows cache to boost till it gets internally limited
and should be reflective on SiSandra MCE , as also on Aida64
But lifting the EDC limit will need a limit on TDC , else it adds to much voltage for allcore and the CPU throttles back
This can be fixed by nearly maxed out negative CO with "lower" but positive vcore offset or just more droopy CPU LLC
 

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View attachment 2489013

View attachment 2489011

Code:
SiSoftware Sandra

Benchmark Results
Aggregate Inter-Thread Bandwidth : 176GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Average Inter-Thread Latency : 39.9ns (9.5ns - 61.4ns)
Inter-Thread (same Core) Latency : 9.8ns
Inter-Core (same Module) Latency : 21.0ns
Inter-Module (same Package) Latency : 58.4ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 5.5GB/s
No. Threads : 32
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 105.00W
Aggregate Inter-Thread Bandwidth : 1716.17MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 3.80ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 707.05kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 36.22MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 0.08ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
U0-M0C0T0 <> U2-M0C1T0 Data Latency : 22.2ns
U0-M0C0T0 <> U4-M0C2T0 Data Latency : 19.6ns
U0-M0C0T0 <> U6-M0C3T0 Data Latency : 20.1ns
U0-M0C0T0 <> U8-M0C4T0 Data Latency : 19.9ns
U0-M0C0T0 <> U10-M0C5T0 Data Latency : 20.4ns
U0-M0C0T0 <> U12-M0C6T0 Data Latency : 20.8ns
U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.5ns
U0-M0C0T0 <> U16-M1C0T0 Data Latency : 56.9ns
U0-M0C0T0 <> U18-M1C1T0 Data Latency : 56.6ns
U0-M0C0T0 <> U20-M1C2T0 Data Latency : 56.9ns
U0-M0C0T0 <> U22-M1C3T0 Data Latency : 57.3ns
U0-M0C0T0 <> U24-M1C4T0 Data Latency : 58.0ns
U0-M0C0T0 <> U26-M1C5T0 Data Latency : 57.5ns
U0-M0C0T0 <> U28-M1C6T0 Data Latency : 58.1ns
U0-M0C0T0 <> U30-M1C7T0 Data Latency : 58.1ns
U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.6ns
U0-M0C0T0 <> U3-M0C1T1 Data Latency : 19.5ns
U0-M0C0T0 <> U5-M0C2T1 Data Latency : 19.5ns
U0-M0C0T0 <> U7-M0C3T1 Data Latency : 20.0ns
U0-M0C0T0 <> U9-M0C4T1 Data Latency : 19.8ns
U0-M0C0T0 <> U11-M0C5T1 Data Latency : 20.5ns
U0-M0C0T0 <> U13-M0C6T1 Data Latency : 20.8ns
U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.5ns
U0-M0C0T0 <> U17-M1C0T1 Data Latency : 56.9ns
U0-M0C0T0 <> U19-M1C1T1 Data Latency : 56.4ns
U0-M0C0T0 <> U21-M1C2T1 Data Latency : 56.9ns
U0-M0C0T0 <> U23-M1C3T1 Data Latency : 57.3ns
U0-M0C0T0 <> U25-M1C4T1 Data Latency : 58.0ns
U0-M0C0T0 <> U27-M1C5T1 Data Latency : 57.5ns
U0-M0C0T0 <> U29-M1C6T1 Data Latency : 58.1ns
U0-M0C0T0 <> U31-M1C7T1 Data Latency : 58.1ns
U2-M0C1T0 <> U4-M0C2T0 Data Latency : 19.2ns
U2-M0C1T0 <> U6-M0C3T0 Data Latency : 20.8ns
U2-M0C1T0 <> U8-M0C4T0 Data Latency : 19.7ns
U2-M0C1T0 <> U10-M0C5T0 Data Latency : 21.4ns
U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.5ns
U2-M0C1T0 <> U14-M0C7T0 Data Latency : 21.0ns
U2-M0C1T0 <> U16-M1C0T0 Data Latency : 56.8ns
U2-M0C1T0 <> U18-M1C1T0 Data Latency : 57.0ns
U2-M0C1T0 <> U20-M1C2T0 Data Latency : 57.1ns
U2-M0C1T0 <> U22-M1C3T0 Data Latency : 60.9ns
U2-M0C1T0 <> U24-M1C4T0 Data Latency : 61.0ns
U2-M0C1T0 <> U26-M1C5T0 Data Latency : 60.8ns
U2-M0C1T0 <> U28-M1C6T0 Data Latency : 60.5ns
U2-M0C1T0 <> U30-M1C7T0 Data Latency : 60.3ns
U2-M0C1T0 <> U1-M0C0T1 Data Latency : 22.2ns
U2-M0C1T0 <> U3-M0C1T1 Data Latency : 10.0ns
U2-M0C1T0 <> U5-M0C2T1 Data Latency : 21.9ns
U2-M0C1T0 <> U7-M0C3T1 Data Latency : 23.0ns
U2-M0C1T0 <> U9-M0C4T1 Data Latency : 21.1ns
U2-M0C1T0 <> U11-M0C5T1 Data Latency : 22.3ns
U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.6ns
U2-M0C1T0 <> U15-M0C7T1 Data Latency : 21.8ns
U2-M0C1T0 <> U17-M1C0T1 Data Latency : 61.4ns
U2-M0C1T0 <> U19-M1C1T1 Data Latency : 61.1ns
U2-M0C1T0 <> U21-M1C2T1 Data Latency : 61.2ns
U2-M0C1T0 <> U23-M1C3T1 Data Latency : 60.9ns
U2-M0C1T0 <> U25-M1C4T1 Data Latency : 61.1ns
U2-M0C1T0 <> U27-M1C5T1 Data Latency : 60.8ns
U2-M0C1T0 <> U29-M1C6T1 Data Latency : 60.5ns
U2-M0C1T0 <> U31-M1C7T1 Data Latency : 60.3ns
U4-M0C2T0 <> U6-M0C3T0 Data Latency : 21.3ns
U4-M0C2T0 <> U8-M0C4T0 Data Latency : 20.6ns
U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.5ns
U4-M0C2T0 <> U12-M0C6T0 Data Latency : 19.9ns
U4-M0C2T0 <> U14-M0C7T0 Data Latency : 19.8ns
U4-M0C2T0 <> U16-M1C0T0 Data Latency : 60.3ns
U4-M0C2T0 <> U18-M1C1T0 Data Latency : 60.7ns
U4-M0C2T0 <> U20-M1C2T0 Data Latency : 60.2ns
U4-M0C2T0 <> U22-M1C3T0 Data Latency : 60.6ns
U4-M0C2T0 <> U24-M1C4T0 Data Latency : 59.7ns
U4-M0C2T0 <> U26-M1C5T0 Data Latency : 60.4ns
U4-M0C2T0 <> U28-M1C6T0 Data Latency : 59.6ns
U4-M0C2T0 <> U30-M1C7T0 Data Latency : 60.0ns
U4-M0C2T0 <> U1-M0C0T1 Data Latency : 22.0ns
U4-M0C2T0 <> U3-M0C1T1 Data Latency : 22.2ns
U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.8ns
U4-M0C2T0 <> U7-M0C3T1 Data Latency : 21.2ns
U4-M0C2T0 <> U9-M0C4T1 Data Latency : 20.6ns
U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.5ns
U4-M0C2T0 <> U13-M0C6T1 Data Latency : 19.9ns
U4-M0C2T0 <> U15-M0C7T1 Data Latency : 19.8ns
U4-M0C2T0 <> U17-M1C0T1 Data Latency : 60.4ns
U4-M0C2T0 <> U19-M1C1T1 Data Latency : 60.8ns
U4-M0C2T0 <> U21-M1C2T1 Data Latency : 60.1ns
U4-M0C2T0 <> U23-M1C3T1 Data Latency : 60.5ns
U4-M0C2T0 <> U25-M1C4T1 Data Latency : 59.7ns
U4-M0C2T0 <> U27-M1C5T1 Data Latency : 60.4ns
U4-M0C2T0 <> U29-M1C6T1 Data Latency : 59.6ns
U4-M0C2T0 <> U31-M1C7T1 Data Latency : 60.1ns
U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.6ns
U6-M0C3T0 <> U10-M0C5T0 Data Latency : 21.7ns
U6-M0C3T0 <> U12-M0C6T0 Data Latency : 19.9ns
U6-M0C3T0 <> U14-M0C7T0 Data Latency : 21.1ns
U6-M0C3T0 <> U16-M1C0T0 Data Latency : 61.1ns
U6-M0C3T0 <> U18-M1C1T0 Data Latency : 60.9ns
U6-M0C3T0 <> U20-M1C2T0 Data Latency : 60.9ns
U6-M0C3T0 <> U22-M1C3T0 Data Latency : 60.4ns
U6-M0C3T0 <> U24-M1C4T0 Data Latency : 60.4ns
U6-M0C3T0 <> U26-M1C5T0 Data Latency : 60.5ns
U6-M0C3T0 <> U28-M1C6T0 Data Latency : 60.2ns
U6-M0C3T0 <> U30-M1C7T0 Data Latency : 60.1ns
U6-M0C3T0 <> U1-M0C0T1 Data Latency : 21.9ns
U6-M0C3T0 <> U3-M0C1T1 Data Latency : 23.2ns
U6-M0C3T0 <> U5-M0C2T1 Data Latency : 21.4ns
U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.9ns
U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.7ns
U6-M0C3T0 <> U11-M0C5T1 Data Latency : 21.7ns
U6-M0C3T0 <> U13-M0C6T1 Data Latency : 19.9ns
U6-M0C3T0 <> U15-M0C7T1 Data Latency : 21.2ns
U6-M0C3T0 <> U17-M1C0T1 Data Latency : 57.0ns
U6-M0C3T0 <> U19-M1C1T1 Data Latency : 57.0ns
U6-M0C3T0 <> U21-M1C2T1 Data Latency : 57.3ns
U6-M0C3T0 <> U23-M1C3T1 Data Latency : 57.5ns
U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.0ns
U6-M0C3T0 <> U27-M1C5T1 Data Latency : 58.2ns
U6-M0C3T0 <> U29-M1C6T1 Data Latency : 58.6ns
U6-M0C3T0 <> U31-M1C7T1 Data Latency : 58.3ns
U8-M0C4T0 <> U10-M0C5T0 Data Latency : 21.0ns
U8-M0C4T0 <> U12-M0C6T0 Data Latency : 22.8ns
U8-M0C4T0 <> U14-M0C7T0 Data Latency : 21.7ns
U8-M0C4T0 <> U16-M1C0T0 Data Latency : 57.7ns
U8-M0C4T0 <> U18-M1C1T0 Data Latency : 57.2ns
U8-M0C4T0 <> U20-M1C2T0 Data Latency : 58.0ns
U8-M0C4T0 <> U22-M1C3T0 Data Latency : 57.8ns
U8-M0C4T0 <> U24-M1C4T0 Data Latency : 58.6ns
U8-M0C4T0 <> U26-M1C5T0 Data Latency : 58.4ns
U8-M0C4T0 <> U28-M1C6T0 Data Latency : 58.9ns
U8-M0C4T0 <> U30-M1C7T0 Data Latency : 58.8ns
U8-M0C4T0 <> U1-M0C0T1 Data Latency : 20.7ns
U8-M0C4T0 <> U3-M0C1T1 Data Latency : 19.9ns
U8-M0C4T0 <> U5-M0C2T1 Data Latency : 21.8ns
U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.5ns
U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.5ns
U8-M0C4T0 <> U11-M0C5T1 Data Latency : 21.0ns
U8-M0C4T0 <> U13-M0C6T1 Data Latency : 22.9ns
U8-M0C4T0 <> U15-M0C7T1 Data Latency : 21.7ns
U8-M0C4T0 <> U17-M1C0T1 Data Latency : 57.7ns
U8-M0C4T0 <> U19-M1C1T1 Data Latency : 57.2ns
U8-M0C4T0 <> U21-M1C2T1 Data Latency : 57.9ns
U8-M0C4T0 <> U23-M1C3T1 Data Latency : 57.8ns
U8-M0C4T0 <> U25-M1C4T1 Data Latency : 58.6ns
U8-M0C4T0 <> U27-M1C5T1 Data Latency : 58.4ns
U8-M0C4T0 <> U29-M1C6T1 Data Latency : 58.8ns
U8-M0C4T0 <> U31-M1C7T1 Data Latency : 58.7ns
U10-M0C5T0 <> U12-M0C6T0 Data Latency : 21.7ns
U10-M0C5T0 <> U14-M0C7T0 Data Latency : 21.7ns
U10-M0C5T0 <> U16-M1C0T0 Data Latency : 57.4ns
U10-M0C5T0 <> U18-M1C1T0 Data Latency : 57.1ns
U10-M0C5T0 <> U20-M1C2T0 Data Latency : 57.6ns
U10-M0C5T0 <> U22-M1C3T0 Data Latency : 57.8ns
U10-M0C5T0 <> U24-M1C4T0 Data Latency : 58.4ns
U10-M0C5T0 <> U26-M1C5T0 Data Latency : 58.3ns
U10-M0C5T0 <> U28-M1C6T0 Data Latency : 58.9ns
U10-M0C5T0 <> U30-M1C7T0 Data Latency : 58.2ns
U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.3ns
U10-M0C5T0 <> U3-M0C1T1 Data Latency : 20.9ns
U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.5ns
U10-M0C5T0 <> U7-M0C3T1 Data Latency : 21.5ns
U10-M0C5T0 <> U9-M0C4T1 Data Latency : 20.9ns
U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.8ns
U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.7ns
U10-M0C5T0 <> U15-M0C7T1 Data Latency : 21.7ns
U10-M0C5T0 <> U17-M1C0T1 Data Latency : 57.4ns
U10-M0C5T0 <> U19-M1C1T1 Data Latency : 57.2ns
U10-M0C5T0 <> U21-M1C2T1 Data Latency : 57.6ns
U10-M0C5T0 <> U23-M1C3T1 Data Latency : 57.6ns
U10-M0C5T0 <> U25-M1C4T1 Data Latency : 58.4ns
U10-M0C5T0 <> U27-M1C5T1 Data Latency : 58.3ns
U10-M0C5T0 <> U29-M1C6T1 Data Latency : 58.8ns
U10-M0C5T0 <> U31-M1C7T1 Data Latency : 58.3ns
U12-M0C6T0 <> U14-M0C7T0 Data Latency : 22.4ns
U12-M0C6T0 <> U16-M1C0T0 Data Latency : 58.4ns
U12-M0C6T0 <> U18-M1C1T0 Data Latency : 57.8ns
U12-M0C6T0 <> U20-M1C2T0 Data Latency : 58.5ns
U12-M0C6T0 <> U22-M1C3T0 Data Latency : 58.7ns
U12-M0C6T0 <> U24-M1C4T0 Data Latency : 59.1ns
U12-M0C6T0 <> U26-M1C5T0 Data Latency : 59.0ns
U12-M0C6T0 <> U28-M1C6T0 Data Latency : 59.7ns
U12-M0C6T0 <> U30-M1C7T0 Data Latency : 59.8ns
U12-M0C6T0 <> U1-M0C0T1 Data Latency : 21.6ns
U12-M0C6T0 <> U3-M0C1T1 Data Latency : 20.7ns
U12-M0C6T0 <> U5-M0C2T1 Data Latency : 22.4ns
U12-M0C6T0 <> U7-M0C3T1 Data Latency : 21.3ns
U12-M0C6T0 <> U9-M0C4T1 Data Latency : 22.9ns
U12-M0C6T0 <> U11-M0C5T1 Data Latency : 21.8ns
U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.9ns
U12-M0C6T0 <> U15-M0C7T1 Data Latency : 22.5ns
U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.4ns
U12-M0C6T0 <> U19-M1C1T1 Data Latency : 58.0ns
U12-M0C6T0 <> U21-M1C2T1 Data Latency : 58.5ns
U12-M0C6T0 <> U23-M1C3T1 Data Latency : 58.6ns
U12-M0C6T0 <> U25-M1C4T1 Data Latency : 59.1ns
U12-M0C6T0 <> U27-M1C5T1 Data Latency : 59.0ns
U12-M0C6T0 <> U29-M1C6T1 Data Latency : 59.7ns
U12-M0C6T0 <> U31-M1C7T1 Data Latency : 59.7ns
U14-M0C7T0 <> U16-M1C0T0 Data Latency : 58.0ns
U14-M0C7T0 <> U18-M1C1T0 Data Latency : 57.6ns
U14-M0C7T0 <> U20-M1C2T0 Data Latency : 58.1ns
U14-M0C7T0 <> U22-M1C3T0 Data Latency : 58.1ns
U14-M0C7T0 <> U24-M1C4T0 Data Latency : 59.1ns
U14-M0C7T0 <> U26-M1C5T0 Data Latency : 58.5ns
U14-M0C7T0 <> U28-M1C6T0 Data Latency : 59.6ns
U14-M0C7T0 <> U30-M1C7T0 Data Latency : 59.1ns
U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.6ns
U14-M0C7T0 <> U3-M0C1T1 Data Latency : 20.8ns
U14-M0C7T0 <> U5-M0C2T1 Data Latency : 21.3ns
U14-M0C7T0 <> U7-M0C3T1 Data Latency : 21.4ns
U14-M0C7T0 <> U9-M0C4T1 Data Latency : 21.7ns
U14-M0C7T0 <> U11-M0C5T1 Data Latency : 21.9ns
U14-M0C7T0 <> U13-M0C6T1 Data Latency : 22.3ns
U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.8ns
U14-M0C7T0 <> U17-M1C0T1 Data Latency : 57.9ns
U14-M0C7T0 <> U19-M1C1T1 Data Latency : 57.5ns
U14-M0C7T0 <> U21-M1C2T1 Data Latency : 58.1ns
U14-M0C7T0 <> U23-M1C3T1 Data Latency : 58.2ns
U14-M0C7T0 <> U25-M1C4T1 Data Latency : 59.0ns
U14-M0C7T0 <> U27-M1C5T1 Data Latency : 58.5ns
U14-M0C7T0 <> U29-M1C6T1 Data Latency : 59.5ns
U14-M0C7T0 <> U31-M1C7T1 Data Latency : 59.1ns
U16-M1C0T0 <> U18-M1C1T0 Data Latency : 19.2ns
U16-M1C0T0 <> U20-M1C2T0 Data Latency : 20.0ns
U16-M1C0T0 <> U22-M1C3T0 Data Latency : 19.7ns
U16-M1C0T0 <> U24-M1C4T0 Data Latency : 20.9ns
U16-M1C0T0 <> U26-M1C5T0 Data Latency : 20.3ns
U16-M1C0T0 <> U28-M1C6T0 Data Latency : 21.5ns
U16-M1C0T0 <> U30-M1C7T0 Data Latency : 20.5ns
U16-M1C0T0 <> U1-M0C0T1 Data Latency : 57.1ns
U16-M1C0T0 <> U3-M0C1T1 Data Latency : 56.9ns
U16-M1C0T0 <> U5-M0C2T1 Data Latency : 57.0ns
U16-M1C0T0 <> U7-M0C3T1 Data Latency : 57.4ns
U16-M1C0T0 <> U9-M0C4T1 Data Latency : 57.6ns
U16-M1C0T0 <> U11-M0C5T1 Data Latency : 57.6ns
U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.2ns
U16-M1C0T0 <> U15-M0C7T1 Data Latency : 58.0ns
U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.8ns
U16-M1C0T0 <> U19-M1C1T1 Data Latency : 19.2ns
U16-M1C0T0 <> U21-M1C2T1 Data Latency : 20.1ns
U16-M1C0T0 <> U23-M1C3T1 Data Latency : 19.7ns
U16-M1C0T0 <> U25-M1C4T1 Data Latency : 20.9ns
U16-M1C0T0 <> U27-M1C5T1 Data Latency : 20.3ns
U16-M1C0T0 <> U29-M1C6T1 Data Latency : 21.5ns
U16-M1C0T0 <> U31-M1C7T1 Data Latency : 20.5ns
U18-M1C1T0 <> U20-M1C2T0 Data Latency : 18.9ns
U18-M1C1T0 <> U22-M1C3T0 Data Latency : 19.9ns
U18-M1C1T0 <> U24-M1C4T0 Data Latency : 19.7ns
U18-M1C1T0 <> U26-M1C5T0 Data Latency : 20.5ns
U18-M1C1T0 <> U28-M1C6T0 Data Latency : 20.5ns
U18-M1C1T0 <> U30-M1C7T0 Data Latency : 20.4ns
U18-M1C1T0 <> U1-M0C0T1 Data Latency : 56.1ns
U18-M1C1T0 <> U3-M0C1T1 Data Latency : 56.8ns
U18-M1C1T0 <> U5-M0C2T1 Data Latency : 56.9ns
U18-M1C1T0 <> U7-M0C3T1 Data Latency : 57.1ns
U18-M1C1T0 <> U9-M0C4T1 Data Latency : 57.0ns
U18-M1C1T0 <> U11-M0C5T1 Data Latency : 57.1ns
U18-M1C1T0 <> U13-M0C6T1 Data Latency : 57.7ns
U18-M1C1T0 <> U15-M0C7T1 Data Latency : 57.3ns
U18-M1C1T0 <> U17-M1C0T1 Data Latency : 19.2ns
U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.8ns
U18-M1C1T0 <> U21-M1C2T1 Data Latency : 18.9ns
U18-M1C1T0 <> U23-M1C3T1 Data Latency : 19.9ns
U18-M1C1T0 <> U25-M1C4T1 Data Latency : 19.7ns
U18-M1C1T0 <> U27-M1C5T1 Data Latency : 20.5ns
U18-M1C1T0 <> U29-M1C6T1 Data Latency : 20.4ns
U18-M1C1T0 <> U31-M1C7T1 Data Latency : 20.4ns
U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.6ns
U20-M1C2T0 <> U24-M1C4T0 Data Latency : 21.6ns
U20-M1C2T0 <> U26-M1C5T0 Data Latency : 20.4ns
U20-M1C2T0 <> U28-M1C6T0 Data Latency : 22.0ns
U20-M1C2T0 <> U30-M1C7T0 Data Latency : 21.1ns
U20-M1C2T0 <> U1-M0C0T1 Data Latency : 57.1ns
U20-M1C2T0 <> U3-M0C1T1 Data Latency : 57.7ns
U20-M1C2T0 <> U5-M0C2T1 Data Latency : 57.4ns
U20-M1C2T0 <> U7-M0C3T1 Data Latency : 57.6ns
U20-M1C2T0 <> U9-M0C4T1 Data Latency : 57.7ns
U20-M1C2T0 <> U11-M0C5T1 Data Latency : 58.2ns
U20-M1C2T0 <> U13-M0C6T1 Data Latency : 58.3ns
U20-M1C2T0 <> U15-M0C7T1 Data Latency : 58.2ns
U20-M1C2T0 <> U17-M1C0T1 Data Latency : 20.1ns
U20-M1C2T0 <> U19-M1C1T1 Data Latency : 19.0ns
U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.8ns
U20-M1C2T0 <> U23-M1C3T1 Data Latency : 19.5ns
U20-M1C2T0 <> U25-M1C4T1 Data Latency : 21.6ns
U20-M1C2T0 <> U27-M1C5T1 Data Latency : 20.4ns
U20-M1C2T0 <> U29-M1C6T1 Data Latency : 22.0ns
U20-M1C2T0 <> U31-M1C7T1 Data Latency : 21.1ns
U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.4ns
U22-M1C3T0 <> U26-M1C5T0 Data Latency : 21.3ns
U22-M1C3T0 <> U28-M1C6T0 Data Latency : 21.0ns
U22-M1C3T0 <> U30-M1C7T0 Data Latency : 20.9ns
U22-M1C3T0 <> U1-M0C0T1 Data Latency : 57.0ns
U22-M1C3T0 <> U3-M0C1T1 Data Latency : 57.7ns
U22-M1C3T0 <> U5-M0C2T1 Data Latency : 57.4ns
U22-M1C3T0 <> U7-M0C3T1 Data Latency : 57.7ns
U22-M1C3T0 <> U9-M0C4T1 Data Latency : 57.6ns
U22-M1C3T0 <> U11-M0C5T1 Data Latency : 57.9ns
U22-M1C3T0 <> U13-M0C6T1 Data Latency : 58.3ns
U22-M1C3T0 <> U15-M0C7T1 Data Latency : 58.1ns
U22-M1C3T0 <> U17-M1C0T1 Data Latency : 19.6ns
U22-M1C3T0 <> U19-M1C1T1 Data Latency : 20.0ns
U22-M1C3T0 <> U21-M1C2T1 Data Latency : 19.4ns
U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.8ns
U22-M1C3T0 <> U25-M1C4T1 Data Latency : 20.4ns
U22-M1C3T0 <> U27-M1C5T1 Data Latency : 21.3ns
U22-M1C3T0 <> U29-M1C6T1 Data Latency : 21.0ns
U22-M1C3T0 <> U31-M1C7T1 Data Latency : 20.9ns
U24-M1C4T0 <> U26-M1C5T0 Data Latency : 21.2ns
U24-M1C4T0 <> U28-M1C6T0 Data Latency : 22.9ns
U24-M1C4T0 <> U30-M1C7T0 Data Latency : 21.9ns
U24-M1C4T0 <> U1-M0C0T1 Data Latency : 57.9ns
U24-M1C4T0 <> U3-M0C1T1 Data Latency : 58.3ns
U24-M1C4T0 <> U5-M0C2T1 Data Latency : 58.1ns
U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.3ns
U24-M1C4T0 <> U9-M0C4T1 Data Latency : 58.7ns
U24-M1C4T0 <> U11-M0C5T1 Data Latency : 58.9ns
U24-M1C4T0 <> U13-M0C6T1 Data Latency : 59.3ns
U24-M1C4T0 <> U15-M0C7T1 Data Latency : 59.1ns
U24-M1C4T0 <> U17-M1C0T1 Data Latency : 21.1ns
U24-M1C4T0 <> U19-M1C1T1 Data Latency : 19.8ns
U24-M1C4T0 <> U21-M1C2T1 Data Latency : 21.7ns
U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.5ns
U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.9ns
U24-M1C4T0 <> U27-M1C5T1 Data Latency : 21.3ns
U24-M1C4T0 <> U29-M1C6T1 Data Latency : 22.9ns
U24-M1C4T0 <> U31-M1C7T1 Data Latency : 21.9ns
U26-M1C5T0 <> U28-M1C6T0 Data Latency : 21.6ns
U26-M1C5T0 <> U30-M1C7T0 Data Latency : 21.7ns
U26-M1C5T0 <> U1-M0C0T1 Data Latency : 57.4ns
U26-M1C5T0 <> U3-M0C1T1 Data Latency : 58.2ns
U26-M1C5T0 <> U5-M0C2T1 Data Latency : 57.9ns
U26-M1C5T0 <> U7-M0C3T1 Data Latency : 58.2ns
U26-M1C5T0 <> U9-M0C4T1 Data Latency : 58.2ns
U26-M1C5T0 <> U11-M0C5T1 Data Latency : 58.3ns
U26-M1C5T0 <> U13-M0C6T1 Data Latency : 58.9ns
U26-M1C5T0 <> U15-M0C7T1 Data Latency : 58.7ns
U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.3ns
U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.6ns
U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.2ns
U26-M1C5T0 <> U23-M1C3T1 Data Latency : 21.3ns
U26-M1C5T0 <> U25-M1C4T1 Data Latency : 21.1ns
U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.8ns
U26-M1C5T0 <> U29-M1C6T1 Data Latency : 21.6ns
U26-M1C5T0 <> U31-M1C7T1 Data Latency : 21.7ns
U28-M1C6T0 <> U30-M1C7T0 Data Latency : 22.3ns
U28-M1C6T0 <> U1-M0C0T1 Data Latency : 58.4ns
U28-M1C6T0 <> U3-M0C1T1 Data Latency : 58.7ns
U28-M1C6T0 <> U5-M0C2T1 Data Latency : 58.8ns
U28-M1C6T0 <> U7-M0C3T1 Data Latency : 59.1ns
U28-M1C6T0 <> U9-M0C4T1 Data Latency : 58.9ns
U28-M1C6T0 <> U11-M0C5T1 Data Latency : 59.2ns
U28-M1C6T0 <> U13-M0C6T1 Data Latency : 59.6ns
U28-M1C6T0 <> U15-M0C7T1 Data Latency : 59.5ns
U28-M1C6T0 <> U17-M1C0T1 Data Latency : 21.6ns
U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.4ns
U28-M1C6T0 <> U21-M1C2T1 Data Latency : 22.2ns
U28-M1C6T0 <> U23-M1C3T1 Data Latency : 21.1ns
U28-M1C6T0 <> U25-M1C4T1 Data Latency : 23.0ns
U28-M1C6T0 <> U27-M1C5T1 Data Latency : 21.7ns
U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.8ns
U28-M1C6T0 <> U31-M1C7T1 Data Latency : 22.3ns
U30-M1C7T0 <> U1-M0C0T1 Data Latency : 58.0ns
U30-M1C7T0 <> U3-M0C1T1 Data Latency : 58.4ns
U30-M1C7T0 <> U5-M0C2T1 Data Latency : 58.4ns
U30-M1C7T0 <> U7-M0C3T1 Data Latency : 58.8ns
U30-M1C7T0 <> U9-M0C4T1 Data Latency : 58.7ns
U30-M1C7T0 <> U11-M0C5T1 Data Latency : 58.6ns
U30-M1C7T0 <> U13-M0C6T1 Data Latency : 59.5ns
U30-M1C7T0 <> U15-M0C7T1 Data Latency : 59.2ns
U30-M1C7T0 <> U17-M1C0T1 Data Latency : 20.6ns
U30-M1C7T0 <> U19-M1C1T1 Data Latency : 20.6ns
U30-M1C7T0 <> U21-M1C2T1 Data Latency : 21.1ns
U30-M1C7T0 <> U23-M1C3T1 Data Latency : 21.2ns
U30-M1C7T0 <> U25-M1C4T1 Data Latency : 21.9ns
U30-M1C7T0 <> U27-M1C5T1 Data Latency : 22.0ns
U30-M1C7T0 <> U29-M1C6T1 Data Latency : 22.2ns
U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.8ns
U1-M0C0T1 <> U3-M0C1T1 Data Latency : 19.4ns
U1-M0C0T1 <> U5-M0C2T1 Data Latency : 20.2ns
U1-M0C0T1 <> U7-M0C3T1 Data Latency : 19.9ns
U1-M0C0T1 <> U9-M0C4T1 Data Latency : 20.6ns
U1-M0C0T1 <> U11-M0C5T1 Data Latency : 20.2ns
U1-M0C0T1 <> U13-M0C6T1 Data Latency : 21.5ns
U1-M0C0T1 <> U15-M0C7T1 Data Latency : 20.5ns
U1-M0C0T1 <> U17-M1C0T1 Data Latency : 56.9ns
U1-M0C0T1 <> U19-M1C1T1 Data Latency : 56.3ns
U1-M0C0T1 <> U21-M1C2T1 Data Latency : 57.0ns
U1-M0C0T1 <> U23-M1C3T1 Data Latency : 57.1ns
U1-M0C0T1 <> U25-M1C4T1 Data Latency : 57.9ns
U1-M0C0T1 <> U27-M1C5T1 Data Latency : 57.6ns
U1-M0C0T1 <> U29-M1C6T1 Data Latency : 58.3ns
U1-M0C0T1 <> U31-M1C7T1 Data Latency : 57.9ns
U3-M0C1T1 <> U5-M0C2T1 Data Latency : 19.4ns
U3-M0C1T1 <> U7-M0C3T1 Data Latency : 20.3ns
U3-M0C1T1 <> U9-M0C4T1 Data Latency : 19.9ns
U3-M0C1T1 <> U11-M0C5T1 Data Latency : 20.8ns
U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.8ns
U3-M0C1T1 <> U15-M0C7T1 Data Latency : 20.7ns
U3-M0C1T1 <> U17-M1C0T1 Data Latency : 57.0ns
U3-M0C1T1 <> U19-M1C1T1 Data Latency : 56.8ns
U3-M0C1T1 <> U21-M1C2T1 Data Latency : 57.2ns
U3-M0C1T1 <> U23-M1C3T1 Data Latency : 57.2ns
U3-M0C1T1 <> U25-M1C4T1 Data Latency : 57.8ns
U3-M0C1T1 <> U27-M1C5T1 Data Latency : 57.7ns
U3-M0C1T1 <> U29-M1C6T1 Data Latency : 58.7ns
U3-M0C1T1 <> U31-M1C7T1 Data Latency : 58.1ns
U5-M0C2T1 <> U7-M0C3T1 Data Latency : 19.8ns
U5-M0C2T1 <> U9-M0C4T1 Data Latency : 21.7ns
U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.6ns
U5-M0C2T1 <> U13-M0C6T1 Data Latency : 22.3ns
U5-M0C2T1 <> U15-M0C7T1 Data Latency : 21.3ns
U5-M0C2T1 <> U17-M1C0T1 Data Latency : 57.3ns
U5-M0C2T1 <> U19-M1C1T1 Data Latency : 57.2ns
U5-M0C2T1 <> U21-M1C2T1 Data Latency : 57.4ns
U5-M0C2T1 <> U23-M1C3T1 Data Latency : 57.7ns
U5-M0C2T1 <> U25-M1C4T1 Data Latency : 58.2ns
U5-M0C2T1 <> U27-M1C5T1 Data Latency : 58.3ns
U5-M0C2T1 <> U29-M1C6T1 Data Latency : 58.7ns
U5-M0C2T1 <> U31-M1C7T1 Data Latency : 58.6ns
U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.5ns
U7-M0C3T1 <> U11-M0C5T1 Data Latency : 21.6ns
U7-M0C3T1 <> U13-M0C6T1 Data Latency : 21.3ns
U7-M0C3T1 <> U15-M0C7T1 Data Latency : 21.2ns
U7-M0C3T1 <> U17-M1C0T1 Data Latency : 57.0ns
U7-M0C3T1 <> U19-M1C1T1 Data Latency : 57.1ns
U7-M0C3T1 <> U21-M1C2T1 Data Latency : 57.1ns
U7-M0C3T1 <> U23-M1C3T1 Data Latency : 57.5ns
U7-M0C3T1 <> U25-M1C4T1 Data Latency : 57.9ns
U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.1ns
U7-M0C3T1 <> U29-M1C6T1 Data Latency : 58.7ns
U7-M0C3T1 <> U31-M1C7T1 Data Latency : 58.2ns
U9-M0C4T1 <> U11-M0C5T1 Data Latency : 21.0ns
U9-M0C4T1 <> U13-M0C6T1 Data Latency : 22.9ns
U9-M0C4T1 <> U15-M0C7T1 Data Latency : 21.7ns
U9-M0C4T1 <> U17-M1C0T1 Data Latency : 57.7ns
U9-M0C4T1 <> U19-M1C1T1 Data Latency : 57.3ns
U9-M0C4T1 <> U21-M1C2T1 Data Latency : 58.0ns
U9-M0C4T1 <> U23-M1C3T1 Data Latency : 57.8ns
U9-M0C4T1 <> U25-M1C4T1 Data Latency : 58.6ns
U9-M0C4T1 <> U27-M1C5T1 Data Latency : 58.4ns
U9-M0C4T1 <> U29-M1C6T1 Data Latency : 58.9ns
U9-M0C4T1 <> U31-M1C7T1 Data Latency : 58.9ns
U11-M0C5T1 <> U13-M0C6T1 Data Latency : 21.7ns
U11-M0C5T1 <> U15-M0C7T1 Data Latency : 21.7ns
U11-M0C5T1 <> U17-M1C0T1 Data Latency : 57.4ns
U11-M0C5T1 <> U19-M1C1T1 Data Latency : 57.3ns
U11-M0C5T1 <> U21-M1C2T1 Data Latency : 57.6ns
U11-M0C5T1 <> U23-M1C3T1 Data Latency : 57.8ns
U11-M0C5T1 <> U25-M1C4T1 Data Latency : 58.5ns
U11-M0C5T1 <> U27-M1C5T1 Data Latency : 58.4ns
U11-M0C5T1 <> U29-M1C6T1 Data Latency : 58.9ns
U11-M0C5T1 <> U31-M1C7T1 Data Latency : 58.4ns
U13-M0C6T1 <> U15-M0C7T1 Data Latency : 22.9ns
U13-M0C6T1 <> U17-M1C0T1 Data Latency : 58.4ns
U13-M0C6T1 <> U19-M1C1T1 Data Latency : 57.9ns
U13-M0C6T1 <> U21-M1C2T1 Data Latency : 58.5ns
U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.6ns
U13-M0C6T1 <> U25-M1C4T1 Data Latency : 59.0ns
U13-M0C6T1 <> U27-M1C5T1 Data Latency : 59.0ns
U13-M0C6T1 <> U29-M1C6T1 Data Latency : 59.7ns
U13-M0C6T1 <> U31-M1C7T1 Data Latency : 59.8ns
U15-M0C7T1 <> U17-M1C0T1 Data Latency : 57.9ns
U15-M0C7T1 <> U19-M1C1T1 Data Latency : 57.6ns
U15-M0C7T1 <> U21-M1C2T1 Data Latency : 58.1ns
U15-M0C7T1 <> U23-M1C3T1 Data Latency : 58.2ns
U15-M0C7T1 <> U25-M1C4T1 Data Latency : 59.0ns
U15-M0C7T1 <> U27-M1C5T1 Data Latency : 58.6ns
U15-M0C7T1 <> U29-M1C6T1 Data Latency : 59.5ns
U15-M0C7T1 <> U31-M1C7T1 Data Latency : 59.2ns
U17-M1C0T1 <> U19-M1C1T1 Data Latency : 19.2ns
U17-M1C0T1 <> U21-M1C2T1 Data Latency : 20.0ns
U17-M1C0T1 <> U23-M1C3T1 Data Latency : 19.7ns
U17-M1C0T1 <> U25-M1C4T1 Data Latency : 20.9ns
U17-M1C0T1 <> U27-M1C5T1 Data Latency : 20.4ns
U17-M1C0T1 <> U29-M1C6T1 Data Latency : 21.5ns
U17-M1C0T1 <> U31-M1C7T1 Data Latency : 20.5ns
U19-M1C1T1 <> U21-M1C2T1 Data Latency : 18.9ns
U19-M1C1T1 <> U23-M1C3T1 Data Latency : 19.9ns
U19-M1C1T1 <> U25-M1C4T1 Data Latency : 19.7ns
U19-M1C1T1 <> U27-M1C5T1 Data Latency : 20.5ns
U19-M1C1T1 <> U29-M1C6T1 Data Latency : 20.4ns
U19-M1C1T1 <> U31-M1C7T1 Data Latency : 20.4ns
U21-M1C2T1 <> U23-M1C3T1 Data Latency : 19.6ns
U21-M1C2T1 <> U25-M1C4T1 Data Latency : 21.6ns
U21-M1C2T1 <> U27-M1C5T1 Data Latency : 20.4ns
U21-M1C2T1 <> U29-M1C6T1 Data Latency : 22.0ns
U21-M1C2T1 <> U31-M1C7T1 Data Latency : 21.1ns
U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.4ns
U23-M1C3T1 <> U27-M1C5T1 Data Latency : 21.3ns
U23-M1C3T1 <> U29-M1C6T1 Data Latency : 21.0ns
U23-M1C3T1 <> U31-M1C7T1 Data Latency : 21.0ns
U25-M1C4T1 <> U27-M1C5T1 Data Latency : 21.3ns
U25-M1C4T1 <> U29-M1C6T1 Data Latency : 23.0ns
U25-M1C4T1 <> U31-M1C7T1 Data Latency : 21.9ns
U27-M1C5T1 <> U29-M1C6T1 Data Latency : 21.6ns
U27-M1C5T1 <> U31-M1C7T1 Data Latency : 21.7ns
U29-M1C6T1 <> U31-M1C7T1 Data Latency : 22.2ns
1x 64bytes Blocks Bandwidth : 26GB/s
4x 64bytes Blocks Bandwidth : 28.76GB/s
4x 256bytes Blocks Bandwidth : 96.46GB/s
4x 1kB Blocks Bandwidth : 321.1GB/s
4x 4kB Blocks Bandwidth : 507GB/s
16x 4kB Blocks Bandwidth : 726.56GB/s
4x 64kB Blocks Bandwidth : 995.61GB/s
16x 64kB Blocks Bandwidth : 598.29GB/s
8x 256kB Blocks Bandwidth : 602.17GB/s
4x 1MB Blocks Bandwidth : 608.9GB/s
16x 1MB Blocks Bandwidth : 24.7GB/s
8x 4MB Blocks Bandwidth : 19.17GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 5GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
Microcode : A20F10-1009
Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
Platform Compliance : x64
No. Threads : 32
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5950X 16-Core Processor
URL : https://www.amd.com
Speed : 5GHz
Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 5GHz
Modules per Processor : 2 Unit(s)
Cores per Processor : 8 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : A20F10-1009
L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
Rated Power (TDP) : 105.00W

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.
I wish the links to the 2nd CCD wouldn't be that low - AMD likely can bump them up
But 9.8ns Inter-Thread Latency is quite awesome :)
2489041


Just if they would finally unlock PBO Override beyond 200mhz :/
* test was between Windows 10 ProWorkstation Ultimate-Perf Powerplan & Balanced AMD with the slider to the right
** lost my own Plan but the red line is the balanced, which shows improvement on cache-boost ~ when you have more boosting reserves, as other cores slow down by c-state generation
Result could be way better if DF-States where not broken :cautious:


I do feel like you can unleash the EDC limiter
Cache seems to throttle a bit for you
Also thanks to your MDL Optimize Offline guide @KedarWolf
Combined with GitHub - DrEmpiricism/ConvertTo-PfW: Windows 10 Home to Windows 10 Pro for Workstations converter.
It works quite well :)
* just need to use NTLite (free) for iso creation, as .esd encrypts and the old decrypter - has disabled servers :(
Was playing with 21H1, but maan you have 100+ windows autorun services added to it ~ it's really bad
But without them (autoruns.exe) it wasn't even bad ~ tho ProWorkstation seems to have a subtle better thread scheduler
 

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View attachment 2489013

View attachment 2489011

Code:
SiSoftware Sandra

Benchmark Results
Aggregate Inter-Thread Bandwidth : 176GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Average Inter-Thread Latency : 39.9ns (9.5ns - 61.4ns)
Inter-Thread (same Core) Latency : 9.8ns
Inter-Core (same Module) Latency : 21.0ns
Inter-Module (same Package) Latency : 58.4ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 5.5GB/s
No. Threads : 32
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 105.00W
Aggregate Inter-Thread Bandwidth : 1716.17MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 3.80ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 707.05kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 36.22MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 0.08ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
U0-M0C0T0 <> U2-M0C1T0 Data Latency : 22.2ns
U0-M0C0T0 <> U4-M0C2T0 Data Latency : 19.6ns
U0-M0C0T0 <> U6-M0C3T0 Data Latency : 20.1ns
U0-M0C0T0 <> U8-M0C4T0 Data Latency : 19.9ns
U0-M0C0T0 <> U10-M0C5T0 Data Latency : 20.4ns
U0-M0C0T0 <> U12-M0C6T0 Data Latency : 20.8ns
U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.5ns
U0-M0C0T0 <> U16-M1C0T0 Data Latency : 56.9ns
U0-M0C0T0 <> U18-M1C1T0 Data Latency : 56.6ns
U0-M0C0T0 <> U20-M1C2T0 Data Latency : 56.9ns
U0-M0C0T0 <> U22-M1C3T0 Data Latency : 57.3ns
U0-M0C0T0 <> U24-M1C4T0 Data Latency : 58.0ns
U0-M0C0T0 <> U26-M1C5T0 Data Latency : 57.5ns
U0-M0C0T0 <> U28-M1C6T0 Data Latency : 58.1ns
U0-M0C0T0 <> U30-M1C7T0 Data Latency : 58.1ns
U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.6ns
U0-M0C0T0 <> U3-M0C1T1 Data Latency : 19.5ns
U0-M0C0T0 <> U5-M0C2T1 Data Latency : 19.5ns
U0-M0C0T0 <> U7-M0C3T1 Data Latency : 20.0ns
U0-M0C0T0 <> U9-M0C4T1 Data Latency : 19.8ns
U0-M0C0T0 <> U11-M0C5T1 Data Latency : 20.5ns
U0-M0C0T0 <> U13-M0C6T1 Data Latency : 20.8ns
U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.5ns
U0-M0C0T0 <> U17-M1C0T1 Data Latency : 56.9ns
U0-M0C0T0 <> U19-M1C1T1 Data Latency : 56.4ns
U0-M0C0T0 <> U21-M1C2T1 Data Latency : 56.9ns
U0-M0C0T0 <> U23-M1C3T1 Data Latency : 57.3ns
U0-M0C0T0 <> U25-M1C4T1 Data Latency : 58.0ns
U0-M0C0T0 <> U27-M1C5T1 Data Latency : 57.5ns
U0-M0C0T0 <> U29-M1C6T1 Data Latency : 58.1ns
U0-M0C0T0 <> U31-M1C7T1 Data Latency : 58.1ns
U2-M0C1T0 <> U4-M0C2T0 Data Latency : 19.2ns
U2-M0C1T0 <> U6-M0C3T0 Data Latency : 20.8ns
U2-M0C1T0 <> U8-M0C4T0 Data Latency : 19.7ns
U2-M0C1T0 <> U10-M0C5T0 Data Latency : 21.4ns
U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.5ns
U2-M0C1T0 <> U14-M0C7T0 Data Latency : 21.0ns
U2-M0C1T0 <> U16-M1C0T0 Data Latency : 56.8ns
U2-M0C1T0 <> U18-M1C1T0 Data Latency : 57.0ns
U2-M0C1T0 <> U20-M1C2T0 Data Latency : 57.1ns
U2-M0C1T0 <> U22-M1C3T0 Data Latency : 60.9ns
U2-M0C1T0 <> U24-M1C4T0 Data Latency : 61.0ns
U2-M0C1T0 <> U26-M1C5T0 Data Latency : 60.8ns
U2-M0C1T0 <> U28-M1C6T0 Data Latency : 60.5ns
U2-M0C1T0 <> U30-M1C7T0 Data Latency : 60.3ns
U2-M0C1T0 <> U1-M0C0T1 Data Latency : 22.2ns
U2-M0C1T0 <> U3-M0C1T1 Data Latency : 10.0ns
U2-M0C1T0 <> U5-M0C2T1 Data Latency : 21.9ns
U2-M0C1T0 <> U7-M0C3T1 Data Latency : 23.0ns
U2-M0C1T0 <> U9-M0C4T1 Data Latency : 21.1ns
U2-M0C1T0 <> U11-M0C5T1 Data Latency : 22.3ns
U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.6ns
U2-M0C1T0 <> U15-M0C7T1 Data Latency : 21.8ns
U2-M0C1T0 <> U17-M1C0T1 Data Latency : 61.4ns
U2-M0C1T0 <> U19-M1C1T1 Data Latency : 61.1ns
U2-M0C1T0 <> U21-M1C2T1 Data Latency : 61.2ns
U2-M0C1T0 <> U23-M1C3T1 Data Latency : 60.9ns
U2-M0C1T0 <> U25-M1C4T1 Data Latency : 61.1ns
U2-M0C1T0 <> U27-M1C5T1 Data Latency : 60.8ns
U2-M0C1T0 <> U29-M1C6T1 Data Latency : 60.5ns
U2-M0C1T0 <> U31-M1C7T1 Data Latency : 60.3ns
U4-M0C2T0 <> U6-M0C3T0 Data Latency : 21.3ns
U4-M0C2T0 <> U8-M0C4T0 Data Latency : 20.6ns
U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.5ns
U4-M0C2T0 <> U12-M0C6T0 Data Latency : 19.9ns
U4-M0C2T0 <> U14-M0C7T0 Data Latency : 19.8ns
U4-M0C2T0 <> U16-M1C0T0 Data Latency : 60.3ns
U4-M0C2T0 <> U18-M1C1T0 Data Latency : 60.7ns
U4-M0C2T0 <> U20-M1C2T0 Data Latency : 60.2ns
U4-M0C2T0 <> U22-M1C3T0 Data Latency : 60.6ns
U4-M0C2T0 <> U24-M1C4T0 Data Latency : 59.7ns
U4-M0C2T0 <> U26-M1C5T0 Data Latency : 60.4ns
U4-M0C2T0 <> U28-M1C6T0 Data Latency : 59.6ns
U4-M0C2T0 <> U30-M1C7T0 Data Latency : 60.0ns
U4-M0C2T0 <> U1-M0C0T1 Data Latency : 22.0ns
U4-M0C2T0 <> U3-M0C1T1 Data Latency : 22.2ns
U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.8ns
U4-M0C2T0 <> U7-M0C3T1 Data Latency : 21.2ns
U4-M0C2T0 <> U9-M0C4T1 Data Latency : 20.6ns
U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.5ns
U4-M0C2T0 <> U13-M0C6T1 Data Latency : 19.9ns
U4-M0C2T0 <> U15-M0C7T1 Data Latency : 19.8ns
U4-M0C2T0 <> U17-M1C0T1 Data Latency : 60.4ns
U4-M0C2T0 <> U19-M1C1T1 Data Latency : 60.8ns
U4-M0C2T0 <> U21-M1C2T1 Data Latency : 60.1ns
U4-M0C2T0 <> U23-M1C3T1 Data Latency : 60.5ns
U4-M0C2T0 <> U25-M1C4T1 Data Latency : 59.7ns
U4-M0C2T0 <> U27-M1C5T1 Data Latency : 60.4ns
U4-M0C2T0 <> U29-M1C6T1 Data Latency : 59.6ns
U4-M0C2T0 <> U31-M1C7T1 Data Latency : 60.1ns
U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.6ns
U6-M0C3T0 <> U10-M0C5T0 Data Latency : 21.7ns
U6-M0C3T0 <> U12-M0C6T0 Data Latency : 19.9ns
U6-M0C3T0 <> U14-M0C7T0 Data Latency : 21.1ns
U6-M0C3T0 <> U16-M1C0T0 Data Latency : 61.1ns
U6-M0C3T0 <> U18-M1C1T0 Data Latency : 60.9ns
U6-M0C3T0 <> U20-M1C2T0 Data Latency : 60.9ns
U6-M0C3T0 <> U22-M1C3T0 Data Latency : 60.4ns
U6-M0C3T0 <> U24-M1C4T0 Data Latency : 60.4ns
U6-M0C3T0 <> U26-M1C5T0 Data Latency : 60.5ns
U6-M0C3T0 <> U28-M1C6T0 Data Latency : 60.2ns
U6-M0C3T0 <> U30-M1C7T0 Data Latency : 60.1ns
U6-M0C3T0 <> U1-M0C0T1 Data Latency : 21.9ns
U6-M0C3T0 <> U3-M0C1T1 Data Latency : 23.2ns
U6-M0C3T0 <> U5-M0C2T1 Data Latency : 21.4ns
U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.9ns
U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.7ns
U6-M0C3T0 <> U11-M0C5T1 Data Latency : 21.7ns
U6-M0C3T0 <> U13-M0C6T1 Data Latency : 19.9ns
U6-M0C3T0 <> U15-M0C7T1 Data Latency : 21.2ns
U6-M0C3T0 <> U17-M1C0T1 Data Latency : 57.0ns
U6-M0C3T0 <> U19-M1C1T1 Data Latency : 57.0ns
U6-M0C3T0 <> U21-M1C2T1 Data Latency : 57.3ns
U6-M0C3T0 <> U23-M1C3T1 Data Latency : 57.5ns
U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.0ns
U6-M0C3T0 <> U27-M1C5T1 Data Latency : 58.2ns
U6-M0C3T0 <> U29-M1C6T1 Data Latency : 58.6ns
U6-M0C3T0 <> U31-M1C7T1 Data Latency : 58.3ns
U8-M0C4T0 <> U10-M0C5T0 Data Latency : 21.0ns
U8-M0C4T0 <> U12-M0C6T0 Data Latency : 22.8ns
U8-M0C4T0 <> U14-M0C7T0 Data Latency : 21.7ns
U8-M0C4T0 <> U16-M1C0T0 Data Latency : 57.7ns
U8-M0C4T0 <> U18-M1C1T0 Data Latency : 57.2ns
U8-M0C4T0 <> U20-M1C2T0 Data Latency : 58.0ns
U8-M0C4T0 <> U22-M1C3T0 Data Latency : 57.8ns
U8-M0C4T0 <> U24-M1C4T0 Data Latency : 58.6ns
U8-M0C4T0 <> U26-M1C5T0 Data Latency : 58.4ns
U8-M0C4T0 <> U28-M1C6T0 Data Latency : 58.9ns
U8-M0C4T0 <> U30-M1C7T0 Data Latency : 58.8ns
U8-M0C4T0 <> U1-M0C0T1 Data Latency : 20.7ns
U8-M0C4T0 <> U3-M0C1T1 Data Latency : 19.9ns
U8-M0C4T0 <> U5-M0C2T1 Data Latency : 21.8ns
U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.5ns
U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.5ns
U8-M0C4T0 <> U11-M0C5T1 Data Latency : 21.0ns
U8-M0C4T0 <> U13-M0C6T1 Data Latency : 22.9ns
U8-M0C4T0 <> U15-M0C7T1 Data Latency : 21.7ns
U8-M0C4T0 <> U17-M1C0T1 Data Latency : 57.7ns
U8-M0C4T0 <> U19-M1C1T1 Data Latency : 57.2ns
U8-M0C4T0 <> U21-M1C2T1 Data Latency : 57.9ns
U8-M0C4T0 <> U23-M1C3T1 Data Latency : 57.8ns
U8-M0C4T0 <> U25-M1C4T1 Data Latency : 58.6ns
U8-M0C4T0 <> U27-M1C5T1 Data Latency : 58.4ns
U8-M0C4T0 <> U29-M1C6T1 Data Latency : 58.8ns
U8-M0C4T0 <> U31-M1C7T1 Data Latency : 58.7ns
U10-M0C5T0 <> U12-M0C6T0 Data Latency : 21.7ns
U10-M0C5T0 <> U14-M0C7T0 Data Latency : 21.7ns
U10-M0C5T0 <> U16-M1C0T0 Data Latency : 57.4ns
U10-M0C5T0 <> U18-M1C1T0 Data Latency : 57.1ns
U10-M0C5T0 <> U20-M1C2T0 Data Latency : 57.6ns
U10-M0C5T0 <> U22-M1C3T0 Data Latency : 57.8ns
U10-M0C5T0 <> U24-M1C4T0 Data Latency : 58.4ns
U10-M0C5T0 <> U26-M1C5T0 Data Latency : 58.3ns
U10-M0C5T0 <> U28-M1C6T0 Data Latency : 58.9ns
U10-M0C5T0 <> U30-M1C7T0 Data Latency : 58.2ns
U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.3ns
U10-M0C5T0 <> U3-M0C1T1 Data Latency : 20.9ns
U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.5ns
U10-M0C5T0 <> U7-M0C3T1 Data Latency : 21.5ns
U10-M0C5T0 <> U9-M0C4T1 Data Latency : 20.9ns
U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.8ns
U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.7ns
U10-M0C5T0 <> U15-M0C7T1 Data Latency : 21.7ns
U10-M0C5T0 <> U17-M1C0T1 Data Latency : 57.4ns
U10-M0C5T0 <> U19-M1C1T1 Data Latency : 57.2ns
U10-M0C5T0 <> U21-M1C2T1 Data Latency : 57.6ns
U10-M0C5T0 <> U23-M1C3T1 Data Latency : 57.6ns
U10-M0C5T0 <> U25-M1C4T1 Data Latency : 58.4ns
U10-M0C5T0 <> U27-M1C5T1 Data Latency : 58.3ns
U10-M0C5T0 <> U29-M1C6T1 Data Latency : 58.8ns
U10-M0C5T0 <> U31-M1C7T1 Data Latency : 58.3ns
U12-M0C6T0 <> U14-M0C7T0 Data Latency : 22.4ns
U12-M0C6T0 <> U16-M1C0T0 Data Latency : 58.4ns
U12-M0C6T0 <> U18-M1C1T0 Data Latency : 57.8ns
U12-M0C6T0 <> U20-M1C2T0 Data Latency : 58.5ns
U12-M0C6T0 <> U22-M1C3T0 Data Latency : 58.7ns
U12-M0C6T0 <> U24-M1C4T0 Data Latency : 59.1ns
U12-M0C6T0 <> U26-M1C5T0 Data Latency : 59.0ns
U12-M0C6T0 <> U28-M1C6T0 Data Latency : 59.7ns
U12-M0C6T0 <> U30-M1C7T0 Data Latency : 59.8ns
U12-M0C6T0 <> U1-M0C0T1 Data Latency : 21.6ns
U12-M0C6T0 <> U3-M0C1T1 Data Latency : 20.7ns
U12-M0C6T0 <> U5-M0C2T1 Data Latency : 22.4ns
U12-M0C6T0 <> U7-M0C3T1 Data Latency : 21.3ns
U12-M0C6T0 <> U9-M0C4T1 Data Latency : 22.9ns
U12-M0C6T0 <> U11-M0C5T1 Data Latency : 21.8ns
U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.9ns
U12-M0C6T0 <> U15-M0C7T1 Data Latency : 22.5ns
U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.4ns
U12-M0C6T0 <> U19-M1C1T1 Data Latency : 58.0ns
U12-M0C6T0 <> U21-M1C2T1 Data Latency : 58.5ns
U12-M0C6T0 <> U23-M1C3T1 Data Latency : 58.6ns
U12-M0C6T0 <> U25-M1C4T1 Data Latency : 59.1ns
U12-M0C6T0 <> U27-M1C5T1 Data Latency : 59.0ns
U12-M0C6T0 <> U29-M1C6T1 Data Latency : 59.7ns
U12-M0C6T0 <> U31-M1C7T1 Data Latency : 59.7ns
U14-M0C7T0 <> U16-M1C0T0 Data Latency : 58.0ns
U14-M0C7T0 <> U18-M1C1T0 Data Latency : 57.6ns
U14-M0C7T0 <> U20-M1C2T0 Data Latency : 58.1ns
U14-M0C7T0 <> U22-M1C3T0 Data Latency : 58.1ns
U14-M0C7T0 <> U24-M1C4T0 Data Latency : 59.1ns
U14-M0C7T0 <> U26-M1C5T0 Data Latency : 58.5ns
U14-M0C7T0 <> U28-M1C6T0 Data Latency : 59.6ns
U14-M0C7T0 <> U30-M1C7T0 Data Latency : 59.1ns
U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.6ns
U14-M0C7T0 <> U3-M0C1T1 Data Latency : 20.8ns
U14-M0C7T0 <> U5-M0C2T1 Data Latency : 21.3ns
U14-M0C7T0 <> U7-M0C3T1 Data Latency : 21.4ns
U14-M0C7T0 <> U9-M0C4T1 Data Latency : 21.7ns
U14-M0C7T0 <> U11-M0C5T1 Data Latency : 21.9ns
U14-M0C7T0 <> U13-M0C6T1 Data Latency : 22.3ns
U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.8ns
U14-M0C7T0 <> U17-M1C0T1 Data Latency : 57.9ns
U14-M0C7T0 <> U19-M1C1T1 Data Latency : 57.5ns
U14-M0C7T0 <> U21-M1C2T1 Data Latency : 58.1ns
U14-M0C7T0 <> U23-M1C3T1 Data Latency : 58.2ns
U14-M0C7T0 <> U25-M1C4T1 Data Latency : 59.0ns
U14-M0C7T0 <> U27-M1C5T1 Data Latency : 58.5ns
U14-M0C7T0 <> U29-M1C6T1 Data Latency : 59.5ns
U14-M0C7T0 <> U31-M1C7T1 Data Latency : 59.1ns
U16-M1C0T0 <> U18-M1C1T0 Data Latency : 19.2ns
U16-M1C0T0 <> U20-M1C2T0 Data Latency : 20.0ns
U16-M1C0T0 <> U22-M1C3T0 Data Latency : 19.7ns
U16-M1C0T0 <> U24-M1C4T0 Data Latency : 20.9ns
U16-M1C0T0 <> U26-M1C5T0 Data Latency : 20.3ns
U16-M1C0T0 <> U28-M1C6T0 Data Latency : 21.5ns
U16-M1C0T0 <> U30-M1C7T0 Data Latency : 20.5ns
U16-M1C0T0 <> U1-M0C0T1 Data Latency : 57.1ns
U16-M1C0T0 <> U3-M0C1T1 Data Latency : 56.9ns
U16-M1C0T0 <> U5-M0C2T1 Data Latency : 57.0ns
U16-M1C0T0 <> U7-M0C3T1 Data Latency : 57.4ns
U16-M1C0T0 <> U9-M0C4T1 Data Latency : 57.6ns
U16-M1C0T0 <> U11-M0C5T1 Data Latency : 57.6ns
U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.2ns
U16-M1C0T0 <> U15-M0C7T1 Data Latency : 58.0ns
U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.8ns
U16-M1C0T0 <> U19-M1C1T1 Data Latency : 19.2ns
U16-M1C0T0 <> U21-M1C2T1 Data Latency : 20.1ns
U16-M1C0T0 <> U23-M1C3T1 Data Latency : 19.7ns
U16-M1C0T0 <> U25-M1C4T1 Data Latency : 20.9ns
U16-M1C0T0 <> U27-M1C5T1 Data Latency : 20.3ns
U16-M1C0T0 <> U29-M1C6T1 Data Latency : 21.5ns
U16-M1C0T0 <> U31-M1C7T1 Data Latency : 20.5ns
U18-M1C1T0 <> U20-M1C2T0 Data Latency : 18.9ns
U18-M1C1T0 <> U22-M1C3T0 Data Latency : 19.9ns
U18-M1C1T0 <> U24-M1C4T0 Data Latency : 19.7ns
U18-M1C1T0 <> U26-M1C5T0 Data Latency : 20.5ns
U18-M1C1T0 <> U28-M1C6T0 Data Latency : 20.5ns
U18-M1C1T0 <> U30-M1C7T0 Data Latency : 20.4ns
U18-M1C1T0 <> U1-M0C0T1 Data Latency : 56.1ns
U18-M1C1T0 <> U3-M0C1T1 Data Latency : 56.8ns
U18-M1C1T0 <> U5-M0C2T1 Data Latency : 56.9ns
U18-M1C1T0 <> U7-M0C3T1 Data Latency : 57.1ns
U18-M1C1T0 <> U9-M0C4T1 Data Latency : 57.0ns
U18-M1C1T0 <> U11-M0C5T1 Data Latency : 57.1ns
U18-M1C1T0 <> U13-M0C6T1 Data Latency : 57.7ns
U18-M1C1T0 <> U15-M0C7T1 Data Latency : 57.3ns
U18-M1C1T0 <> U17-M1C0T1 Data Latency : 19.2ns
U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.8ns
U18-M1C1T0 <> U21-M1C2T1 Data Latency : 18.9ns
U18-M1C1T0 <> U23-M1C3T1 Data Latency : 19.9ns
U18-M1C1T0 <> U25-M1C4T1 Data Latency : 19.7ns
U18-M1C1T0 <> U27-M1C5T1 Data Latency : 20.5ns
U18-M1C1T0 <> U29-M1C6T1 Data Latency : 20.4ns
U18-M1C1T0 <> U31-M1C7T1 Data Latency : 20.4ns
U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.6ns
U20-M1C2T0 <> U24-M1C4T0 Data Latency : 21.6ns
U20-M1C2T0 <> U26-M1C5T0 Data Latency : 20.4ns
U20-M1C2T0 <> U28-M1C6T0 Data Latency : 22.0ns
U20-M1C2T0 <> U30-M1C7T0 Data Latency : 21.1ns
U20-M1C2T0 <> U1-M0C0T1 Data Latency : 57.1ns
U20-M1C2T0 <> U3-M0C1T1 Data Latency : 57.7ns
U20-M1C2T0 <> U5-M0C2T1 Data Latency : 57.4ns
U20-M1C2T0 <> U7-M0C3T1 Data Latency : 57.6ns
U20-M1C2T0 <> U9-M0C4T1 Data Latency : 57.7ns
U20-M1C2T0 <> U11-M0C5T1 Data Latency : 58.2ns
U20-M1C2T0 <> U13-M0C6T1 Data Latency : 58.3ns
U20-M1C2T0 <> U15-M0C7T1 Data Latency : 58.2ns
U20-M1C2T0 <> U17-M1C0T1 Data Latency : 20.1ns
U20-M1C2T0 <> U19-M1C1T1 Data Latency : 19.0ns
U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.8ns
U20-M1C2T0 <> U23-M1C3T1 Data Latency : 19.5ns
U20-M1C2T0 <> U25-M1C4T1 Data Latency : 21.6ns
U20-M1C2T0 <> U27-M1C5T1 Data Latency : 20.4ns
U20-M1C2T0 <> U29-M1C6T1 Data Latency : 22.0ns
U20-M1C2T0 <> U31-M1C7T1 Data Latency : 21.1ns
U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.4ns
U22-M1C3T0 <> U26-M1C5T0 Data Latency : 21.3ns
U22-M1C3T0 <> U28-M1C6T0 Data Latency : 21.0ns
U22-M1C3T0 <> U30-M1C7T0 Data Latency : 20.9ns
U22-M1C3T0 <> U1-M0C0T1 Data Latency : 57.0ns
U22-M1C3T0 <> U3-M0C1T1 Data Latency : 57.7ns
U22-M1C3T0 <> U5-M0C2T1 Data Latency : 57.4ns
U22-M1C3T0 <> U7-M0C3T1 Data Latency : 57.7ns
U22-M1C3T0 <> U9-M0C4T1 Data Latency : 57.6ns
U22-M1C3T0 <> U11-M0C5T1 Data Latency : 57.9ns
U22-M1C3T0 <> U13-M0C6T1 Data Latency : 58.3ns
U22-M1C3T0 <> U15-M0C7T1 Data Latency : 58.1ns
U22-M1C3T0 <> U17-M1C0T1 Data Latency : 19.6ns
U22-M1C3T0 <> U19-M1C1T1 Data Latency : 20.0ns
U22-M1C3T0 <> U21-M1C2T1 Data Latency : 19.4ns
U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.8ns
U22-M1C3T0 <> U25-M1C4T1 Data Latency : 20.4ns
U22-M1C3T0 <> U27-M1C5T1 Data Latency : 21.3ns
U22-M1C3T0 <> U29-M1C6T1 Data Latency : 21.0ns
U22-M1C3T0 <> U31-M1C7T1 Data Latency : 20.9ns
U24-M1C4T0 <> U26-M1C5T0 Data Latency : 21.2ns
U24-M1C4T0 <> U28-M1C6T0 Data Latency : 22.9ns
U24-M1C4T0 <> U30-M1C7T0 Data Latency : 21.9ns
U24-M1C4T0 <> U1-M0C0T1 Data Latency : 57.9ns
U24-M1C4T0 <> U3-M0C1T1 Data Latency : 58.3ns
U24-M1C4T0 <> U5-M0C2T1 Data Latency : 58.1ns
U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.3ns
U24-M1C4T0 <> U9-M0C4T1 Data Latency : 58.7ns
U24-M1C4T0 <> U11-M0C5T1 Data Latency : 58.9ns
U24-M1C4T0 <> U13-M0C6T1 Data Latency : 59.3ns
U24-M1C4T0 <> U15-M0C7T1 Data Latency : 59.1ns
U24-M1C4T0 <> U17-M1C0T1 Data Latency : 21.1ns
U24-M1C4T0 <> U19-M1C1T1 Data Latency : 19.8ns
U24-M1C4T0 <> U21-M1C2T1 Data Latency : 21.7ns
U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.5ns
U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.9ns
U24-M1C4T0 <> U27-M1C5T1 Data Latency : 21.3ns
U24-M1C4T0 <> U29-M1C6T1 Data Latency : 22.9ns
U24-M1C4T0 <> U31-M1C7T1 Data Latency : 21.9ns
U26-M1C5T0 <> U28-M1C6T0 Data Latency : 21.6ns
U26-M1C5T0 <> U30-M1C7T0 Data Latency : 21.7ns
U26-M1C5T0 <> U1-M0C0T1 Data Latency : 57.4ns
U26-M1C5T0 <> U3-M0C1T1 Data Latency : 58.2ns
U26-M1C5T0 <> U5-M0C2T1 Data Latency : 57.9ns
U26-M1C5T0 <> U7-M0C3T1 Data Latency : 58.2ns
U26-M1C5T0 <> U9-M0C4T1 Data Latency : 58.2ns
U26-M1C5T0 <> U11-M0C5T1 Data Latency : 58.3ns
U26-M1C5T0 <> U13-M0C6T1 Data Latency : 58.9ns
U26-M1C5T0 <> U15-M0C7T1 Data Latency : 58.7ns
U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.3ns
U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.6ns
U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.2ns
U26-M1C5T0 <> U23-M1C3T1 Data Latency : 21.3ns
U26-M1C5T0 <> U25-M1C4T1 Data Latency : 21.1ns
U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.8ns
U26-M1C5T0 <> U29-M1C6T1 Data Latency : 21.6ns
U26-M1C5T0 <> U31-M1C7T1 Data Latency : 21.7ns
U28-M1C6T0 <> U30-M1C7T0 Data Latency : 22.3ns
U28-M1C6T0 <> U1-M0C0T1 Data Latency : 58.4ns
U28-M1C6T0 <> U3-M0C1T1 Data Latency : 58.7ns
U28-M1C6T0 <> U5-M0C2T1 Data Latency : 58.8ns
U28-M1C6T0 <> U7-M0C3T1 Data Latency : 59.1ns
U28-M1C6T0 <> U9-M0C4T1 Data Latency : 58.9ns
U28-M1C6T0 <> U11-M0C5T1 Data Latency : 59.2ns
U28-M1C6T0 <> U13-M0C6T1 Data Latency : 59.6ns
U28-M1C6T0 <> U15-M0C7T1 Data Latency : 59.5ns
U28-M1C6T0 <> U17-M1C0T1 Data Latency : 21.6ns
U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.4ns
U28-M1C6T0 <> U21-M1C2T1 Data Latency : 22.2ns
U28-M1C6T0 <> U23-M1C3T1 Data Latency : 21.1ns
U28-M1C6T0 <> U25-M1C4T1 Data Latency : 23.0ns
U28-M1C6T0 <> U27-M1C5T1 Data Latency : 21.7ns
U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.8ns
U28-M1C6T0 <> U31-M1C7T1 Data Latency : 22.3ns
U30-M1C7T0 <> U1-M0C0T1 Data Latency : 58.0ns
U30-M1C7T0 <> U3-M0C1T1 Data Latency : 58.4ns
U30-M1C7T0 <> U5-M0C2T1 Data Latency : 58.4ns
U30-M1C7T0 <> U7-M0C3T1 Data Latency : 58.8ns
U30-M1C7T0 <> U9-M0C4T1 Data Latency : 58.7ns
U30-M1C7T0 <> U11-M0C5T1 Data Latency : 58.6ns
U30-M1C7T0 <> U13-M0C6T1 Data Latency : 59.5ns
U30-M1C7T0 <> U15-M0C7T1 Data Latency : 59.2ns
U30-M1C7T0 <> U17-M1C0T1 Data Latency : 20.6ns
U30-M1C7T0 <> U19-M1C1T1 Data Latency : 20.6ns
U30-M1C7T0 <> U21-M1C2T1 Data Latency : 21.1ns
U30-M1C7T0 <> U23-M1C3T1 Data Latency : 21.2ns
U30-M1C7T0 <> U25-M1C4T1 Data Latency : 21.9ns
U30-M1C7T0 <> U27-M1C5T1 Data Latency : 22.0ns
U30-M1C7T0 <> U29-M1C6T1 Data Latency : 22.2ns
U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.8ns
U1-M0C0T1 <> U3-M0C1T1 Data Latency : 19.4ns
U1-M0C0T1 <> U5-M0C2T1 Data Latency : 20.2ns
U1-M0C0T1 <> U7-M0C3T1 Data Latency : 19.9ns
U1-M0C0T1 <> U9-M0C4T1 Data Latency : 20.6ns
U1-M0C0T1 <> U11-M0C5T1 Data Latency : 20.2ns
U1-M0C0T1 <> U13-M0C6T1 Data Latency : 21.5ns
U1-M0C0T1 <> U15-M0C7T1 Data Latency : 20.5ns
U1-M0C0T1 <> U17-M1C0T1 Data Latency : 56.9ns
U1-M0C0T1 <> U19-M1C1T1 Data Latency : 56.3ns
U1-M0C0T1 <> U21-M1C2T1 Data Latency : 57.0ns
U1-M0C0T1 <> U23-M1C3T1 Data Latency : 57.1ns
U1-M0C0T1 <> U25-M1C4T1 Data Latency : 57.9ns
U1-M0C0T1 <> U27-M1C5T1 Data Latency : 57.6ns
U1-M0C0T1 <> U29-M1C6T1 Data Latency : 58.3ns
U1-M0C0T1 <> U31-M1C7T1 Data Latency : 57.9ns
U3-M0C1T1 <> U5-M0C2T1 Data Latency : 19.4ns
U3-M0C1T1 <> U7-M0C3T1 Data Latency : 20.3ns
U3-M0C1T1 <> U9-M0C4T1 Data Latency : 19.9ns
U3-M0C1T1 <> U11-M0C5T1 Data Latency : 20.8ns
U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.8ns
U3-M0C1T1 <> U15-M0C7T1 Data Latency : 20.7ns
U3-M0C1T1 <> U17-M1C0T1 Data Latency : 57.0ns
U3-M0C1T1 <> U19-M1C1T1 Data Latency : 56.8ns
U3-M0C1T1 <> U21-M1C2T1 Data Latency : 57.2ns
U3-M0C1T1 <> U23-M1C3T1 Data Latency : 57.2ns
U3-M0C1T1 <> U25-M1C4T1 Data Latency : 57.8ns
U3-M0C1T1 <> U27-M1C5T1 Data Latency : 57.7ns
U3-M0C1T1 <> U29-M1C6T1 Data Latency : 58.7ns
U3-M0C1T1 <> U31-M1C7T1 Data Latency : 58.1ns
U5-M0C2T1 <> U7-M0C3T1 Data Latency : 19.8ns
U5-M0C2T1 <> U9-M0C4T1 Data Latency : 21.7ns
U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.6ns
U5-M0C2T1 <> U13-M0C6T1 Data Latency : 22.3ns
U5-M0C2T1 <> U15-M0C7T1 Data Latency : 21.3ns
U5-M0C2T1 <> U17-M1C0T1 Data Latency : 57.3ns
U5-M0C2T1 <> U19-M1C1T1 Data Latency : 57.2ns
U5-M0C2T1 <> U21-M1C2T1 Data Latency : 57.4ns
U5-M0C2T1 <> U23-M1C3T1 Data Latency : 57.7ns
U5-M0C2T1 <> U25-M1C4T1 Data Latency : 58.2ns
U5-M0C2T1 <> U27-M1C5T1 Data Latency : 58.3ns
U5-M0C2T1 <> U29-M1C6T1 Data Latency : 58.7ns
U5-M0C2T1 <> U31-M1C7T1 Data Latency : 58.6ns
U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.5ns
U7-M0C3T1 <> U11-M0C5T1 Data Latency : 21.6ns
U7-M0C3T1 <> U13-M0C6T1 Data Latency : 21.3ns
U7-M0C3T1 <> U15-M0C7T1 Data Latency : 21.2ns
U7-M0C3T1 <> U17-M1C0T1 Data Latency : 57.0ns
U7-M0C3T1 <> U19-M1C1T1 Data Latency : 57.1ns
U7-M0C3T1 <> U21-M1C2T1 Data Latency : 57.1ns
U7-M0C3T1 <> U23-M1C3T1 Data Latency : 57.5ns
U7-M0C3T1 <> U25-M1C4T1 Data Latency : 57.9ns
U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.1ns
U7-M0C3T1 <> U29-M1C6T1 Data Latency : 58.7ns
U7-M0C3T1 <> U31-M1C7T1 Data Latency : 58.2ns
U9-M0C4T1 <> U11-M0C5T1 Data Latency : 21.0ns
U9-M0C4T1 <> U13-M0C6T1 Data Latency : 22.9ns
U9-M0C4T1 <> U15-M0C7T1 Data Latency : 21.7ns
U9-M0C4T1 <> U17-M1C0T1 Data Latency : 57.7ns
U9-M0C4T1 <> U19-M1C1T1 Data Latency : 57.3ns
U9-M0C4T1 <> U21-M1C2T1 Data Latency : 58.0ns
U9-M0C4T1 <> U23-M1C3T1 Data Latency : 57.8ns
U9-M0C4T1 <> U25-M1C4T1 Data Latency : 58.6ns
U9-M0C4T1 <> U27-M1C5T1 Data Latency : 58.4ns
U9-M0C4T1 <> U29-M1C6T1 Data Latency : 58.9ns
U9-M0C4T1 <> U31-M1C7T1 Data Latency : 58.9ns
U11-M0C5T1 <> U13-M0C6T1 Data Latency : 21.7ns
U11-M0C5T1 <> U15-M0C7T1 Data Latency : 21.7ns
U11-M0C5T1 <> U17-M1C0T1 Data Latency : 57.4ns
U11-M0C5T1 <> U19-M1C1T1 Data Latency : 57.3ns
U11-M0C5T1 <> U21-M1C2T1 Data Latency : 57.6ns
U11-M0C5T1 <> U23-M1C3T1 Data Latency : 57.8ns
U11-M0C5T1 <> U25-M1C4T1 Data Latency : 58.5ns
U11-M0C5T1 <> U27-M1C5T1 Data Latency : 58.4ns
U11-M0C5T1 <> U29-M1C6T1 Data Latency : 58.9ns
U11-M0C5T1 <> U31-M1C7T1 Data Latency : 58.4ns
U13-M0C6T1 <> U15-M0C7T1 Data Latency : 22.9ns
U13-M0C6T1 <> U17-M1C0T1 Data Latency : 58.4ns
U13-M0C6T1 <> U19-M1C1T1 Data Latency : 57.9ns
U13-M0C6T1 <> U21-M1C2T1 Data Latency : 58.5ns
U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.6ns
U13-M0C6T1 <> U25-M1C4T1 Data Latency : 59.0ns
U13-M0C6T1 <> U27-M1C5T1 Data Latency : 59.0ns
U13-M0C6T1 <> U29-M1C6T1 Data Latency : 59.7ns
U13-M0C6T1 <> U31-M1C7T1 Data Latency : 59.8ns
U15-M0C7T1 <> U17-M1C0T1 Data Latency : 57.9ns
U15-M0C7T1 <> U19-M1C1T1 Data Latency : 57.6ns
U15-M0C7T1 <> U21-M1C2T1 Data Latency : 58.1ns
U15-M0C7T1 <> U23-M1C3T1 Data Latency : 58.2ns
U15-M0C7T1 <> U25-M1C4T1 Data Latency : 59.0ns
U15-M0C7T1 <> U27-M1C5T1 Data Latency : 58.6ns
U15-M0C7T1 <> U29-M1C6T1 Data Latency : 59.5ns
U15-M0C7T1 <> U31-M1C7T1 Data Latency : 59.2ns
U17-M1C0T1 <> U19-M1C1T1 Data Latency : 19.2ns
U17-M1C0T1 <> U21-M1C2T1 Data Latency : 20.0ns
U17-M1C0T1 <> U23-M1C3T1 Data Latency : 19.7ns
U17-M1C0T1 <> U25-M1C4T1 Data Latency : 20.9ns
U17-M1C0T1 <> U27-M1C5T1 Data Latency : 20.4ns
U17-M1C0T1 <> U29-M1C6T1 Data Latency : 21.5ns
U17-M1C0T1 <> U31-M1C7T1 Data Latency : 20.5ns
U19-M1C1T1 <> U21-M1C2T1 Data Latency : 18.9ns
U19-M1C1T1 <> U23-M1C3T1 Data Latency : 19.9ns
U19-M1C1T1 <> U25-M1C4T1 Data Latency : 19.7ns
U19-M1C1T1 <> U27-M1C5T1 Data Latency : 20.5ns
U19-M1C1T1 <> U29-M1C6T1 Data Latency : 20.4ns
U19-M1C1T1 <> U31-M1C7T1 Data Latency : 20.4ns
U21-M1C2T1 <> U23-M1C3T1 Data Latency : 19.6ns
U21-M1C2T1 <> U25-M1C4T1 Data Latency : 21.6ns
U21-M1C2T1 <> U27-M1C5T1 Data Latency : 20.4ns
U21-M1C2T1 <> U29-M1C6T1 Data Latency : 22.0ns
U21-M1C2T1 <> U31-M1C7T1 Data Latency : 21.1ns
U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.4ns
U23-M1C3T1 <> U27-M1C5T1 Data Latency : 21.3ns
U23-M1C3T1 <> U29-M1C6T1 Data Latency : 21.0ns
U23-M1C3T1 <> U31-M1C7T1 Data Latency : 21.0ns
U25-M1C4T1 <> U27-M1C5T1 Data Latency : 21.3ns
U25-M1C4T1 <> U29-M1C6T1 Data Latency : 23.0ns
U25-M1C4T1 <> U31-M1C7T1 Data Latency : 21.9ns
U27-M1C5T1 <> U29-M1C6T1 Data Latency : 21.6ns
U27-M1C5T1 <> U31-M1C7T1 Data Latency : 21.7ns
U29-M1C6T1 <> U31-M1C7T1 Data Latency : 22.2ns
1x 64bytes Blocks Bandwidth : 26GB/s
4x 64bytes Blocks Bandwidth : 28.76GB/s
4x 256bytes Blocks Bandwidth : 96.46GB/s
4x 1kB Blocks Bandwidth : 321.1GB/s
4x 4kB Blocks Bandwidth : 507GB/s
16x 4kB Blocks Bandwidth : 726.56GB/s
4x 64kB Blocks Bandwidth : 995.61GB/s
16x 64kB Blocks Bandwidth : 598.29GB/s
8x 256kB Blocks Bandwidth : 602.17GB/s
4x 1MB Blocks Bandwidth : 608.9GB/s
16x 1MB Blocks Bandwidth : 24.7GB/s
8x 4MB Blocks Bandwidth : 19.17GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 5GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
Microcode : A20F10-1009
Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
Platform Compliance : x64
No. Threads : 32
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5950X 16-Core Processor
URL : https://www.amd.com
Speed : 5GHz
Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 5GHz
Modules per Processor : 2 Unit(s)
Cores per Processor : 8 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : A20F10-1009
L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
Rated Power (TDP) : 105.00W

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.
2489043


Hi! I took it seriously the stress test, 41 cycles.. The truth is I was running an strange version of TM5 and I noticed that it only run 11 test, instead of the 15. So, even if I set 25 cycles, for some reason it continue to testing. No bad. But I will try again after a power off, capacitors discharge.. and try again.. Pretty stable.. And I think the best performance. The latency can go lower, I'm still running above 100 windows process after the last Sophia version.
Well, if you can and help to understand how you came to these values (tRAS, tRP, tWR and tRTP not aligned, an also why with soy low voltage (1.49) do you need so high ProcODT and high CklDvrStr). And last question, I read once time in a Yuri's Post where he talk about CTR, that mention that high vSOC and CPU LLC could cause degradation. It's safe to run so high vSOC for 3800 fcql? Thanks a lot! And also for sharing you vales. Works perfect for me.
 

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Premium Member
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View attachment 2489043

Hi! I took it seriously the stress test, 41 cycles.. The truth is I was running an strange version of TM5 and I noticed that it only run 11 test, instead of the 15. So, even if I set 25 cycles, for some reason it continue to testing. No bad. But I will try again after a power off, capacitors discharge.. and try again.. Pretty stable.. And I think the best performance. The latency can go lower, I'm still running above 100 windows process after the last Sophia version.
Well, if you can and help to understand how you came to these values (tRAS, tRP, tWR and tRTP not aligned, an also why with soy low voltage (1.49) do you need so high ProcODT and high CklDvrStr). And last question, I read once time in a Yuri's Post where he talk about CTR, that mention that high vSOC and CPU LLC could cause degradation. It's safe to run so high vSOC for 3800 fcql? Thanks a lot! And also for sharing you vales. Works perfect for me.
The 19-21 was suggested to me by someone and I find it a bit easier to get stable and a bit better in benchmarks. Technically it should be 21-21 but I find 19-21 benches a bit better. I changed the SCLs to 4 and lowered the ProODT to 40 and the ClkDrStr to 40, this passes TM5, SCLs at 2 doesn't. 1.2v on SoC is the highest I'll go but I've seen people running as high as 1.25v.

From what I understand 5000 series chips have good tolerance for higher voltages, it's 3000 series you want to keep lower.

Edit: I actually get a better score on AIDA64 and Sandra multi-core efficiency with SCLs at 4 instead of 2.
 

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Old crazy guy
Joined
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2,772 Posts
The 19-21 was suggested to me by someone and I find it a bit easier to get stable and a bit better in benchmarks. Technically it should be 21-21 but I find 19-21 benches a bit better. I changed the SCLs to 4 and lowered the ProODT to 40 and the ClkDrStr to 40, this passes TM5, SCLs at 2 doesn't. 1.2v on SoC is the highest I'll go but I've seen people running as high as 1.25v.
I'm checking out but 19/21/42 doesn't work well with my kit, the latency gets errathic.
With a little bump in VDIMM works find with SCL at 2.

But my bandwidth in Sandra is way lower; did you do anything special? I'm on A22 instead of A21O.

2489073
 

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Premium Member
Joined
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6,014 Posts
I'm checking out but 19/21/42 doesn't work well with my kit, the latency gets errathic.
With a little bump in VDIMM works find with SCL at 2.

But my bandwidth in Sandra is way lower; did you do anything special? I'm on A22 instead of A21O.

View attachment 2489073
I'll test traditional instead of 19-21 for latency, but yeah, I change a lot of hidden things you can with A210. I won't be home from work for 8 hours or so though to test. :(

Edit: I'll share my BIOS settings when I get home.
 

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Registered
Overclocking - latest technology
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277 Posts
The 19-21 was suggested to me by someone and I find it a bit easier to get stable and a bit better in benchmarks. Technically it should be 21-21 but I find 19-21 benches a bit better. I changed the SCLs to 4 and lowered the ProODT to 40 and the ClkDrStr to 40, this passes TM5, SCLs at 2 doesn't. 1.2v on SoC is the highest I'll go but I've seen people running as high as 1.25v.

From what I understand 5000 series chips have good tolerance for higher voltages, it's 3000 series you want to keep lower.

Edit: I actually get a better score on AIDA64 and Sandra multi-core efficiency with SCLs at 4 instead of 2.
Yes, it really surprised me that works perfect for me. I think we both share the same PCB, it´s the same model, both Dual Rank. And the score are really good. I don´t think I could improve it so much at 3800. Have you tried 4000-15-15-15? I think this would be my next step.

Regarding the timings, it´s something that I try to understand, reading a lot, but there are some values that ar far away from the rulesets, that really consfused me. Becuase, I know there are a lot of PCB and electrical specific parameters to have in consideration, but as a newbie, that one day I will stop being, I read a lot and in my head I try to think about relationships more than values and rules, so hundreds or thousands of times Veii enlightened us with his advice, because I don´t hink that is everything trial and error, but there must be a relationship, some values with voltages, others with nano seconds and frequencies. I´d love to have an excel but not for calculation, but to understand the relationship between those ns and how they should be related. I think it would be a good way to ask less, or to be more specific, and also to understand better. I see many times that @Veii tell us when a value is not stable, but not by rules, but by his understanding how it works, for example I read a lot about the relationships of tRDWR and tWRRD, which is used as latency, and these related to the TWR, and the SCL, and with the tRFC, everything has to be in tune. So if we talk about recommended values, it is trial and error, but if we talk about relationships, and since everything is related, it can better find a way to test. For example, lowering the tRCDRD, which seems to be the most difficult of all values, implies that you have to make several changes, I can understand some of them, how to loose some times to achieve a stable configuration with less performance and then adjust. But how do I determine the voltage increase? How do I know if 1.5 is enought? Or do I have to go to 1.55 or 1.6? I mean, because this configuration that we are both running now, in my case I´m at 1.5v and you are at 1.49V. However, I always received recommendations not to lower than 1.55! So I always had errors due to overvoltage, not due to lack of it. There is the problem, which is what I would like to understand. The relationships. Some are in ns, related to clock cycles, if some transfer does not start, if another does not finish well, others related to voltage, and others related to resistances or impedances, which obviously have to do with voltage. Following the rules is not so easy, because there are thousands of recommendations, and not all of them coincide. I think that would be a great step to improve a configuration. For example, I will have spent a month trying to lower the tRCDRD to 15 and not to mention 14, but following some assumptions. And I have no way to "hit" without a good calculation. The rayzen Calculator DRAM is very good, but it was outdated, not only does it not go higher than 1800MHz (or MT / s) but if one wants to look for even tighter values, it never takes them. Perhaps there is a calculator that is more self explanatory. I have many doubts left but I keep reading, writing down. I have a Word Document with Veii's recommendations, they are the best! That is why my question about how you got to such a low tRAS, or such a low tRTP, must have a reason, in fact, see how well it worked for me, but like that, I did not learn anything! I take it as a hobby, I have three memory kits, three different mobos, I can try several OC, but I lack that knowledge that I will gradually learn. I confess that it costs me because I am new, but I am 45 years old and I started at 13 with my first online service back in the early 90's, then I was an Engineer in the old Compaq, then HP, Solution Architect, and had all HW certifications and SW. I worked a lot with circuits from a very young age, so I can say that in my life I always did troubleshooting, now I am dedicated to the sales of Software in one of the main German companies, but I am passionate about this and I want to continue learning. I would lack a better guide than values!

The 19-21 was suggested to me by someone and I find it a bit easier to get stable and a bit better in benchmarks. Technically it should be 21-21 but I find 19-21 benches a bit better. I changed the SCLs to 4 and lowered the ProODT to 40 and the ClkDrStr to 40, this passes TM5, SCLs at 2 doesn't. 1.2v on SoC is the highest I'll go but I've seen people running as high as 1.25v.
So you did´t pass TM5 with SCL 2 and ProcODT of 48? Does it perform better with SCL 4 and lower ProcODT of 40? Againt, in mi mind, I higher ClkDrStr would help to compensate high voltages, like ProcODT to be lower and also vSOC. I am really impress that your first configuration pass almows 50 cycles of TM5, but I don'´t thing it´s enought. Let´s see if it pass Y-Cuncher All test.. ANTA777.. and also the HCI Memtest, I have the deliuve version..

Thanks for your tips!
 

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Premium Member
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Yes, it really surprised me that works perfect for me. I think we both share the same PCB, it´s the same model, both Dual Rank. And the score are really good. I don´t think I could improve it so much at 3800. Have you tried 4000-15-15-15? I think this would be my next step.

Regarding the timings, it´s something that I try to understand, reading a lot, but there are some values that ar far away from the rulesets, that really consfused me. Becuase, I know there are a lot of PCB and electrical specific parameters to have in consideration, but as a newbie, that one day I will stop being, I read a lot and in my head I try to think about relationships more than values and rules, so hundreds or thousands of times Veii enlightened us with his advice, because I don´t hink that is everything trial and error, but there must be a relationship, some values with voltages, others with nano seconds and frequencies. I´d love to have an excel but not for calculation, but to understand the relationship between those ns and how they should be related. I think it would be a good way to ask less, or to be more specific, and also to understand better. I see many times that @Veii tell us when a value is not stable, but not by rules, but by his understanding how it works, for example I read a lot about the relationships of tRDWR and tWRRD, which is used as latency, and these related to the TWR, and the SCL, and with the tRFC, everything has to be in tune. So if we talk about recommended values, it is trial and error, but if we talk about relationships, and since everything is related, it can better find a way to test. For example, lowering the tRCDRD, which seems to be the most difficult of all values, implies that you have to make several changes, I can understand some of them, how to loose some times to achieve a stable configuration with less performance and then adjust. But how do I determine the voltage increase? How do I know if 1.5 is enought? Or do I have to go to 1.55 or 1.6? I mean, because this configuration that we are both running now, in my case I´m at 1.5v and you are at 1.49V. However, I always received recommendations not to lower than 1.55! So I always had errors due to overvoltage, not due to lack of it. There is the problem, which is what I would like to understand. The relationships. Some are in ns, related to clock cycles, if some transfer does not start, if another does not finish well, others related to voltage, and others related to resistances or impedances, which obviously have to do with voltage. Following the rules is not so easy, because there are thousands of recommendations, and not all of them coincide. I think that would be a great step to improve a configuration. For example, I will have spent a month trying to lower the tRCDRD to 15 and not to mention 14, but following some assumptions. And I have no way to "hit" without a good calculation. The rayzen Calculator DRAM is very good, but it was outdated, not only does it not go higher than 1800MHz (or MT / s) but if one wants to look for even tighter values, it never takes them. Perhaps there is a calculator that is more self explanatory. I have many doubts left but I keep reading, writing down. I have a Word Document with Veii's recommendations, they are the best! That is why my question about how you got to such a low tRAS, or such a low tRTP, must have a reason, in fact, see how well it worked for me, but like that, I did not learn anything! I take it as a hobby, I have three memory kits, three different mobos, I can try several OC, but I lack that knowledge that I will gradually learn. I confess that it costs me because I am new, but I am 45 years old and I started at 13 with my first online service back in the early 90's, then I was an Engineer in the old Compaq, then HP, Solution Architect, and had all HW certifications and SW. I worked a lot with circuits from a very young age, so I can say that in my life I always did troubleshooting, now I am dedicated to the sales of Software in one of the main German companies, but I am passionate about this and I want to continue learning. I would lack a better guide than values!



So you did´t pass TM5 with SCL 2 and ProcODT of 48? Does it perform better with SCL 4 and lower ProcODT of 40? Againt, in mi mind, I higher ClkDrStr would help to compensate high voltages, like ProcODT to be lower and also vSOC. I am really impress that your first configuration pass almows 50 cycles of TM5, but I don'´t thing it´s enought. Let´s see if it pass Y-Cuncher All test.. ANTA777.. and also the HCI Memtest, I have the deliuve version..

Thanks for your tips!
Anything above 3800 I get a lot of WHEA errors but I think it's just a limitation of my IMC. Your results may be different.
 
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6. Power Supply Idle Control = Low Current Idle (Advanced\AMD CBS\CPU Common Options) Here I had set it to "Typical Power Idle" however it suggest Low Current, do you know what would be better?
It depends on the PSU/BIOS/ETC, keep it "Typical Power Idle" and it is one less thing to worry...
 

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Please don't take it as rude, if i give a bit of critique too this writeup :)
All 3 options are strange and first two misunderstood

Global C-States, does allow the per-core c-states to function and dLDO to function (speedstep , nothing to do with suspended cores)
This means, it allows the cpu to go down to 550Mhz P3/P4 state
This is important to have it enabled.
In combination with CPPC , it allows windows to lower frequency on worse cores and accept dLDO_injector , to smooth the voltage differentiation between cores ~ where each of the little core modules

Credits for the shot to Fritzchen's Fritz AMD/Zen3/Ryzen/Vermeer | Flickr
It needs to be enabled, soo cores can adjust and Vermeer can adjust inside the powerbudget

DF-States are controlling the suspension and also the wake-up from hibernation , triggers the overboosting bug , which causes an "idle to wake-up" crash by badly designed powerplans from AMD & Microsoft, without Peak frequency boosts
This has to be disabled till it get's fixed on 1202 or 1202ABCD :p
* i need to test if it's still an issue on 1202 , after figuring out what the hello kitty is wrong with RZQ and why IMC behaviour is now completely exotic and wrong/broken
~ after the PMTable rewrite & 3 new activated sensors inside FIT

View attachment 2489039
Whole Source

This is what you described as Infinity Fabric Scaling "disabled"
It's on FW level disabled & does nothing from the surface viewpoint (maybe does something internally if you keep it functioning at misson-mode = 0)
and if you ask any engineer about Dynamic FCLK and variable SOC - they will cut the contact with you
I think this topic is under NDA , 4 engineers refused to answer and cut the chat after asking more about ABPDIS and why Dynamic FCLK is disabled internally


You can keep it at 0 mission mode
it won't function except for Renoir & Cezanne, which have STAMP control and are build upon this. Same for ryzen U & G series notebooks ~ there it functions
For Matisse and Vermeer it's disabled since mid of the lifespan of Matisse & Matisse has an 1900 FCLK lock - like Vermeer was attempted to get after Patch C, gladly this nonsense was stopped after Patch D

Before 1200 , soo 1191/1181 and lower, you can run this
1202 seems to set internally X-X-X-2-X-X-X-2
SMU debug shows on 1200 and lower that 2-1-X-X-2-1-X-X is used
One 600mhz link with one 300mhz one. Level 2 and Level 3 where not readable , but 2-2-1 was not accepted by SMU
Currently i test 2-1-1-2/2-1-1-2, as Level3/4 (the last link) is set at 600mhz and used (by FW alone, i had them at auto)
probably 2-1-1-2 could be good, but we'll see, test in progress AGESA 1.2.0.2 is awkward & did a lot of changes

The rest is fine
You can include opening PBO EDC to 400A
It still allows cache to boost till it gets internally limited
and should be reflective on SiSandra MCE , as also on Aida64
But lifting the EDC limit will need a limit on TDC , else it adds to much voltage for allcore and the CPU throttles back
This can be fixed by nearly maxed out negative CO with "lower" but positive vcore offset or just more droopy CPU LLC
Veii! How do you think it might sound a bit rude coming from you? It is an honor to have you here and have an advice or explanation from you. I regret not having entered a while ago to be able to take advantage of more of the time when you were more active, but that's life!

DF-States are controlling the suspension and also the wake-up from hibernation , triggers the overboosting bug , which causes an "idle to wake-up" crash by badly designed powerplans from AMD & Microsoft, without Peak frequency boosts
This has to be disabled till it get's fixed on 1202 or 1202ABCD :p
* i need to test if it's still an issue on 1202 , after figuring out what the hello kitty is wrong with RZQ and why IMC behaviour is now completely exotic and wrong/broken
~ after the PMTable rewrite & 3 new activated sensors inside FIT
Well, impressive explanation! and great picture!! and also the graph. You know why I am disabled it (C-states), because is a "best practice" to avoid the common reboot on iddle, but is not the sotution neigher a workaround. Perhaps going to a less aggressive curve, not per core. all cores -20 or -25, and a little positive Vcore Offset would help to avoid the idle reboot. But one think make me doubt, I´m running SMU 56.45 (and thinking of installing two older versions, before Patch D .. to test if an OC above 4000 or 4000 works better, since today I receive WHEAS constants). I also disabled the DF States, so maybe it help with the Idle reboot, not the C-States.. I will enable it to see if I have some reboots. Do you recommend me to change to an older BIOS than my actual 56.45? I will loose REBAR but I prefer to have a 4000-x-x-x without WHEAs

This is what you described as Infinity Fabric Scaling "disabled"
It's on FW level disabled & does nothing from the surface viewpoint (maybe does something internally if you keep it functioning at misson-mode = 0)
and if you ask any engineer about Dynamic FCLK and variable SOC - they will cut the contact with you
I think this topic is under NDA , 4 engineers refused to answer and cut the chat after asking more about ABPDIS and why Dynamic FCLK is disabled internally


You can keep it at 0 mission mode
it won't function except for Renoir & Cezanne, which have STAMP control and are build upon this. Same for ryzen U & G series notebooks ~ there it functions
For Matisse and Vermeer it's disabled since mid of the lifespan of Matisse & Matisse has an 1900 FCLK lock - like Vermeer was attempted to get after Patch C, gladly this nonsense was stopped after Patch D
Ok, so I´m gonna disable it. 4 engineered refused to unswer you. Wow!

Before 1200 , soo 1191/1181 and lower, you can run this
1202 seems to set internally X-X-X-2-X-X-X-2
SMU debug shows on 1200 and lower that 2-1-X-X-2-1-X-X is used
One 600mhz link with one 300mhz one. Level 2 and Level 3 where not readable , but 2-2-1 was not accepted by SMU
Currently i test 2-1-1-2/2-1-1-2, as Level3/4 (the last link) is set at 600mhz and used (by FW alone, i had them at auto)
probably 2-1-1-2 could be good, but we'll see, test in progress AGESA 1.2.0.2 is awkward & did a lot of changes
Ok, I´m on 1200,right now so I don´t need it, but I would like to try 56.30, I think it´s one the better version to try 4000 Freq, right? So If I´m not wrong should be AGESA 1.9.0.x , and in that case I should use 2-1-1-1/2-1-1-1, To understand, what exacttly do that? I just google it to find the AGESA version and I found you in Reddit :). I always wanted to know, when you refer as Boost in memory, what it is? I never found any Boost on my Asus. I will try your suggestion of maxed out CO to -30 and maybe apply +40mV right? And also LL2? or one of them?

Thanks!!
 
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