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Old crazy guy
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Looks ok?
Yes, looks ok.
Also consider there's a pooling period rate in HWInfo in the sensors configuration.
If you want to really catch almost all the clock variations it should be set to 500ms.
But it will impact the CPu quite heavy so should only be reduced on a spot basis and then set back to default.
And you should select in the main settings Snapshot CPU Pooling to get more accurate results for effective clocks.
 

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Yea, I was looking at it with the rate set to 500ms. Haven't tried Snapshot pooling before though.

@mongoled @ManniX-ITA
Horrible news.... I tested again last night before sleep and to my dismay,

Identical settings as prior night 25 cycle pass = cycle 7, error 1.

Next I tried increasing vdimm from 1.49 to 1.5 as suggested and went to bed. Woke up to a competed 25 cycle test, but errors, 7, 14, 0, 11, 1, 7, 14, 1, 8 .

*I did not increase beyond because the other day when you first mentioned it, I tried 1.51 vdimm and got error 14 after 40 minutes.

I think I may have to try a complete re-work. I've been looking at your and dom's settings and think I may need to fiddle with CADBUS setttings. OR completely re work my RTT's, maybe lower park like you both have.

*When I run the TM5 test I have HWinfo open and msi afterburner. shouldn't be a problem though right? afterburners hw monitor is paused. so it doesn't do much of anything

Going to test CAD_BUS variations now. any and all suggestions welcome

Settings tested last night (vdimm was 1.49 for first test, maybe I should allow it to complete a full run with 1.49 to see what other errors arise)
2514349


Edit:
Tested:
Pictured, 40-20-24-24Cycle 7, error 1
1.5 vdimm25 cycles, UNKNOWN when 1st error occured, 7, 14, 0, 11, 1, 7, 14, 1, 8
1.48 vdimm
60-20-24-24cycle 1, error 10
40-20-30-24cycle 17, 1h45m, error 1 - COULD BE 1.5 VDIMM /w this setting OR 56-0-0
40-20-20-24Cycle 23, 2h30m, error 1, 1, 1 (back to back), then completed to 25 cycles, no other errors
40-20-20-20cycle 4, 20m, error 10
40-20-30-20Cycle 20, 2h, error 2, 2, 2, 0
 

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Default config first (press 1, then 7, then 0). Let it run couple of hours
If it passes in that, the CO is stable?
I’m testing all cores -10 right now, 0 boost override with a tuned PBO
 

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I notice that while effective are precise, reported core clocks are rounded to the nearest 25mhz.
Just set "Cpu snapshot polling mode" checkbox in startup hwinfo window's settings. No need to reduce polling interval.
25 mhz is a frequency resolution for the p-states. Its actually the exact frequency, the core run at. What you see in "snapshot mode" (as i see it) is the COF table formed by SMU firmware, where each COF may be for example, dfs prerounded value. Need double check it though.
 
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Old crazy guy
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Just set "Cpu snapshot polling mode" checkbox in startup hwinfo window's settings. No need to reduce polling interval.
You still need to reduce the pooling interval otherwise it could miss peaks and/or smoothen the current.


The snapshot is a different method to get the data but still relies on the pooling interval.
Instead of being actively queried one by one the counters are written all at once, like dumping the powertable via the SMU.
 

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OMG. error on cycle 23, 2h30m into the test, 3x error 1 back to back. Anyone have insights into what the CAD_BUS testing I'm doing may mean? I've included time of 1st error for all except 1 (overnight test). I figure the ones that go so long must have some similarities / differences to others that would imply or mean something to someone with better understanding

* see post above for the most updated results. I am editing that post with results as I get them
 

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You still need to reduce the pooling interval otherwise it could miss peaks and/or smoothen the current.
Why bother with peaks if you evaluating clock stretching this way, over a period of time, in any case?

like dumping the powertable via the SMU
Why "like" ? ))

And Idk, whether high SMU poll rate might adversely affect its functionality, so unless proven otherwise, I wouldn't use other than default 2s.
 

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OMG. error on cycle 23, 2h30m into the test, 3x error 1 back to back. Anyone have insights into what the CAD_BUS testing I'm doing may mean? I've included time of 1st error for all except 1 (overnight test). I figure the ones that go so long must have some similarities / differences to others that would imply or mean something to someone with better understanding

* see post above for the most updated results. I am editing that post with results as I get them
Did you see my posts about RAM temps and the fans I use etc? Errors late in testing likely due to RAM getting too hot.

My RAM performs really well if I keep it under 40C while stress testing and if you're hitting 50C+, might be a problem. :(

 

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Did you see my posts about RAM temps and the fans I use etc? Errors late in testing likely due to RAM getting too hot.

My RAM performs really well if I keep it under 40C while stress testing and if you're hitting 50C+, might be a problem. :(

Yea, I saw it, also looked at the fans. Pretty cool. How / Where do you mount those fans?
At the moment my case has quite high airflow, it's a lian li lancool ii mesh, with all fan spaces maxed out, 8 incl. the aio.

My ram never exceeds 48.5c, during testing, so it stays below 50 where errors typically develop for b die. It's actually only dimm1 that gets to 48.5c during MT5; max temps are - dimm1 44.5c, dimm2 48.5c, dimm3 45c, dimm4 46c.
 

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Default config first (press 1, then 7, then 0). Let it run couple of hours
Here's almost 6 hours of testing my curve (all cores -10 with PPT 200 TDC 70 EDC 130) with Y Cruncher


2514372
 

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2514374


40-20-24-24Cycle 7, error 1
1.5 vdimm25 cycles, UNKNOWN when 1st error occured, 7, 14, 0, 11, 1, 7, 14, 1, 8
1.48 vdimm
60-20-24-24cycle 1, error 10
40-20-20-20cycle 4, 20m, error 10
40-20-30-24cycle 17, 1h45m, error 1 - COULD BE 1.5 VDIMM /w this setting OR 56-0-0
40-20-20-24Cycle 23, 2h30m, error 1, 1, 1 (back to back), then completed to 25 cycles, no other errors
40-20-30-20Cycle 20, 2h, error 2, 2, 2, 0

Do these results mean anything to anyone? Not sure what to make of them as I don't have a consistent trend, which makes sense as this is about balance.

I'll test the pictured settings at 1.48vdimm in the mean time, if it's clearly worse, then I'll try testing with 1.5vdimm in combination with some of those CAD_BUS variations.
 

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Yea, I saw it, also looked at the fans. Pretty cool. How / Where do you mount those fans?
At the moment my case has quite high airflow, it's a lian li lancool ii mesh, with all fan spaces maxed out, 8 incl. the aio.

My ram never exceeds 48.5c, during testing, so it stays below 50 where errors typically develop for b die. It's actually only dimm1 that gets to 48.5c during MT5; max temps are - dimm1 44.5c, dimm2 48.5c, dimm3 45c, dimm4 46c.
On the mount they just screw on with standard fan screws. 48C is still pretty high, might cause errors. Like I said in that post I get errors going over 40C that under I get no errors under 40C using really tight timings for Dual Rank RAM.
 

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View attachment 2514374

40-20-24-24Cycle 7, error 1
1.5 vdimm25 cycles, UNKNOWN when 1st error occured, 7, 14, 0, 11, 1, 7, 14, 1, 8
1.48 vdimm
60-20-24-24cycle 1, error 10
40-20-20-20cycle 4, 20m, error 10
40-20-30-24cycle 17, 1h45m, error 1 - COULD BE 1.5 VDIMM /w this setting OR 56-0-0
40-20-20-24Cycle 23, 2h30m, error 1, 1, 1 (back to back), then completed to 25 cycles, no other errors
40-20-30-20Cycle 20, 2h, error 2, 2, 2, 0

Do these results mean anything to anyone? Not sure what to make of them as I don't have a consistent trend, which makes sense as this is about balance.

I'll test the pictured settings at 1.48vdimm in the mean time, if it's clearly worse, then I'll try testing with 1.5vdimm in combination with some of those CAD_BUS variations.

Did you look through Veii's error descriptions?
"2,0", "1" all relate to VDIMM.

EDIT: Also keep in mind that to use CAD_BUS setup timings you must use CAD_BUS X-20-20-20, not like in your last 3 tests.
Looks like instability issues between voltage and Memory Training issues (might want to try 40-20-24-20)
Small MB test sizes are refreshes. Be it tRFC refreshes, or mid-transfer timings like tRRD/tWTR , or SCLs

Every timing can be bruteforced, but he has too many error 1 & 0's
1.5v sample was hitting

Likely signal ripple got too worse and RTTs where bad, or rather SETUP timings couldn't cut well, as signal was too noisy
Visible by the remain tests, when voltage dropped ~ signal appeared cleaner

Overall looks like RTTs are not optimal.
I would try to drop RTT_NOM once more and see if you get PCB crashes
When you increase ClkDrvStr , you have to lower/weaken RTT_NOM or lower voltage.
When you lower procODT, you also should lower VDIMM but increase ClkDrvStr or SOC
If SOC is high, generally weaken RTTs and weaken CAD_BUS (all of them) ~ or just weaken VTT_DDR
If SOC is high, weaken the 1.8v rail ~ i feel ASRock's decision with 1.83v on stock, is pretty perfect , replicating the voltage on the ASUS board.
1.82v was fine, but beyond 1.83v i had issues. I didn't have issues if remain voltages where strange or too low (VDDG, SOC)

The Error #0 , refresh stable can also be an issue with powerdown & so also SETUP timings
But can also be overshooting by RTTs
Tho for RTTs, it often is an explosion of errors at the same time , then peace ~ when signal peak is too strong and reflects back, or fully drops out for a sec
RTT_WR is dynamic, it will catch issues and adjust ripple ~ but for it to function either RTT_NOM needs to work or PARK, one of both
Disabled PARK means 0 doesn't mean 240/480ohm. Then RTT_WR takes over

He/She is close, soo keep trying
I still would give tRRD_L a bump at 5
and tWTR_L a bump at 10
Just for good measure
These tRRD's are too low, they will cause issues , not only with 4 dimms not only with "great" PCBs but also on low primaries
They add performance, but primaries mean much more. Pushing them higher can help in stabilizing your lower tRCD_RD
Most of the talk is bout B-Die, the only one with Rev-E seems to be @Veii but it's a way better bin, so not sure if I should try to copy his settings. This is as far as I could get reading the thread.
You can copy & adjust frequency till it's not stable anymore :)
As long as you follow a tCCD_L rule, everything runs on these micron kits.
I want a bit more playing time with them and finally get this tRCD 18 under 4000 to work ~ before writing tCCD_L rulesets in stone
It simply refuses on everything i try ~ feels like doing medical work on a war-person. Strongly handcapped on tRCD and tRFC ~ the micron Rev.E's
I'm close but yet didn't made it.
Here are some examples and collection of past fun

3933 is the furthest i got with tRCDRD 18
And bit more fun
Highest CL12 i got was 3667, voltage did not make any difference - even 1.7 didn't do 💩 to make it run any higher freq
(maybe had already negative effects, as RTTs likely where not suited for 1.7+)

Yep i'm back on the ITX, thunderbolt 4 only runs well with Matisse . . . annoying
Old slower sets:

2514380
Sure i do have
2514379

C9BKV 055M:E vs your D9VPP 075:E

But all rev.E are kind of similar
Just keep in mind, i move from now mostly in the >1.6v range ~ because thermals are no issue when RTTs are set and weaken
Especially taking a look on:

This is 1.64v , 727 was 1.6v (but used 40+ ClkDrvStr)
* i don't really have a directed fan and roomtemp is surely over 26c most of the day (outdoor is 28-30c)
 

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What does it mean if TM5 skips seconds on the timer in the status tab? Is it just a software bug? I didn't get any errors but the timer would look like it skips 1 second every 10 seconds. (For example, 36s to 37s would happen much quicker then a second)

My guess is, it is just desync between gui and the internal timer?
 

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I am farily well mystified by cad bus timings at this point. I could never get anything stable at 0 0 0. And 1 1 1 is waayyyy worse. Anything lower than 46 doesnt seem to post, and anything above 2 doesnt seem to post either 🤷‍♂️. Can anyone shed any light on the cad bus?

2514386



What does it mean if TM5 skips seconds on the timer in the status tab? Is it just a software bug? I didn't get any errors but the timer would look like it skips 1 second every 10 seconds. (For example, 36s to 37s would happen much quicker then a second)

My guess is, it is just desync between gui and the internal timer?
System memory use is nearly maxed. Expect some hesitation or delay.
 

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Might just be a "feature" of the program, then, lol
 
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