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I am farily well mystified by cad bus timings at this point. I could never get anything stable at 0 0 0. And 1 1 1 is waayyyy worse. Anything lower than 46 doesnt seem to post, and anything above 2 doesnt seem to post either 🤷‍♂️. Can anyone shed any light on the cad bus?

View attachment 2514386




System memory use is nearly maxed. Expect some hesitation or delay.
Here are some notes I saved in my excel file from various authors

AddrCmdSetup value can range from 50 - 63
In theory AddrCmdSetup should arrive after CsOdtSetup/CkeSetup, therefore the last two may remain 0 and only AddrCmdSetup between 50 and 63.
You can try Setup 56-0-0 with CAD BUS X-20-24-24. My observations show that this is better:
For example, most Asus boards lock AddrCmdSetup at 61 when we have Zen1 / +, ie. setup times are 61-0-0. For comparison Gigabyte puts 11 by default, but I can change it.
Higher AddrCmdSetup helps for lower ProcODT/ClkDrvStr. But we need to find the right settings with which we have no loss of performance.
Ive been hoping that a "magic" setting combo will appear to allow more peeps to run flat 14s, as has happened with 1T/2T with the 56-56-56 discovery
 

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Hmmm ok, I can certainly run "tighter" timings with 56 56 56 but performance was worse than my "loose" setup now. I'm tempted to revisit and run more tests now.....
 

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Why bother with peaks if you evaluating clock stretching this way, over a period of time, in any case?
Just to say as additional info eheh
That's useful to get the max boost clock with boosttester, for clock stretching is useful the current value
Default 2 seconds is too much and if the core is not steady 100% usage you could get the wrong idea there's stretching

Why "like" ? ))

And Idk, whether high SMU poll rate might adversely affect its functionality, so unless proven otherwise, I wouldn't use other than default 2s.
No idea what exactly HWInfo's snapshot is doing but I strongly suspect is exactly that :p
Do you know more?

I can tell about my testing with the 5950x; at 1 second doesn't make any difference, that's my default.
500 ms if the sensors window is not minimized it has a sizeable hit on performances, minimized very thin
Below that is affecting adversely
In general SMU shouldn't be stressed more than once in 40-60ms but the power table dump is an intensive task
It takes 80-120ms to dump it hence it's better to set at least 200ms between requests or the SMU could crash and the CPU reset
Which is indeed the minimum time suggested by AMD for their crappy RM Monitoring SDK
 

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Final testing dump info dump as I'm heading to bed. Close but no cigar was the theme of the day; even though the pictured settings passed 25 TM5 cycles the other day :unsure:

2514396


All tests done with settings as pictured above aside from the mentioned change
1.49 vdimmCycle 7, error 1
1.5 vdimm25 cycles, UNKNOWN when 1st error occured, 7, 14, 0, 11, 1, 7, 14, 1, 8
1.5 vdimm (repeat)Cycle 6. 33m. Error 3, then ran for 60m total with error 3, 3, (total errors = 3, 3, 3)
1.48 vdimmCycle 6. Error 2, 1, 2, 6, 6, 0, 2
1.47 vdimmcycle 1. error 2, 10, 10 - too low vdimm
60-20-24-24cycle 1, error 10
40-20-20-20cycle 4, 20m, error 10
40-20-30-24cycle 17, 1h45m, error 1 - COULD BE 1.5 VDIMM /w this setting OR 56-0-0
40-20-20-24Cycle 23, 2h30m, error 1, 1, 1 (back to back), then completed to 25 cycles, no other errors
40-20-30-20Cycle 20, 2h, error 2, 2, 2, 0
40-20-24-20Cycle 4. 20m. Error 1. ran for another 12m, 32m total, error 1, 4
RttNom 6 (40 ohm)Cycle 13. 1h20m. Error 3, 3
ProcODT 36.9Cycle 3. 20m. error 3
 

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Overall looks like RTTs are not optimal.
I would try to drop RTT_NOM once more and see if you get PCB crashes
When you increase ClkDrvStr , you have to lower/weaken RTT_NOM or lower voltage.
When you lower procODT, you also should lower VDIMM but increase ClkDrvStr or SOC
If SOC is high, generally weaken RTTs and weaken CAD_BUS (all of them) ~ or just weaken VTT_DDR
If SOC is high, weaken the 1.8v rail ~ i feel ASRock's decision with 1.83v on stock, is pretty perfect , replicating the voltage on the ASUS board.
1.82v was fine, but beyond 1.83v i had issues. I didn't have issues if remain voltages where strange or too low (VDDG, SOC)

The Error #0 , refresh stable can also be an issue with powerdown & so also SETUP timings
But can also be overshooting by RTTs
Tho for RTTs, it often is an explosion of errors at the same time , then peace ~ when signal peak is too strong and reflects back, or fully drops out for a sec
RTT_WR is dynamic, it will catch issues and adjust ripple ~ but for it to function either RTT_NOM needs to work or PARK, one of both
Disabled PARK means 0 doesn't mean 240/480ohm. Then RTT_WR takes over

He/She is close, soo keep trying
I still would give tRRD_L a bump at 5
and tWTR_L a bump at 10
Just for good measure
These tRRD's are too low, they will cause issues , not only with 4 dimms not only with "great" PCBs but also on low primaries
They add performance, but primaries mean much more. Pushing them higher can help in stabilizing your lower tRCD_RD
Thank you for this info. I will begin testing with it tomorrow. The only point I currently debate, is if I'm close, do I just keep pushing till I find stability with the current settings?
OR do I scrap it all, and re do the procODT, RTTs, etc....
 

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Seems good so far, gonna let it run all night when I go to bed.

View attachment 2514364
Re Y-Cruncher long duration runs, just be aware that Y-Cruncher will tax the CPU hard, some people dont like high temperatures for some reason, just wanted to point that out. I have in the past run over 8 hours Y-Cruncher though through experience if it passes the first 3 hours ive never seen an error after that ....

Can you post your CO and boost override settings for this run ?

Yea, I saw it, also looked at the fans. Pretty cool. How / Where do you mount those fans?
At the moment my case has quite high airflow, it's a lian li lancool ii mesh, with all fan spaces maxed out, 8 incl. the aio.

My ram never exceeds 48.5c, during testing, so it stays below 50 where errors typically develop for b die. It's actually only dimm1 that gets to 48.5c during MT5; max temps are - dimm1 44.5c, dimm2 48.5c, dimm3 45c, dimm4 46c.
You should put some fans just as a troubleshooting tool to rule out that it is heat accumalation that is the cause of the inconsistencies, if you put the fans and there are no changes to the consistency of the errors then you will then know its not heat related.

Here's almost 6 hours of testing my curve (all cores -10 with PPT 200 TDC 70 EDC 130) with Y Cruncher


View attachment 2514372
Same as explanation to Drevi, you would have better overall system performance/efficiency tuning each core seperatly, but its fine if you go all core CO, you just need to invest more time

:D

Thank you for this info. I will begin testing with it tomorrow. The only point I currently debate, is if I'm close, do I just keep pushing till I find stability with the current settings?
OR do I scrap it all, and re do the procODT, RTTs, etc....
Im confident that if you drop tRCDRD to 16 you can call it a day, you are now in the realms of chasing the white rabbit

:D

I spent most of yesterday trying to find a magic combo for my bad stick but did not come up with anything.....
 
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Running y-cruncher standalone is not enough if you are using PBO.
It will run on all cores, lower frequency.
To properly test CO you need to check with CoreCycler, one single core at a time.
And also avoid using at all the PC if possible.
Otherwise the core under test will slow down in frequency.

You can also use y-cruncher with CoreCyler.
But it's better to use as well Prime95 with CoreCycler and run all the FFT sizes from 4K to MAX:

Code:
# Smallest:     4K to   21K - Prime95 preset: "tests L1/L2 caches, high power/heat/CPU stress"
# Small:       36K to  248K - Prime95 preset: "tests L1/L2/L3 caches, maximum power/heat/CPU stress"
# Large:      426K to 8192K - Prime95 preset: "stresses memory controller and RAM" (although dedicated memory stress testing is disabled here by default!)
# Huge:      8960K to   MAX - anything beginning at 8960K up to the highest FFT size (32768K for SSE/AVX, 51200K for AVX2)
# All:          4K to   MAX - 4K to up to the highest FFT size (32768K for SSE/AVX, 51200K for AVX2)
# Moderate:  1344K to 4096K - special preset, recommended in the "Curve Optimizer Guide Ryzen 5000"
# Heavy:        4K to 1344K - special preset, recommended in the "Curve Optimizer Guide Ryzen 5000"
# HeavyShort:   4K to  160K - special preset, recommended in the "Curve Optimizer Guide Ryzen 5000"
Of course it takes a huge amount of time.
But running "All" with SSE/AVX/AVX2 is the only way to be 100% all is working fine.

You should run at least 20m cycle per core (thermal equilibirum):

Code:
# - Prime95 "Smallest":     4K to   21K - [SSE] ~3-4 Minutes   <|> [AVX] ~8-9 Minutes    <|> [AVX2] ~8-10 Minutes
# - Prime95 "Small":       36K to  248K - [SSE] ~4-6 Minutes   <|> [AVX] ~14-19 Minutes  <|> [AVX2] ~14-19 Minutes
# - Prime95 "Large":      426K to 8192K - [SSE] ~18-22 Minutes <|> [AVX] ~37-44 Minutes  <|> [AVX2] ~38-51 Minutes
# - Prime95 "Huge":      8960K to   MAX - [SSE] ~13-19 Minutes <|> [AVX] ~27-40 Minutes  <|> [AVX2] ~33-51 Minutes
# - Prime95 "All":          4K to   MAX - [SSE] ~40-65 Minutes <|> [AVX] ~92-131 Minutes <|> [AVX2] ~102-159 Minutes
# - Prime95 "Moderate":  1344K to 4096K - [SSE] ~7-15 Minutes  <|> [AVX] ~17-30 Minutes  <|> [AVX2] ~17-33 Minutes
# - Prime95 "Heavy":        4K to 1344K - [SSE] ~15-28 Minutes <|> [AVX] ~43-68 Minutes  <|> [AVX2] ~47-73 Minutes
# - Prime95 "HeavyShort":   4K to  160K - [SSE] ~6-8 Minutes   <|> [AVX] ~22-24 Minutes  <|> [AVX2] ~23-25 Minutes
# - y-Cruncher: ~10 Minutes
# Default: 6m
runtimePerCore = auto
So use Auto to test all FFT or set it to at least 20 minutes if the cycle will last less, like with Small set.

I gave up after running all FFT in SSE, too much time on a 5950x :p
One day I'll test as well AVX and AVX2.

You should also consider CPPC Preferred cores.
In a normal usage only the first best 2-3 cores will ever run at full speed tested with CoreCycler.
Once the scheduler will distribute load and threads to the other cores the total load will be higher and they'll run at a lower frequency.
So if you want to save some time you could take a shortcut and test thoroughly only the best ones.
Though I fully agree with these sentiments, the key words out of all this for me is the following

To properly test CO you need to check with CoreCycler, one single core at a time.
I do wonder if AMD "properly" test their CPUs in the manner you have described above, i.e. recycling each core through every possible combination of instruction set to see where a crash will be induced. Looking at posting history since Zen's release I highly doubt they do!

So the burden of how to define the word "proper" is down to the end user, obviously the "proper" way is to do what you have said above.

Now, for me personally, I prefer to spread my testing across a plethora of tests, some more lengthy than others, hence the reason I said at the sentance you quoted

After Y-Cruncher is stable I do another CoreCycler, then use the system normally for an extended period of time to possibly catch idle crashes before moving to other types of stress tests
I do take it upon myself (rightly or wrongly) to "evaluate" the poster and their posting history to determine how much information to feed to that particular poster, as too much information for most people is not a good combination for learning!

If after giving information that may be slightly "sparce" in the eyes of others and seeing that the poster I am giving information is open to receiving more info, its only then that I may go into more detail if I feel it is of benefit to the poster.

Some people may not agree with this methodology, though it has served me well in this journey through life

:)
 
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I do wonder if AMD "properly" test their CPUs in the manner you have described above, i.e. recycling each core through every possible combination of instruction set to see where a crash will be induced. Looking at posting history since Zen's release I highly doubt they do!
I'm not so sure they are so thoroughly.. they probably have some optimized code that works 99% of the times and takes a fraction of that time. Costs :D

Now, for me personally, I prefer to spread my testing across a plethora of tests, some more lengthy than others, hence the reason I said at the sentance you quoted
Yes, what I mean for proper it's about running a single core at max frequency.
When you change the CO count to negative the VID will be lower and the frequency higher (most of the times).
You have to test load on a single core and not an all-core test like y-cruncher (without CC).
That's also needed but on a final step.

Otherwise, which is what I see happening most of the times, after a few weeks the poster comes back with: I was watching a video on Youtube with Chrome and my PC suddenly rebooted, could be my CO config?

And it's almost always that, cause they never tested this scenario.
Testing with Geekbench 5 is helpful but it can easily miss instabilities with 2nd/3rd best core running the ST benchmark.
CC or OCCT with CoreCycling are really a must to ensure stability with CO.

In general I agree with your methodology :D
But in this case I think it's better to be clear that is really needed to test each core, at least the best ones, separately.
Otherwise the risk of random reboots even after weeks is very very high.
 

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I'm not so sure they are so thoroughly.. they probably have some optimized code that works 99% of the times and takes a fraction of that time. Costs :D



Yes, what I mean for proper it's about running a single core at max frequency.
When you change the CO count to negative the VID will be lower and the frequency higher (most of the times).
You have to test load on a single core and not an all-core test like y-cruncher (without CC).
That's also needed but on a final step.

Otherwise, which is what I see happening most of the times, after a few weeks the poster comes back with: I was watching a video on Youtube with Chrome and my PC suddenly rebooted, could be my CO config?

And it's almost always that, cause they never tested this scenario.
Testing with Geekbench 5 is helpful but it can easily miss instabilities with 2nd/3rd best core running the ST benchmark.
CC or OCCT with CoreCycling are really a must to ensure stability with CO.

In general I agree with your methodology :D
But in this case I think it's better to be clear that is really needed to test each core, at least the best ones, separately.
Otherwise the risk of random reboots even after weeks is very very high.
The only slight concern I have with this is that even if we assign an affinity to a process on a core and hammer that core across various workloads to maximise the peak frequency, this type of simulated testing is not what occurs in most "real World" scenarios.

Its the "idle" boosting that is often an issue with CO, when we use tools such as Prime95 to cycle cores they dont mimick this type of scenario but full single load core scenario.

Maybe using boost tester for several hours is a better test for CO ..........??
 

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Maybe using boost tester for several hours is a better test for CO ..........??
No you really need some workload, like Prime95 or y-cruncher.
It's not like real workload but so far I've never seen an instance where fixing it with CC would not fix also random reboots.
Usually it's even fixed before getting it fully stable with CC...

Unless the issue it's not pure core stability but some Over Boosting issue where the core jumps to crazy high frequencies from idle.
But that should be fixed by other means with different settings (that's wher DF C State disabled can help) or a better power plan.
 

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Well yeah, thats where you would re-tweak your CO values, thats if you actually want to increase your single core top frequency.

Im at +200, with +5 | -3 | -7 | -6 | +6 | -9

All core boost 4850, CB23 @4600, Prime95 Small FFTs @ 45xx

If you are really lucky you will get the below

😂 😂

View attachment 2514337
I could probably do +200 PBO with some adjustments to the CO values, but 4.6MC, 4.7SC is good enough and temps and noise are far better vs +200PBO which I ran for a day with -30 CO before I noticed instability. I also undervolt and underclock my GPU to make it silent. Noise and low temps are more important than a few percept performance :)
 

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I think the set is flawless :)
Only tRP would need to be 12 , but this requires more voltage - and more voltage means different RTT

Also it looks like it wants ClkDrvStr a bit ~ but your procODT is far lower than usual
This likely is the reason for low cLDO_VDDP

Test the timings and adjust procODT up and down 28-34ohm , 3 options one of 3 will only have zero variation on Aida64. 0.3ns or more is instability and autocorrection
Formula you used for tRAS is tRCDmax + tCCD_L or tBL
Currently it was used as 14+6=20 (bios issue soo 21)
tRC is tRCDWR+tCWL+tWR+tCCD_L or tBL
8+14+12+6=40

Both are issues because tRP + tRAS does not equal tRC
I think your tCCD_L is 6 here
Try maybe this first
(2T needed 1.54~, 1T needed 1.6v)

Next one is this but with your own RTTs

Looking at it now, it looks amateur 🙊
Too high tRDWR high SD,DD and not even tWR 10. Also ignore GDM, this is a weak preset but timings are ok i think

Buut you can also try to go for tCL 13 :^
Just need to start running tCKE and RTT_WR , in order to utilize voltage beyond 1.6v
Your cooling is far better than mine :)
Hello, I tested the value you asked me to try recently. To run the BIOS memory voltage 1.6V 1XTFAW, you asked me to do TRAS + 1 = TRC, and I was wondering here. I wonder what formula TRRDS, TRRDL, TFAW, TWTRS, TWTRL used. And what should we do with the 3800 14-10-14-12-26-38 that you asked me to test at the end, "RTT" 0/0/5, 7/0/6? Do you need to perform a voltage of 1.6V for 1T memory voltage? And I wonder what the most efficient practical use of the CL14 3800 is among the most effective. Thank you so much for always teaching me!

14-14-14-14-28-29. 1T 1.6V
View attachment 2514342
[/QUOTE]
Do you really need 1.22v soc for 1900 fclk? It eats into the CPU budget. On my setup 1.06V is more than enough for 1900 fclk.
 

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Hello, I tested the value you asked me to try recently. To run the BIOS memory voltage 1.6V 1XTFAW, you asked me to do TRAS + 1 = TRC, and I was wondering here. I wonder what formula TRRDS, TRRDL, TFAW, TWTRS, TWTRL used. And what should we do with the 3800 14-10-14-12-26-38 that you asked me to test at the end, "RTT" 0/0/5, 7/0/6? Do you need to perform a voltage of 1.6V for 1T memory voltage? And I wonder what the most efficient practical use of the CL14 3800 is among the most effective. Thank you so much for always teaching me!

14-14-14-14-28-29. 1T 1.6V
View attachment 2514342
Do you really need 1.22v soc for 1900 fclk? It eats into the CPU budget. On my setup 1.06V is more than enough for 1900 fclk.
[/QUOTE]
In my case, soc voltage is enough to perform 1.1vcl143800. The timing we performed now was the same as teacher "veii"'s. The timing of my actual use is as shown in the picture below.
2514403
 

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I could probably do +200 PBO with some adjustments to the CO values, but 4.6MC, 4.7SC is good enough and temps and noise are far better vs +200PBO which I ran for a day with -30 CO before I noticed instability. I also undervolt and underclock my GPU to make it silent. Noise and low temps are more important than a few percept performance :)
Yeah, I dont notice any difference when using 200 mhz or less with regards to noise or temps as its only single core that is going to boost slightly higher and being on water it makes no difference.

So I already have low temps and low noise

:)

Obviously you have chosen whats best for you.

:)

Vcore soc 1.112v
Dram 1.4v
CPU LLC auto
Soc LLC high
CO -15 -20 -15 -5 +3 -20
PBO +200mhz
PPT/EDC/TDC motherboard
Scalar auto
Thats an excellet sample 5600X!

Can you tell me what you score with CB23 ?

Looking at those CO values and settings you posted you should be getting close to 12300 if temps are not an issue for you and everything is tweaked correctly

:)
 

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Funny to wake up to see you two, @mongoled and @ManniX-ITA talking about CO and CC. I just ran that test last night to confirm my curve.

Ran ALL FFT's for 65m/core, so it would complete all FFT's and loop a tad. Still waiting on 2 cores to finish but likely will, everything else has from previous settings.

My settings are, 250 PPT // 175 TDC // 185 EDC // +200mhz boost // Scalar auto (1x)
Core - Logical CoreCurve Offset
0 - 0 / 1-19
1 - 2 / 3-18
2 - 4 / 5-30
3 - 6 / 7-12
4 - 8 / 9-29
5 - 10 / 11-30
6 - 12 / 13-18
7 - 14 / 15-30
8 - 16 / 17-24
9 - 18 / 19-30
10 - 20 / 21-28
11 - 22 / 23-30
 

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i do have a question about voltage settings. I stumbled upon this post from @Veii from 7 months ago. Does this ruleset still hold true (40mv stepping) and if so, do i need to apply it for the get or set value of VSOC?

I did not exactly apply those rules to my current setup as i was not aware of it. It is 100% stable though. But for the future (going up with IF) it would be good to know
 

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Has anyone else had a CPPC-Preferred core order to
Change in what order cores are chosen?
Mine used to be 4-6-1-2-3-5 now it's 1-2-3-4-5-6
I'm unaware that I've updated any drivers, windows log doesn't show any driver updates, just definition updates. (could it be bc of curve offset?)

(Using occt info to show this info) unsure if it reads correctly or not.
Is this normal, how are these CPPC cores chosen?
(Am now running a per-core offset) so no longer running the all core -30 +50mv offset. (Running amd voltage option inside bios as well. Sil quality is still 80 but no WHEA 18s in quite sometime. Turned off df states, is that a reason CPPC changes?
Edit-Will add pics of new core order, once I'm home-
2514452

(EDIT-UPDATE)
2514453
 

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Thats an excellet sample 5600X!

Can you tell me what you score with CB23 ?

Looking at those CO values and settings you posted you should be getting close to 12300 if temps are not an issue for you and everything is tweaked correctly

:)
11950-11970. I have a CLC280, runs CB23 at 80°.
 

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