Now i'm having some fun...
Error #2 and #6 mostly relates to "not enough current"Still having error 2, 6 and 12
Should i use 2T instead?
Fun indeedNow i'm having some fun...
Yeap, is a A1 PCB, Hynix DJROn your point i think you just overvolt it - but i don't know
Haven't seen people struggle with CL15 thaat much, on such low MT/s
Do you remember your PCBs ?
Got it, i'll work hard on it.Generally, you only fight now with your powering issues, soo we'll see what can happen
If you don't resolve them, your primaries won't drop magically
Actually i've tested 16-20-20-40-60 and it worked stable, but i want to continue the jorney to "Find the missing MB/s/latency".Why don't you run 16-20-20-20-40-60 ?
Would be soo much easier & either work away tRCD 20 or up to 3800MT/s
Balancing high tRRD is not easy
my tCCD_L is 5ns (7 clock i guess?) so tFAW would be 7xRdds?And your tFAW continues to be bad , even tho i told you to figure out tCCD_L from the bios and use this = tRRD_S * tCCD_L = tFAW
I can lower CLDO_VDDP until 820mv, but i can't lower SOC and VDDG_IOD voltages lower than that because my Matisse just randomly restarts.Seeing you can actually post and run this with 1.42v - 1.5v is far too much & you have issues elsewhere. You where overvolting the whole time as it seems
Give more procODT a try. I just now notice you are on Matisse ~ far less cLDO_VDDP , far less VDDG_IOD (wonder if i haven't told you)
And your tRTP or tWR is wrong. If you really use *8 here , then you need to continue this scaling = tRTP 8, 16. Same for tWR, 16,32 and so on
more values work ~ but i have to re'mention it
Probably even gigabyte has an SPD-Z tool (named differently) that deciphers Intel XMP ~ inside the biosmy tCCD_L is 5ns (7 clock i guess?) so tFAW would be 7xRdds?
Stay with 900mV then, even DRAM calculator mentioned thisI can lower CLDO_VDDP until 820mv, but i can't lower SOC and VDDG_IOD voltages lower than that because my Matisse just randomly restarts.
Is 7 clocks, i used the ROG program to see it.Probably even gigabyte has an SPD-Z tool (named differently) that deciphers Intel XMP ~ inside the bios
It likely is different each frequency, but you can use it - yes
Either 4* or tCCD_L *
Apparently increase tRFC had decreased the amount of errors, just with error 4 for now..Stay with 900mV then, even DRAM calculator mentioned this
More is not needed. Early on people could drop it to 700mV.
VDDG IOD and SOC you'll figure out together with y-cruncher
OC'ing T-Force 4133 cl18 bottom part of the post, but i think you've read it already
50mV stepping or 75mV , but 75mV doesn't always work
Again gonna need your help guys.
Probably an air conditioner, if the room keeps getting warmer and warmer on such long testsIt's like a never ending story, it seems to be almost stable though, so I am sure I am just missing that little thing that will push it stable ! Any idea what could help ?
Temperature is pretty good, stable around 24-25C during the day and during the night tests it's actually going down.Probably an air conditioner, if the room keeps getting warmer and warmer on such long tests
or an UPS if house current is the issue
Dropping voltage doesn't seem to help youAt that point, would you consider the single error 4 to not be an issue, knowing it appeared at 58 cycles ?
Or go with "Vdimm at 1.445 instead of 1.45
What's the difference between tCKE 0 and tCKE 1? Do both qualify as "tCKE not used"? For pretty much anything above XMP my board sets tCKE to 1 if on Auto (meaning my whole progress was based on this setting).Usually no, tCKE in combination with RTT_WR makes issues
Same as CAD_BUS TIMINGs do ~ but they coexist together with a lot of work
RTT_WR changes NOM and PARK behaviour once you enable or change it's strengthness
I do have a feeling /2 requires high VDIMM-IN to even function, but /3 has to run close to always
Using RTT_WR generally has a RTT_PARK range. Barely any influence to RTT_NOM
If WR trows errors ~ it's because WR keeps autocorrecting and something bothers it. Be it too low ClkDrvStr , tCKE usage or SETUP Times usage
If it fully refuses to post - either PARK is too strong , or non existent
I'd need an example of what doesn't work for you
I'm sorry, I don't know.What's the difference between tCKE 0 and tCKE 1? Do both qualify as "tCKE not used"? For pretty much anything above XMP my board sets tCKE to 1 if on Auto (meaning my whole progress was based on this setting).
I'll take any info I can get so I appreciate the response!You won't like this reponse
cLDO_VDDP is far to high
Match it as absolute minimum with VDDG CCD, which if really stable on stock ~ looks fine at 950mV
It is influencing at what MCLK you can post but lower is always better ~ as it allows for lower procODT to function (if remain powering is correct)
Should be 4x8GB Samsung B-dieIs this 4x8GB Micron Rev.E ?
Or maybe Hynix CJR ?
I'll try to mess around with some of these tonight. Per my above zentimings, I did manage to get GDM off 2T.You want to push ClkDrvStr to something along the lines of 30-20-30-20 for the start
Maybe 40-20-30-24 if the board struggles with 4 dimms
You also want to work GDM away and start your foundation as GMD off 2T ~ yes it's faster , and saves time for you
Give SD,DD's a try as 1-4-4-1-6-6 (tRDRD = 4-4)
In the ASUS Bios go to Tools - ASUS SPD-Z , disable first both armory crates and other asus spyware (if something more is left) & read out the XMP profiles
The Bios will generate tCCD_L value for you. Remember it , it is important
Check all 4 dimms if they have the same tCCD_L value
If it's 6, then use tRRD_S * tCCDL (6) = 42 for you.
If it's 7 , then you likely are looking at 49 as a value
Let us know which ICs these are , then we can talk about a baseline
For tRAS as a baseline you want tRCD*2 + tCCD_L . This will always work, doesn't matter how bad the kit is.
Then tRC = tRP + tRAS (which will also always work if tRAS is correct to begin with)
for those to be B-die they act just like the C-die set i had. whichThey are all labeled as ver 4.31(Corsair). It was actually one of the first things I checked when I received them.
Yeah TM5 and y-cruncher seem to be the best ways to "punish" memory to make sure it is truly stable. Even then some TM5 profiles seem to push memory a bit more and/or can find out instability better than others.That's what auto set me to - 43.6, 24/24/24/24.
HCI Memtest is 2000% stable though.
Couldn't stabilize tRCDRD at 16, no matter what voltage I threw on it
P.S. Made my assumptions back from my intel tests
That is vDIMM 1.425.
Curios what you meant by "broken" ))inspect more of our brolken dual ccd units