[anta777]

Best test for compare - corona benchmark.

WTRL=7

 

[Audioboxer]

Could not get tWTRL=6 to boot whatever settings i tried.

But i managed to lower tRAS by 1 to =22 -> tRC=34 -> tRFC=221
Is this the correct formula to calculate tRFC, do this look okai ?
View attachment 2527501


Do you have a very bloaty windows install ? Everytime i see a screen with ~800mb used in the start of TestMem.. 800*32= is only 25.6 gigs.
When i start testmem with chrome with 20 tabs and lots of other programs open in background, i get something like ~912*32

How much stuff do you have running after windows restart ?
This is how my windows looks 2minutes after restart: (need 2mins to start everything in background)
View attachment 2527503 View attachment 2527505

Btw, i found SCL=4 to be faster then SCL=2 in dram calc bench.
SCL=2 gives lower read speed but higher write, but in the end SCL is faster.


Get 100% the same with asus bios also..



Very hard to test the differences at this point, but i think the fastest on my setup is:

tRDRDSD=4
tRDRDDD=2
tWRWRSD=6
tWRWRDD=4

Believes it gives a little higher write speed then 4/4/6/6

You could say so, I guess

Though I have firefox open when I took that screenshot and it can be a bit of a memory hog. I obviously don't have it running when I run TM5. I'll restart shortly and get a picture from a fresh boot.

Interesting on the SCLs, I've always just ran 2 because "it works".

Tbf I got my best membench with them at 2.

196 processes

@domdtxdissar have you cut down on Windows services as well?

 

[umea]

Hearing for the first time, that it's dangerous to run X voltage for Y test (for memory)
I daily 1.65v, it was a good sweetspot.
Can pick between 1.64-1.69v. Afterwards the ICs hardcrash
On Rev E till 1.72v before they hardcrash, but haven't notice any positives in running it beyond 1.66v

A0 PCB didn't like anything beyond 1.54v
It was dangerous to keep pushing it and lost memory channels
Then RTTs where remade/redesigned & i can daily higher voltage
But voltage ≠ Amperage arriving
Soo VDIMM ≠ Heat , not directly

1.65v set runs cooler to the touch than 1.51v at "old public RTTs"
Also as voltage helps , i see no reason not to run it
Couldn't extend so far beyond 1.69v. No RTT combination
Couldn't change RTT_WR to something stronger either.

EDIT:
All examples are stability oriented
XOC and Suicide-Runs (scores), are another topic
I don't participate in such

well, that was my knowledge based on what people said over on reddit (useless) but also that github overclocking guide. i guess it makes sense that if B-Die can run higher than "suggested" voltages then others can too.
dropped tRAS and tRC ... time for 21/35. don't seem to be able to get tcl 13 and trp 13 to run properly yet but that's next step

 

[PJVol]

hence the reason I use 1usmus v3 config, as so far this is the only config that gives us an inkling on where we should be looking to change things to stop memory errors.

Not to argue which config is better, I just wanna say the following:
May be I am tooo stupid that I wasn't able to see how "error # descriptions or hints or inking or whatever" can help finding the wrong timing or impendance set.
Moreover, quite often it hints to the opposite of what I should have done to fix them, for example in a half of the cases the description of the error says "overheating or excessive voltage" when both weren't even close to where I should have start to worry.
So, I have serious doubts it may help me to find where I was mistaken, at all, unless some one prove my stupidity and blindness.

PS: I still using 1usmus v3 config, cause it's fast (have neither will nor patience to run these in hours)

 

[domdtxdissar]

Best test for compare - corona benchmark.

WTRL=7

Very small margins.. Done at static allcore OC

"Baseline" settings:

Score = 12198900
Score = 12190300
Score = 12118570 (outliner)

"Baseline + DD's at -2 (6/4/4/2) <-- Seems to be the fastest for me

Score = 12274400
Score = 12262300
Score = 12205300

"Baseline + SCL2"

Score = 12262000
Score = 12193700
Score = 12186600

"Baseline + SCL2 + DD's at -2 (6/4/4/2)"

Score = 12266000
Score = 12251800
Score = 12218200
Score = 12198900

DD's at 1 gave very low results. (6/1/4/1)

tWTRL=7 don't boot

@domdtxdissar have you cut down on Windows services as well?

Running a sophia script slimmed windows

What numbers are you gettinging in the corona benchmark ?

 

[Enferlain]

mongoled
Tm5 can detect only three kinds, but each timing separately.
Personally, the config 1usmus is enough for you.
You deserve it.

I get error in 6 and 12 so those aren't related to your config I guess

Why thanks for leaving your ego on the table....

And subsequently telling anyone who has not worked out your error codes as being stupid.

Maybe thats why you decided not to answer the question

🤣🤣

I don't think it's ego, just language barrier. Guy means the errors outside of what he listed are the same as the other configs

 

[anta777]

My new config for tm5 - absolut.

absolutnew.cfg

bit.ly

For 6-core processors time in main section in config need to increase 1750%.

 

[SneakySloth]

My new config for tm5 - absolut.

absolutnew.cfg

bit.ly

For 6-core processors time in main section in config need to increase 1750%.

Thank you anta777. How many cycles of this should we be running?

 

[anta777]

3, it has already installed

 

[TimeDrapery]

@anta777

You think this new config will catch whatever this Universal config didn't?

That seems like a lot lower percentage for Karhu to error at for TM5 not to report an error

@mongoled

It's okay dude, I'm stupid too 😂😂😂😂😂

 

[domdtxdissar]

Seems like ~1 hour runtime per cycle with 32 gigs ram
Last part is much faster then first..

36min for 1 cycle with 32 gigs memory

Right on time, 2 cycles in 1 hour and 12mins

 

[anta777]

TimeDrapery
I hope.

 

[TimeDrapery]

TimeDrapery
I hope.

@anta777

Me too 😂😂😂😂😂

Thanks for coming through in here and sharing all this with us, that's righteous of you

 

[TimeDrapery]

TimeDrapery
I hope.

@anta777

Also, to be clear, alongside your test config you recommend tightening timings in a certain order so as to associate errors with timing values to change?

 

[anta777]

True

 

[MrHoof]

For 6-core processors time in main section in config need to increase 1750%.

For 8-12-16 cores 1250% is fine? Why only a diffrence for 6?

 

[anta777]

16 threads -1250% (the config was written)
24 threads - >=830%
32 threads - >=625%
12 threads - >=1670%

 

[TimeDrapery]

True

@anta777

Dope I'll reset and work it in the order you describe

 

[anta777]

Ok, only primary timings and tRFC - 3 cycles test, another enough 1 cycle.

 

[SneakySloth]

Ok, only primary timings and tRFC - 3 cycles test, another enough 1 cycle.

Just a quick question, should all DDs be 1 if we're using 4 sticks? And then all DD = SD? Just trying to figure out what else I can reduce here