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Any idea on how to lower TRCDRD from 17 to 16? 16 gives me instant errors on testmem5 even at 1.55v :(
just pay2win by trading out your flare-x kits for Patriot Viper 4400 sticks which actually work great in 4x8
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as showcased by some gentleman whose name escapes me at the moment, but I'm sure he's still around:
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They also work fantastic alongside the Viper 4000 16-16-16 sticks in a 4400-4000-4400-4000 (A0-A1-B0-B1, Bad-Good-Bad-Good slot) config on z690, but I don't know if you can make them work well on AM4 without running different RTT Park (Park/5 on A0/B0, Park/6 on A1/B1) values for the different slots.
 

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Overclock the World
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and lengthen tRC by one clock
tRC is not lengthened on AMD
It will either elapse in the correct time or will be repeaten at the same full ! delay
tRAS will only happen if sensing units decide that enough charge is left and data from X row has been secured before destructive read
this delay before tRP is dynamic but tRP decides the minimum time of it. *
Sometimes tRAS doesn't need tRP+tRCD delay , if cells have enough charge

tRAS is also not lengthened and not cut, also not auto corrected ~ not directly
tRAS only happens after MSR allows it, which is only after cells have enough charge and everything is secured
If they are not, memory will inject independent-length delay and/or insert tAL calibration delay + tRP delay additional dynamic latency (tAL delay) ~ till everything passes check. Only then tRAS is done and tCAS

tRAS can be missed and has lower hitrate, hence delay is longer and usually tRP (virtual added delay before row [p]recharge)
But in general tRAS and tCAS are identical. Identical priority and identical action
Just again, tRAS is either enough or it's "stopped and waited" , then tRAS elapse (error can happen if allowed tRAS delay still is too short ~ there is no extension or stretching)

tRC same like tCWL. Virtual delay
Just well timed to utilize parallelism ~ but hence read is destructive, a (charge check) before & after ! , has to be done
It's "fine" to let it float half charged and/or stack charge // but these are exploits of auto repeat delay.
tRC will (repeating myself) auto repeat, but not timebreak and not shift.

EDIT:
* dynamic delay before tRAS will happen and has no direct name ~ maybe just tAL (AL is also a combined name, of several actions calibrated on boot)
tRP is the title that it was given which controls some of the borders. But at the very end, DIMM control unit & vendor settings are intelligent enough (mostly)

EDIT2:
tRAS "can" be as low as possible, but by this time people should know that lower is not better
Efficient transitions are ~ which is simply a result of testing testing testing :)
I still don't like to split Read and Write delay paths , and cut them down ~ but that's just me
Soo tRAS optimal is either tRCD *2 or tRCD+tRTP (absolute minimum, but doesn't guarantee good efficiency)
 

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I need some advice on upgrading to a 32GB kit as I've been out of touch with new memory now available since purchasing FlareX's back in 2017
I run a C6H with a 16GB kit (snip attached below) and recently installed a 5900x.
I'm happy with current performance but hoping to run a 32GB kit at 3800 c14 and maintain something very close or hopefully better than current setup.

I prefer G-Skill but may consider others depending on what the masses tell me.
So far I'm looking at F4-3600C14D-32GTZNA G.SKILL Trident Z Neo Series 32GB (2 x 16GB) 288-Pin PC RAM DDR4 3600 (PC4 28800) Intel XMP 2.0 Desktop Memory Model F4-3600C14D-32GTZNA - Newegg.com
Also looked at Royal's etc and can't decide where to draw the line. The FlareX have been awesome for me but feeling I need a change to play with lol.

Again feeling behind in the times knowledge wise on the memory topic of gen3, is this the way to go (2x16 neo's) or maybe seeing C6H is T-Topography is there a noticeable performance gain going 4x8 over 2x16?

Any opinions are highly appreciated.
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Again feeling behind in the times knowledge wise on the memory topic of gen3, is this the way to go (2x16 neo's) or maybe seeing C6H is T-Topography is there a noticeable performance gain going 4x8 over 2x16?
T-Topology is better with SR
But 4 dimms increaes the chance of bad batches. RTTs will be different too
B2 (A2) DR PCB on T-Topology is suboptimal but workable
Better to go with 4x A1 or A0 PCB and work on RTTs ~ than increase strain
Unless you plan to update away from the C6H

Ax = SR
Bx = DR
 

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Hi, I posted here once. I got no problem with 2T 0 WHEA for 24/7

but I wanna go pure 1T 0-0-0 .
can any pro guide me to 1T?

currently vdimm 1.545v (air cool)
PPT TDC EDC=114-72-105
Boost Override CPU =50Mhz

I've tried set RTT to 6-3-5/6-3-6/6-3-7
ClkDrvStr to 40-20-30-20/40-20-30-24 and raise my vdimm to 1.6v/1.63v Vsoc 1.18v after vdroop

safe to boot 1T 0 WHEA. once I start TM5 tons of error comes out within a minute. HwinFo64 still 0 WHEA but I shut TM5 immediately to avoid BSOD
 

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lol, flashed AGESA 1.2.0.7 beta for my Unify-X and I seem to be getting micro-stutters I wasn't getting before.
False positive, I think.

It appears the constant stuttering I was getting with the CPU under load in some games I tested was possibly shader caching, whatever that is.

Haven't had time to play many games lately but some of the stuff I was testing does some Nvidia caching or something and can apparently be very stuttery to start out with.

I never had any issues with TPM stuttering on any BIOS prior to now, so I didn't really know what it was/what to look for.

I need some advice on upgrading to a 32GB kit as I've been out of touch with new memory now available since purchasing FlareX's back in 2017
I run a C6H with a 16GB kit (snip attached below) and recently installed a 5900x.
I'm happy with current performance but hoping to run a 32GB kit at 3800 c14 and maintain something very close or hopefully better than current setup.

I prefer G-Skill but may consider others depending on what the masses tell me.
So far I'm looking at F4-3600C14D-32GTZNA G.SKILL Trident Z Neo Series 32GB (2 x 16GB) 288-Pin PC RAM DDR4 3600 (PC4 28800) Intel XMP 2.0 Desktop Memory Model F4-3600C14D-32GTZNA - Newegg.com
Also looked at Royal's etc and can't decide where to draw the line. The FlareX have been awesome for me but feeling I need a change to play with lol.

Again feeling behind in the times knowledge wise on the memory topic of gen3, is this the way to go (2x16 neo's) or maybe seeing C6H is T-Topography is there a noticeable performance gain going 4x8 over 2x16?

Any opinions are highly appreciated.
View attachment 2560054
F4-3600C14D-32GTZNA, that is one of the best kits you can buy now, with the 4000C14 DR kits basically being extinct. 4000C16 might still exist, but a 1.4v rating isn't good for OCing. High change thermal limits are poorer than if you get a kit rated for 1.45~1.55v.

All I would say is it's still an expensive gamble. I briefly had that kit, though it was RipJaws version, and I couldn't do tRCDRD 14 at 3800. Which is quite mental given the bin. But it's likely I was just super unlucky. tRCDRD 14 should really be an almost certainty at 3800 with that kit with the right voltage.

But in the world of memory, you can buy a cheaper kit, like 3200C14 or even 3600C16 or something and still end up being lucky if you goal is something like 3800C14.

If you've got the money to spend though that's likely the best DR bin still being produced for operating at 3800.

Buy any model that isn't RipJaws if you plan on aircooling/not modifying stock heatsinks. It's a crime G.SKILL sell anything with the RipJaws heatsinks. They don't even properly cover the memory chips.
 

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Sad if true, like i wrote in that google doc:

Ok you guys are talking about disabling L2 prefetcher in the AMD CBS biosmenu. I was testing disabling “EnablePrefetcher” in windows which does not help on latency.. I dont have the option to play with L2 prefetcher in my bios so i cant test it for now.. but this will invalidate all previous results on this google spreadsheet.

And it kinda explains "u/zTERRORDACTYL" old 1900:3800 results @ 48.3ns for the 5600x.. cheaters be cheaters 😆
So what do you guys think "we should answer" the owner of the google doc when he asked the following: ?
So what am I supposed to do here? Delete this result? Is there a way to see if the prefetcher was disabled?
I think it would be best to delete all entries which obvious are done with L2 prefetcher disabled.. So far only two entries sticks out to me (together with @TimeDrapery's two newly added ones)
But then we would need to start "policing" the the document for "fake/cheat" prefetcher entries in the future..

Any other point of views/thoughts ?
 

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So what do you guys think "we should answer" the owner of the google doc when he asked the following: ?

I think it would be best to delete all entries which obvious are done with L2 prefetcher disabled.. So far only two entries sticks out to me (together with @TimeDrapery's two newly added ones)
But then we would need to start "policing" the the document for "fake/cheat" prefetcher entries in the future..

Any other point of views/thoughts ?
I have notice another issue that should not be allowed.
Proof of RAM testing/stability should not be provided has a separate pic. It should all be in one single desktop screenshot.

Separate Zentiming and AIDA64 screenshot should not be allowed everything should be in one screenshot including the stability tests.
 

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I have notice another issue that should not be allowed.
Proof of RAM testing/stability should not be provided has a separate pic. It should all be in one single desktop screenshot.

Separate Zentiming and AIDA64 screenshot should not be allowed everything should be in one screenshot including the stability tests.
Well depends if the proof of stability has Zentimings included aswell as the AIDA64 has zentimings in the screenshot it should be fine.
 

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False positive, I think.

It appears the constant stuttering I was getting with the CPU under load in some games I tested was possibly shader caching, whatever that is.

Haven't had time to play many games lately but some of the stuff I was testing does some Nvidia caching or something and can apparently be very stuttery to start out with.

I never had any issues with TPM stuttering on any BIOS prior to now, so I didn't really know what it was/what to look for.



F4-3600C14D-32GTZNA, that is one of the best kits you can buy now, with the 4000C14 DR kits basically being extinct. 4000C16 might still exist, but a 1.4v rating isn't good for OCing. High change thermal limits are poorer than if you get a kit rated for 1.45~1.55v.

All I would say is it's still an expensive gamble. I briefly had that kit, though it was RipJaws version, and I couldn't do tRCDRD 14 at 3800. Which is quite mental given the bin. But it's likely I was just super unlucky. tRCDRD 14 should really be an almost certainty at 3800 with that kit with the right voltage.

But in the world of memory, you can buy a cheaper kit, like 3200C14 or even 3600C16 or something and still end up being lucky if you goal is something like 3800C14.

If you've got the money to spend though that's likely the best DR bin still being produced for operating at 3800.

Buy any model that isn't RipJaws if you plan on aircooling/not modifying stock heatsinks. It's a crime G.SKILL sell anything with the RipJaws heatsinks. They don't even properly cover the memory chips.
My first G.Skill CL14 3600 kit sucked, but I sent it back to Newegg for a second same kit and won the silicon lottery with the second kit. :)
 
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Considering these sticks couldn't even post at these timings before water-cooling my memory, I might be in for a chance

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Huhu,

I'm now sure solving my TM5 "TM5 crash! - Thread Error Handler" problem..
Takes days of testing, but it's nothing about RAM timings.

It is because I have setup the W10 OS with to low swap space.

I'm using a 32G system, and set the OS to use only 4GB vRAM.
TM5 is configured at "Testing Window Size = 1150".

Now with 16G pagefile, I never saw this crash again, and I run many test since changing that setting.
Before there was nearly no run without that crash but with no error within TM5.

That black backgrounded desktop icon while running TM5 is done too.. and I can concentrate at timings.

Prime95 points me, where some threads shuts down short after starting and notify about that possibility.

Hope that can help someone too.

cu
 

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My first G.Skill CL14 3600 kit sucked, but I sent it back to Newegg for a second same kit and won the silicon lottery with the second kit. :)
Strange that! Just shows you how the 'silicon lottery' is still alive and well with super expensive DDR4 bins.

But I have said numerous times in the past, this is why there has never been a 3800 14-14-14-14 bin sold to retail. It would probably be one of G.SKILLs most popular sellers, but clearly they've never been confident enough to mass produce it for retail.

Closest we got was 3800 14-15-15-15.

Then again, I guess you can basically call the 4000 14-14-14-14 bin the 3800 14-14-14-14 bin. But it went extinct super quick. On sale freely probably for like 6 months or less before stock issues and then what looks like complete discontinuation for DR.

Whether that was just a shift to DDR5, or G.SKILL just couldn't keep producing the DR bins, who knows. The only comment I ever seen on it was a CS rep saying the 4000 16-16-16-16 would be the only bin going forward.
 

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Must have been saving unicorn chips for 5 years to make that bin. But also the improved PCB. I think the latter was why 3800 was 14-16-16.
 

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View attachment 2560086

Hi, I posted here once. I got no problem with 2T 0 WHEA for 24/7

but I wanna go pure 1T 0-0-0 .
can any pro guide me to 1T?

currently vdimm 1.545v (air cool)
PPT TDC EDC=114-72-105
Boost Override CPU =50Mhz

I've tried set RTT to 6-3-5/6-3-6/6-3-7
ClkDrvStr to 40-20-30-20/40-20-30-24 and raise my vdimm to 1.6v/1.63v Vsoc 1.18v after vdroop

safe to boot 1T 0 WHEA. once I start TM5 tons of error comes out within a minute. HwinFo64 still 0 WHEA but I shut TM5 immediately to avoid BSOD
Tried 60 or 120 ohms for ClkDrvStr?
ProcODT to 36.9 or 40 ohms?
RTTs don't provide much a benefit, if any, to single-rank so you might be fine with just Disabled-Off-5
What are you able to do if you loosten all your timings and then retighten them around 1T-off?
 

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Overclock the World
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RTTs don't provide much a benefit, if any, to single-rank so you might be fine with just Disabled-Off-5
Except that you don't leave burn marks on your PCB
Sometimes they can be wiped away, soo it's "nothing" ~ surely 🤭

I surely don't need to run 736 on 1.65v or 637 on 1.68v
It's likely just placeholders :)

Aah i wish , i really wish everything was that simple , not having to worry after 1.52v to fry my PCB
"not verifying a change = denying the existence of it"
OCIng would be much easier when resistances didn't matter and XOCer didnt need to change laws of physics , running subzero just so resistance drops and voltage can get another effect
all would be soo much easier, if memory voltage would have a core meaning and resistance + impedances around it would no nothing

Sadly it's not that way :)
But you don't notice a change at the very first. Only when you increase voltage too much
Usually you don't notice powering issues either with GDM, soo no RTT or CAD_BUS issue would be noticed that way ~ can't blame this response
But it's not right ~ you oversee a broader spectrum of power balancing 😇
 
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Except that you don't leave burn marks on your PCB
Sometimes they can be wiped away, soo it's "nothing" ~ surely 🤭

I surely don't need to run 736 on 1.65v or 637 on 1.68v
It's likely just placeholders :)

Aah i wish , i really wish everything was that simple , not having to worry after 1.52v to fry my PCB
"not verifying a change = denying the existence of it"
OCIng would be much easier when resistances didn't matter and XOCer didnt need to change laws of physics , running subzero just so resistance drops and voltage can get another effect
all would be soo much easier, if memory voltage would have a core meaning and resistance + impedances around it would no nothing

Sadly it's not that way :)
But you don't notice a change at the very first. Only when you increase voltage too much
Usually you don't notice powering issues either with GDM, soo no RTT or CAD_BUS issue would be noticed that way ~ can't blame this response
But it's not right ~ you oversee a broader spectrum of power balancing 😇
Burn marks? Termination impedances are on low-current data pins (DQ, DM, DQS_T/DQS_C and TDQS_T/TDQS_C), not high-current power delivery pins. They reduce signal reflection by impedance matching; like how acoustic horns work like. If your stuff is esplodin', something else is going on.

I mean a fancy dynamic ODT (RTT) 'can' help for single-rank, but it's nowhere near as impactful as it is on multi-rank. I do imagine PCB quality has a big say in its usefulness though.
 

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Overclock the World
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I mean a fancy dynamic ODT (RTT) 'can' help for single-rank, but it's nowhere near as impactful as it is on multi-rank. I do imagine PCB quality has a big say in its usefulness though.
On Die Termination feature and generally RTTs behave different on dual rank
it's comparing apples to pears ,just because they grow up in the same soil with the same rain

If you have an A0 PCB design, which starts to fail at 1.48-1.52v, and nearly dies at that (we have had dead A0 dimms here, twice already by people following blind established values)
Mine are not much different.
It's not the IC that fails, usually both my A0 and A2 , between micron and samsung (mind you they are different too, you can't expect everyone to follow jedec designs)
A2 Rev.E start to fail at 1.72ish VDIMM, my A0 B-Dies the ICs start to fail at 1.68v
I think i've reached the IC limit but very well see when PCBs fail and when ICs fail

Dimms do die instantly, but it's nearly never the ICs that mess up, but the PCBs they are on
Sadly it's also no direct post from you, but a quote from another source.
Are you sure about what information you quote me with ?

Because it's the high voltage and exactly the termination impedance's, that depend on what amperage arrives to the dimms and how warm they get
Also it's the high input voltage + strong RTTs that leave such burn residues i can not get away. The 4400 kits and a DR 4267 set (A2 and strange A1 PCB) gotten from a friend, all turned useless
He short-benched them at very high voltages following blind research but there are no way to get stable at all (also yes i do own multiple boards and dimms, if you don't know me)
^ everything i quote is my own source, me ~ based on experience :) Read couple papers, but reality is always different ~ soo i don't gift them too much importance. We overclock, we don't sit at JEDEC designs

These are by now old photo's
I hope this is all i have to lookup ~ just because you don't believe me
Rectangle Font Harmonica Electronics accessory Electronic component

Wood Gesture Plant Tree Vehicle door
Hand Hood Motor vehicle Automotive design Netbook
This was on both A2's , SR and DR
DR i could clean away and they where "fine" although were a strange A1 that trained for over 2 minutes (ripjaws)
Finger Circuit component Material property Gadget Wrist

No burn/oxidation-marks anymore, yet were clear that they had it (cleaning is bothersome and doesn't go away by isopropanol or water)
Cleaning is possible, but all that is not necessary if you just don't follow research blindly
My A0's are perfectly fine to daily 1.65v and my A2 rev.E's in 30° room temp-summer didn't go above 40° without active cooling at 1.68v
Alone that heat differentiates that strongly on RTTs, and i've got a warning that my A0's started to fail at 1.53v (lost channels) ~ i got my lesson , also after messing up @mongoled 's A0's Being equaly resposible for community not knowing what to push and what to lower on over-sensitive weak PCBs :)

Gladly we don't have to have the same experience, that's good ~ so we don't have to agree & i'm happy that you have no messed up dimms
But based on my experience and community here, RTTs need a full redo.
Sadly it depends too much on DIMM PCB and Board PCB.
Boardvendors kinda follow AMDs enforced spec, but not always ~ soo sometimes CAD & RTT impedances differ between Vendor's Trace design. So also on Dimms

They differ way to much, without having a clear indicator of the design & it's not easy to establish "new RTTs"
Also especially since NOM and PARK differ by VDIMM range used
 
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