[Imprezzion]

Set tCWL to 16 and you should be able to lower your tRDWR to 10. And, if you try to set tRDRD_dr to 6 I think it should be much easier to train.

tCWL 16 on it's own is fine but 10 or 11 tRDWR under any circumstance does not POST at all.

From my own testing I also found that tCKE and tRTP cannot go under 8 or it will memory overclock failed POST.

I did manage to get tRDRD_dr to boot 6 so testing that now with TM5 Anta Extreme.

Do you guys think it's worth the extra voltage (and heat) to go for 4200-15-17-17-34-280-2T over 16-17-17-35? I need 1.60v vDIMM to do C15 while C16 only needs 1.49v ish. The DIMM's will get well over 53c on 1.60v if the GPU is also in use which is very close to the RAM. It isn't bad for the DIMM's but B-Die hates temp and might become unstable?

 

[MericaShotUrAss]

tCWL 16 on it's own is fine but 10 or 11 tRDWR under any circumstance does not POST at all.

From my own testing I also found that tCKE and tRTP cannot go under 8 or it will memory overclock failed POST.

I did manage to get tRDRD_dr to boot 6 so testing that now with TM5 Anta Extreme.

Do you guys think it's worth the extra voltage (and heat) to go for 4200-15-17-17-34-280-2T over 16-17-17-35? I need 1.60v vDIMM to do C15 while C16 only needs 1.49v ish. The DIMM's will get well over 53c on 1.60v if the GPU is also in use which is very close to the RAM. It isn't bad for the DIMM's but B-Die hates temp and might become unstable?

Definitely not worth the 20 points in geek bench and to risk stability over time. One reason 4800c16 isn’t going to happen on this kit, will take approximately 1.69vdimm or more to make it worth running with a decent performance improvement. I going based off what it took to post solid timings with minimal testing. Don’t even know if it would stabilize at all

 

[7empe]

Hey, I've been working for a quite long time on my OC of 4x8GB Viper Steel 4400 CL19 combined with 10900KF and M12E mobo. My IMC is limiting me with getting into high frequency range with 4 sticks and sticks itself are just an ordinary b-dies. This is what I could achieve:

2x8GB

• 4600 MHz 17-17-17-35-2T

4x8GB

• 4200 MHz 16-16-16-34-2T (few errors per 5000% of mem coverage that I cannot mitigate...)
• 4133 MHz 16-16-16-34-2T
• 4000 MHz 15-15-15-32-2T
• 3900 MHz 15-15-15-32-1T (possible only with enabling the trace centering)

This is the close look at 4000 MHz CL15 configuration:

Cheers!

 

[YaqY]

tCWL 16 on it's own is fine but 10 or 11 tRDWR under any circumstance does not POST at all.

From my own testing I also found that tCKE and tRTP cannot go under 8 or it will memory overclock failed POST.

I did manage to get tRDRD_dr to boot 6 so testing that now with TM5 Anta Extreme.

Do you guys think it's worth the extra voltage (and heat) to go for 4200-15-17-17-34-280-2T over 16-17-17-35? I need 1.60v vDIMM to do C15 while C16 only needs 1.49v ish. The DIMM's will get well over 53c on 1.60v if the GPU is also in use which is very close to the RAM. It isn't bad for the DIMM's but B-Die hates temp and might become unstable?

Try setting the tertiary timing section to fixed mode on msi and see if it helps posting lower tertiaries.

 

[Imprezzion]

Try setting the tertiary timing section to fixed mode on msi and see if it helps posting lower tertiaries.

I always run Fixed on both tertiary and RTL/IO
I can POST 11's, not 10's now with a bit more voltage but it's an erroring mess.

These DIMM's always hated tRDWR. At 4400C17 it doesn't go under 15's. On 4533C17 it even needs to be above 16 to stand a chance of being stable.

So yeah, dailed in now at 3 completely different overclocks for the RAM and now I can't choose which to daily lol..

4200 16-17-17-35-280-2T 1.50v /1.35v SA 1.25v IO.
4400 17-17-17-36-330-2T 1.48v /1.40v SA 1.35v IO.
4533 17-19-19-39-350-2T 1.52v / 1.43v SA 1.38v IO.

Due to having way higher secondary and tertiary timings the latency at 4200C16 is about 1ns better then both other overclocks but bandwidth is down by like a good 6GB/s aka. 10% so yeah.. which one.

Or, judging by these results, any other combinations of primary timings + frequency I can try to get stable? Super bored anyway working from home lol.

The IMC is not going to do 4600 anyway so yeah, don't get me started. Lol. I mean, highest I can boot with some resemblance of stability is 4700 17-19-19-45-500-2T 1.68v /1.55v SA 1.45v IO but no matter what I do with ODT, VRef, Skews, it just won't stabilize without going way overboard on the IO/SA voltages.

 

[Gregix]

I started to think, that Z370 Taichi was so far best MB I have had.
4400c19 patriots 2*8Gb- 4400c19, 4100c15, 3800c14. 4400c19 was tricky, so just for sport was done.
3200c14 g.skill 2*16Gb - 3800c14 full stable. (Max mhz for this mems/mb/imc combo)
3200c14 TG 4*8Gb - 3800c15 full stable.
Z390 auros pro - no love for anything more than 3600c15 with g.skill, 3800c15-4100c16 with TG. I returned it, as no way to set properly IOLs/RTLs, resulting low scores.

Now, Z390 Gaming Edge, have it like 2 days, have hard time to stabilize it with g.skill at 3800/3866c15. CPU is the same.
But settings cannot be copied between motherboards. Tried 4*8 TG at start, but gave up, maybe will return to them.
My old settings from z370 Taichi for g.skill just errors Ollie in first 20secs, if lucky after 4-7 mins. It sucks.

BTW what was proper dual rank memory's WR/NOM/etc values for MSI?
OK, found it, 80/34/120 wr/nom/park. Seems to work, 8th min ollie 3800c14 running smooth so far.

 

[MericaShotUrAss]

I always run Fixed on both tertiary and RTL/IO
I can POST 11's, not 10's now with a bit more voltage but it's an erroring mess.

These DIMM's always hated tRDWR. At 4400C17 it doesn't go under 15's. On 4533C17 it even needs to be above 16 to stand a chance of being stable.

So yeah, dailed in now at 3 completely different overclocks for the RAM and now I can't choose which to daily lol..

4200 16-17-17-35-280-2T 1.50v /1.35v SA 1.25v IO.
4400 17-17-17-36-330-2T 1.48v /1.40v SA 1.35v IO.
4533 17-19-19-39-350-2T 1.52v / 1.43v SA 1.38v IO.

Due to having way higher secondary and tertiary timings the latency at 4200C16 is about 1ns better then both other overclocks but bandwidth is down by like a good 6GB/s aka. 10% so yeah.. which one.

Or, judging by these results, any other combinations of primary timings + frequency I can try to get stable? Super bored anyway working from home lol.

The IMC is not going to do 4600 anyway so yeah, don't get me started. Lol. I mean, highest I can boot with some resemblance of stability is 4700 17-19-19-45-500-2T 1.68v /1.55v SA 1.45v IO but no matter what I do with ODT, VRef, Skews, it just won't stabilize without going way overboard on the IO/SA voltages.

I would run geekbench and see how significant the difference is because bandwidth is a lot more noticeable than 1ns of latency in games, if you play warzone game is memory bandwidth limited at low resolution, haven’t tested 1440p in a while but couple people I know said they seen improvements as well in 1440p one with a 3090. Your 4400 profile I have a feeling will turn out to give best results in geek and Aida, and Aida latency test is synthetic AF dependent on so many things, like windows build, services running, ect I mean it can be raining out and you gain 1ns 😂😭🤣 and 1.45SA is nothing to worry about on these chips. And there’s tricks to getting certain timings to drop takes a lot of work but may be stick/mobo not happy.

 

[OLDFATSHEEP]

tCWL 16 on it's own is fine but 10 or 11 tRDWR under any circumstance does not POST at all.

From my own testing I also found that tCKE and tRTP cannot go under 8 or it will memory overclock failed POST.

I did manage to get tRDRD_dr to boot 6 so testing that now with TM5 Anta Extreme.

Do you guys think it's worth the extra voltage (and heat) to go for 4200-15-17-17-34-280-2T over 16-17-17-35? I need 1.60v vDIMM to do C15 while C16 only needs 1.49v ish. The DIMM's will get well over 53c on 1.60v if the GPU is also in use which is very close to the RAM. It isn't bad for the DIMM's but B-Die hates temp and might become unstable?

I would just stick to 1.49v in this case.

 

[munternet]

Hey, I've been working for a quite long time on my OC of 4x8GB Viper Steel 4400 CL19 combined with 10900KF and M12E mobo. My IMC is limiting me with getting into high frequency range with 4 sticks and sticks itself are just an ordinary b-dies. This is what I could achieve:

2x8GB

• 4600 MHz 17-17-17-35-2T

4x8GB

• 4200 MHz 16-16-16-34-2T (few errors per 5000% of mem coverage that I cannot mitigate...)
• 4133 MHz 16-16-16-34-2T
• 4000 MHz 15-15-15-32-2T
• 3900 MHz 15-15-15-32-1T (possible only with enabling the trace centering)

This is the close look at 4000 MHz CL15 configuration:

View attachment 2479627

Cheers!

It may not be your IMC limiting you
You are running 4 sticks on a daisychain board which is not ideal although that is a reasonable overclock
Considering your substantial investment in the board and CPU you might consider 2x16GB dual rank B-dies?
Either way, have you addressed Vref, ODT skews and slopes? These will increase the width of stability and maximize your potential if you haven't already

 

[7empe]

It may not be your IMC limiting you
You are running 4 sticks on a daisychain board which is not ideal although that is a reasonable overclock
Considering your substantial investment in the board and CPU you might consider 2x16GB dual rank B-dies?
Either way, have you addressed Vref, ODT skews and slopes? These will increase the width of stability and maximize your potential if you haven't already

Hey, yeah it is daisychain mobo and I will go forward with 2x16GB, but currently I have these 4 sticks so... I am playing what I can do with them ODTs are set to 80-34-40 (WR-Park-Nom). Also 80-34-48 works fine. Did not play with slopes, because I am missing any guidence on where to start here... Same for Vref. All set to auto.

Right now I got finally working 4200 16-16-16-34. It is stable, but despite having fixed RTLs/IO-Ls/ODTs it happens that I got POST code 55 and after several reboots mobo finally trains remaing stuff good enough. What's more intresting is that even if it POSTs, it is not always error free in TM5/Karhu - but there is a pattern - if there is no error during first 5 mins of test, it is fully stable (overnight test passes without single error and Prime95 112k FFTs are stable too). Otherwise I need to perform another reboot, and if there is no code 55, then there is a chance that some "auto" values will be properly set. In the same way I was able to boot with 4266 16-16-16-34. I have no idea which "auto" settings I should fix in BIOS to get rid of this transient instability. As I mentioned - almost all the memory related timings are already fixed. Is it possible that Vref and slope left on "auto" may cause this?

This is 4200 MHz result:

Any hints much appreciated.

Cheers!

 

[Imprezzion]

I run basically the same timings except for 16-17-17 primary on a DR kit at the moment. Secondary and tertiary is 95% the same, I run slightly lower tWR at 12 and tRFC 280, rest is the same. AIDA Results are identical. Bandwidth r,w,c is the same +- a few MB/s, latency is 36.7 for mine, so yeah looks solid to me.

 

[7empe]

I run basically the same timings except for 16-17-17 primary on a DR kit at the moment. Secondary and tertiary is 95% the same, I run slightly lower tWR at 12 and tRFC 280, rest is the same. AIDA Results are identical. Bandwidth r,w,c is the same +- a few MB/s, latency is 36.7 for mine, so yeah looks solid to me.

What are your voltages? VDIMM, VCCSA, VCCIO? As for tRFC, I can run 280, but 275 causes severe instabilities. To be on the safe side I decided to lock on 300 (according to buildzoid, there is no big difference between 280 and 300).

 

[Imprezzion]

What are your voltages? VDIMM, VCCSA, VCCIO? As for tRFC, I can run 280, but 275 causes severe instabilities. To be on the safe side I decided to lock on 300 (according to buildzoid, there is no big difference between 280 and 300).

1.49v vDIMM, 1.35v SA, 1.25v IO. (5Ghz cache, 5.3Ghz all core CPU 1.390v).

80-40-40 ODT's, DLL 0, PPD disabled, no training all manual RTL IO at 63/63/6/6 which is also a slight difference between our clocks lol.

 

[7empe]

1.49v vDIMM, 1.35v SA, 1.25v IO. (5Ghz cache, 5.3Ghz all core CPU 1.390v).

80-40-40 ODT's, DLL 0, PPD disabled, no training all manual RTL IO at 63/63/6/6 which is also a slight difference between our clocks lol.

Nice voltages! Mine CPU has SP 53 and all I can do is 4.8 cache, 5.1 all core with 1.41v (LLC 4 of 8). I can run 5.2 with ridiculous voltages... To get rid of cache L0 errors with 4x8GB 4200 MHz and these timings I have to use 1.33v IO / 1.36v SA.

 

[munternet]

Hey, yeah it is daisychain mobo and I will go forward with 2x16GB, but currently I have these 4 sticks so... I am playing what I can do with them ODTs are set to 80-34-40 (WR-Park-Nom). Also 80-34-48 works fine. Did not play with slopes, because I am missing any guidence on where to start here... Same for Vref. All set to auto.

Right now I got finally working 4200 16-16-16-34. It is stable, but despite having fixed RTLs/IO-Ls/ODTs it happens that I got POST code 55 and after several reboots mobo finally trains remaing stuff good enough. What's more intresting is that even if it POSTs, it is not always error free in TM5/Karhu - but there is a pattern - if there is no error during first 5 mins of test, it is fully stable (overnight test passes without single error and Prime95 112k FFTs are stable too). Otherwise I need to perform another reboot, and if there is no code 55, then there is a chance that some "auto" values will be properly set. In the same way I was able to boot with 4266 16-16-16-34. I have no idea which "auto" settings I should fix in BIOS to get rid of this transient instability. As I mentioned - almost all the memory related timings are already fixed. Is it possible that Vref and slope left on "auto" may cause this?

This is 4200 MHz result:

View attachment 2479777

Any hints much appreciated.

Cheers!

I have made a thread listed in my sig for setting ODTs and the principals for setting slopes is fairly similar. Vref had only one voltage for me that was stable in GSAT so that was a no brainer
I can make a new thread on how I set my slopes if you like although I have the Apex XII and I'm not sure how many boards it will be relevant for. Probably the XII Extreme will be one
GSAT seems the best tool to use for setting all these parameters.
There are other settings in the BIOS that compliment slopes but they train well in the Apex already so I don't need to address them but others might
Your results look pretty good and I'm fairly confident addressing the slopes will make it train and perform consistently
I was having similar problems with 4600c16 up until setting them
Your voltages look pretty good
Have you tried LLC7 with the Extreme. I think it has the best VRM of the lot

 

[Gregix]

Gregix -i7-8086K @5/4.8---3800Mhz-C14-14-14-30-2T----1.52v---SA 1.227v IO 1.226v---TM5 extreme----3 Hour 36 min (tXP=6, gear down mode=disabled)
F4-3200C14D-32GTZ
Probably(but not sure yet) I could go lower with VDIMM.

It does boot 4133, which was surprise to me after fail with z370. Should I go for it? Starting point was c17 at that speed.

 

[7empe]

I have made a thread listed in my sig for setting ODTs and the principals for setting slopes is fairly similar. Vref had only one voltage for me that was stable in GSAT so that was a no brainer
I can make a new thread on how I set my slopes if you like although I have the Apex XII and I'm not sure how many boards it will be relevant for. Probably the XII Extreme will be one
GSAT seems the best tool to use for setting all these parameters.
There are other settings in the BIOS that compliment slopes but they train well in the Apex already so I don't need to address them but others might
Your results look pretty good and I'm fairly confident addressing the slopes will make it train and perform consistently
I was having similar problems with 4600c16 up until setting them
Your voltages look pretty good
Have you tried LLC7 with the Extreme. I think it has the best VRM of the lot

I would be more than happy to read about your experience regarding slope settings. Can you share a link to this thread? Thanks in advance!

 

[asdkj1740]

Reason for knowing how high your cache can go on something like 4000c16 is because you will know your highest stable cache, because high frequency/tight timings can make cache go unstable, and sometimes it’s not worth sacrificing 300MHz cache for 100mhz on ram because cache boosts ram latency and bandwidth! Also once you get something stable you just retest with p95, OCCT large data ect after passing tm5, gsat ect. And you don’t have to rerun hrs of memory tests after you set cache. You can pass p95 4-112fft in place for cache and then throw 20 errors in a previous stable tm5 because cache increase.

what custom settings should i use for cache and memory test in p95??? or which preset suits the most?
thank you.

 

[7empe]

what custom settings should i use for cache and memory test in p95??? or which preset suits the most?
thank you.

With p95 I use custom 112k - 112k FFTs in-place AVX disabled. This stress the cache and memory the most. If cache is unstable, you will notice L0 cache errors - you need to raise vccio in that case (and/or vcore). For computation errors raise vccsa (and/or vdimm).

 

[munternet]

I would be more than happy to read about your experience regarding slope settings. Can you share a link to this thread? Thanks in advance!

I documented my method and linked it in my sig