[sinakr6]

Guys my problem is that memory limits my oc.Im currently using 165x13.5.
But i find out my maximum clock that motherboard can handle is 292.I find it after i set cpu multi to 5 and memory clock to 200 and timing to:
5-5-5-18-26-2t

So i wanna use 292x12 when my memory clock doesnt go higher than 1066.
I set memory clock to 333.But system didnt boot.Thats because of wrong memory timing.Any idea to what timing i should use for 333.The hint is for 200 i used these timing and they worked:
5-5-5-18-26-2t

Please dont say use timing in the spd page cause i tried them and none of them works.

 

[sinakr6]

any idea?

 

[yashau]

Try a 333 x 10.5 instead

 

[sinakr6]

Quote:

Originally Posted by yashau Try a 333 x 10.5 instead

As i told my maximum stable clock is 292

 

[Vipervlv]

Are you sure your memory can handle 1066?

 

[sinakr6]

Quote:

Originally Posted by Vipervlv Are you sure your memory can handle 1066?

Yeah at 267x13.5 ir runs fine at 1066

 

[Vipervlv]

You could try to raise a bit the timing - 6-6-6-18 or you could try to remain the same (5-5-5-15) but raise the voltage 1.85-1.9 up to 2.0.

 

[thealmightyone]

Loosen your timings as far as they will go, overclock your system, then tighten your timings.

 

[sinakr6]

Quote:

Originally Posted by thealmightyone Loosen your timings as far as they will go, overclock your system, then tighten your timings.

Be more spicific.Im not familier with timing.

 

[thealmightyone]

Quote:

Originally Posted by sinakr6 Be more spicific.Im not familier with timing.

The 'timings' are the various tasks associated with memory I/O, which are broken down into many small commands. The value given to the timing is the number of clock cycles it has to undertake its command.

Example: tCL

Quote:

CAS stands for Column Address Strobe or Column Address Select. It controls the amount of time in cycles between sending a reading command and the time to act on it. From the beginning of the CAS to the end of the CAS is the latency. The lower the time of these in cycles, the higher the memory performance.

As you increase the FSB clock, the time per clock falls (eg, from 8 nano seconds to 7 nanoseconds), so the timings have slightly less time to perform it's function. Eventually, as you increase the FSB clock, one of the timings, or more, will not have enough time to perform it's function correctly, and memory errors will appear.

'Loosening' a timing involves increasing the number of allocated clock cycles, eg from 5 to 6.