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This is not MY original work, but I thought it might be helpful to share these with everyone:<br><br>
Cas# Latency (tCL)<br>
Ras# to Cas# Delay (tRTC)<br>
Ras# Precharge (tRP)<br>
Active to Precharge (tRas)<br>
Row Cycle Time (tRC)<br>
Refresh to Activate Delay / Refresh Cycle Time (tRFC)<br>
Refresh Mode Select (RMS) / Refresh Period (tREF)<br>
Command Rate / Command per Clock (1T/2T)<br>
Performance Level / Read Delay (tRD)<br>
Write to Precharge Delay / Write Recovery Time (tWR)<br>
Write to Read command Delay / Write to Read Delay (tWTR)<br>
Activate to Activate delay (tRRD)<br>
Read to Precharge delay (tRTP)<br>
Read to Write delay (tRTW)<br>
Precharge to Precharge delay (tPTP)<br>
Write-Read Command Spacing (tWR-RD)<br>
Read-Write Command Spacing (tRD-WR)<br>
Write-Write Command Spacing (tWR-WR)<br>
Force Auto Precharge<br>
Maximum Asynchronous Latency<br>
Maximum Read Latency<br>
Read/Write Queue Bypass<br>
Queue Bypass Max<br>
DRAM Idle timer<br><br>
-Cas# Latency (tCL).<br>
Number of clocks that elapses between the memory controller telling<br>
the memory module to access a particular column in the current row,<br>
and the data from that column being read from the module's output pins.<br><br>
-RAS# to CAS# Delay (tRCD).<br>
Controls the number of clocks inserted between a row activate command<br>
and a read or write command to that row. Last Intel chipset (965 and P35)<br>
allow to change RAS# to CAS# Read Delay and RAS# to CAS# Write Delay separately<br><br>
-RAS# Precharge (tRP).<br>
Controls the number of clocks that are inserted between a row precharge<br>
command and an activate command to the same rank.<br><br>
-Activate to Precharge delay (tRAS).<br>
Number of clocks taken between a bank active command and issuing the<br>
precharge command. Usually, tRAS=tCL + tRCD + 2.<br><br>
-Row Cycle Time (tRC).<br>
Determines the minimum number of clock cycles a memory row takes to<br>
complete a full cycle, from row activation up to the precharging of<br>
the active row. For optimal performance, use the lowest value you can,<br>
according to the tRC = tRAS + tRP formula. For example:<br>
if your memory module's tRAS is 7 clock cycles and its tRP is 4 clock cycles,<br>
then the row cycle time or tRC should be 11 clock cycles.<br><br>
-Refresh to Activate Delay / Refresh Cycle Time (tRFC).<br>
Determines the number of clock measured from a Refresh command (REF)<br>
until the first Activate command (ACT) to the same rank<br><br>
-Refresh Mode Select (RMS) / Refresh Period (tREF).<br>
Determines at what rate refreshes will be executed. Contrary to other timings,<br>
higher value is better for performance.<br><br>
-Command Rate / Command per Clock (1T/2T).<br>
Delay between when a memory chip is selected and when the first active<br>
command can be issued. The factors that determine whether a memory<br>
subsystem can tolerate a 1T command rate are many, including the number<br>
of memory banks, the number of DIMMs present, and the quality of the DIMMs.<br><br>
-Performance Level / Read Delay (tRD).<br>
tRD is the number of memory clocks from DRAM Chip Select# assert<br>
to Host Data Ready# assertion on the FSB.<br>
Hight influence on performance and stability.<br><br>
-Write to Precharge Delay / Write Recovery Time (tWR).<br>
-Write Recovery time is an internal dram timing, values are usually 3 to 10.<br>
It specifies the amount of delay (in clock cycles) that must elapse after the<br>
completion of a valid write operation, before an active bank can be precharged.<br>
-Write to Precharge is a command delay, and is calculed as:<br>
Write to Precharge = tCL - 1 +BL/2 + tWR.<br>
BL(Burst Lenght) practically always 8.<br><br>
-Write to Read command Delay / Write to Read Delay (tWTR).<br>
-Write to Read delay is an internal dram timing, values are usually 2 to 8.<br>
Specifie the number of clock between the last valid write operation and the next<br>
read command to the same internal bank<br>
-Write to Read command is a command delay, and is calculed as:<br>
Write to Read = tCL - 1 +BL/2 + tWTR.<br>
BL(Burst Lenght) practically always 8.<br><br>
-Activate to Activate delay (tRRD).<br>
Number of clocks between two row activate in different banks of the same rank.<br><br>
-Read to Precharge delay (tRTP).<br>
Number of clocks that are inserted between a read command to a row<br>
pre-charge command to the same rank.<br><br>
-Read to Write delay (tRTW).<br>
Number of clocks that are inserted between a read command to a write<br>
command to the same rank.<br><br>
-Precharge to Precharge delay (tPTP).<br>
Number of clocks that are inserted between two Precharge command in<br>
different banks of the same rank.<br><br>
-Write-Read Command Spacing (tWR-RD).<br>
This field determines the number of turn-around clocks on the data bus needs<br>
to be inserted between write command and a subsequent read command on Different Rank.<br><br>
-Read-Write Command Spacing (tRD-WR).<br>
This field determines the number of turn-around clocks on the data bus needs<br>
to be inserted between read command and a subsequent write command on Different Rank.<br><br>
-Write-Write Command Spacing (tWR-WR).<br>
This field controls the turnaround time on the DQ bus for WR-WR sequence to<br>
different ranks in one channel.<br><br>
-Force Auto Precharge.<br>
When enabled, force auto Precharging with every read or write command.<br>
This may be preferred in situation where powers savings is favored over performance.<br><br>
-Maximum Asynchronous Latency.<br>
Specify the maximum round trip latency in the system from the processeur to<br>
the DRAM devices and back.<br><br>
-Maximum Read Latency.<br>
Specify the maximum round trip latency in the system from the processeur to<br>
the DRAM devices and back. This time is specified in NorthBridge clock and<br>
includes the asynchronous and synchronous latencies.<br><br>
-Read/Write Queue Bypass<br>
Specify the number of times that the oldest operation in the DCI read/Write<br>
queue may be bypassed .<br><br>
-Queue Bypass Max<br>
Specify the maximum of times that the oldest memory-access request in<br>
the DRAM controller queue may be bypassed .<br><br>
-DRAM Idle timer.<br>
Determine the number of clocks the DRAM Controller will remain in the idle<br>
state before it begins precharging all pages.<br><br>
Original document is found <a href="http://www.tweakers.fr/timings.html" target="_blank">here</a>.<br><br>
Hope this helps! <img alt="" class="inlineimg" src="/images/smilies/smile.gif" style="border:0px solid;" title="Smile">
 

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Awesome, thanks man.
 

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Ok I understand the meanings, but I have a genral question about the ACT RAS# To PRE; I currently have it set very low and stable, and I am wondering why. Am I getting better performance with it lower or higher, or is there a sweet spot I am unaware of.<br>
Current DIMM's are a 8GB set of G.SKILL Trident X 15000 serial(so samsung chips, not hynix)<br>
The setup is as follows<br>
1866MHZ<br>
1.66250V<br>
CL 7<br>
RAS# 8<br>
RAS# PRE 9<br><b>RAS# ACT TIME 10</b><br>
READ to PRE 5<br>
RAS# to RAS# Delay 4<br>
WRITE to READ DELAY 5<br>
CAS# Write LATENCY 7<br>
WRITE RECOVERY TIME 10<br>
REF CYCLE TIME 300ns<br>
ROW CYCLE TIME 30<br>
READ TO WRITE DELAY 7<br>
WRITE TO READ DELAY 1<br>
WRITE TO WRITE 3<br>
READ TO READ 3<br>
REF RATE 7.8ns<br>
COMMAND RATE 1T<br><br>
Any help or suggestions from members would be great as I do not know much about RAM and I have a craving learn after getting these 2400mhz rated beasts
 

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So which is better? 9-9-9-24 or 9-9-9-27?
 

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9-9-9-24
 

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That's really nice and handy. Thanx!!!
 

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<div class="quote-container" data-huddler-embed="/t/381699/ram-timings-explained#post_19433046" data-huddler-embed-placeholder="false"><span>Quote:</span>
<div class="quote-block">Originally Posted by <strong>convivialguru</strong> <a href="/t/381699/ram-timings-explained#post_19433046"><img alt="View Post" class="inlineimg" src="/img/forum/go_quote.gif"></a><br><br>
So which is better? 9-9-9-24 or 9-9-9-27?</div>
</div>
The lower, the better. You will want low as possible latencies for video editing and but for gaming you will want higher clock speeds (timings aren't as important).
 

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<div class="quote-container" data-huddler-embed="/t/381699/ram-timings-explained#post_19434207" data-huddler-embed-placeholder="false"><span>Quote:</span>
<div class="quote-block">Originally Posted by <strong>noobhell</strong> <a href="/t/381699/ram-timings-explained#post_19434207"><img alt="View Post" class="inlineimg" src="/img/forum/go_quote.gif"></a><br><br>
The lower, the better. You will want low as possible latencies for video editing and but for gaming you will want higher clock speeds (timings aren't as important).</div>
</div>
<br>
For general computer use is low latencies better? Is higher clock speeds only for gaming? or is there something else that benefits from higher clock speeds?
 

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<div class="quote-container" data-huddler-embed="/t/381699/ram-timings-explained#post_19446467" data-huddler-embed-placeholder="false"><span>Quote:</span>
<div class="quote-block">Originally Posted by <strong>hucklebuck</strong> <a href="/t/381699/ram-timings-explained#post_19446467"><img alt="View Post" class="inlineimg" src="/img/forum/go_quote.gif"></a><br><br><div class="quote-container" data-huddler-embed="/t/381699/ram-timings-explained#post_19434207" data-huddler-embed-placeholder="false"><span>Quote:</span>
<div class="quote-block">Originally Posted by <strong>noobhell</strong> <a href="/t/381699/ram-timings-explained#post_19434207"><img alt="View Post" class="inlineimg" src="/img/forum/go_quote.gif"></a><br><br>
The lower, the better. You will want low as possible latencies for video editing and but for gaming you will want higher clock speeds (timings aren't as important).</div>
</div>
<br>
For general computer use is low latencies better? Is higher clock speeds only for gaming? or is there something else that benefits from higher clock speeds?</div>
</div>
For everything lower latencies will be better, but if you need to decide between low latencies or a higher clock speed, you should look at what you will be doing on your computer. Of course video editing benefits from higher clock speeds too, but timings are more important.
 

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<div class="quote-container" data-huddler-embed="/t/381699/ram-timings-explained#post_19434207" data-huddler-embed-placeholder="false"><span>Quote:</span>
<div class="quote-block">Originally Posted by <strong>noobhell</strong> <a href="/t/381699/ram-timings-explained#post_19434207"><img alt="View Post" class="inlineimg" src="/img/forum/go_quote.gif"></a><br><br>
The lower, the better. You will want low as possible latencies for video editing and but for gaming you will want higher clock speeds (timings aren't as important).</div>
</div>
<br>
Pardon me! I'm unable to understand. Could you clarify? See, Higher clock frequency will indeed result in lower time i.e. lower latency. So why are you referring it to as <i>"low latencies or a higher clock speed"</i>. Am I correct? <img alt="rolleyes.gif" class="bbcode_smiley" src="http://files.overclock.net/images/smilies/rolleyes.gif">
 

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<div class="quote-container" data-huddler-embed="/t/381699/ram-timings-explained#post_19519729" data-huddler-embed-placeholder="false"><span>Quote:</span>
<div class="quote-block">Originally Posted by <strong>core unlocker</strong> <a href="/t/381699/ram-timings-explained#post_19519729"><img alt="View Post" class="inlineimg" src="/img/forum/go_quote.gif"></a><br><br>
Pardon me! I'm unable to understand. Could you clarify? See, Higher clock frequency will indeed result in lower time i.e. lower latency. So why are you referring it to as <i>"low latencies or a higher clock speed"</i>. Am I correct? <img alt="rolleyes.gif" class="bbcode_smiley" src="http://files.overclock.net/images/smilies/rolleyes.gif"></div>
</div>
<br>
He is reffering to Ocing RAM over OCing the CPU, so the answer to your question is a a two part answer.<br>
1. No in the context in which he is referring to, you would be wrong.<br>
2.Yes. Having a higher clocked CPU will create more of a performance boost then tweaknig RAM timings and thus, cause the RAM to perform faster as well, but still within the same latencies.<img alt="thumb.gif" class="bbcode_smiley" src="http://files.overclock.net/images/smilies/thumb.gif">
 

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==--<br>
THANKYOUTHANKYOUTHANKYOUTHANKYOUTHANKYOUTHANKYOU!<br><br>
I've had to guess at the meanings of most of this.<br><br>
--faye
 
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