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Here is an interesting (although not hugely informative) about what might be going into AMD's next chips, Opteron cited specifically. Maybe this is how AMD plans on getting a big performance boost?

Article link

I'm somewhat unfamiliar with what it takes to add a math co-processor, but is this something that could be implemented in the AM2 chips, or would it have to wait for a whole new architecture?
 

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Yes, this has been brought up receintly
 

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This would very likely be added to new architecture. Removing the FPU from the CPU, whilst leaving the ALU to perform integer operations whilst the proprietary chip FPU would receive all floating point operations. A smart move when one considers both the amount of FPU instensive tasks (voice recognition, etc.) and quad to eight core specific processing units.

One would have to disable the current FPU in the CPU and create a form factor motherboard to accept an FPU chip as well as chipset control and recognition of the FPU specific operation streams. Too much work. This is for implimentation on quad or greater cores I would think.

R
 

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Discussion Starter #4
Is there another post that has this info that you speak of?
I tried to find any other posts on the subject but I only looked under "math" and "co-processor". Could you link or re-direct me so this doesn't become a duplicate?

EDIT: This post was in regard to The Duke's comment. Sry for the confusion
 

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This was not "looked up" by me.

This was taken from my head and common sense. The only time I look things up are when I am not very certain, lack the knowlege, benchmarks or when questioned as to the veracity of my words. This is why I used the terms "Very Likely" and "I would think". Personal opinion.

R
 

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Discussion Starter #6
Pardon my ignorance and double post, but couldn't help but wonder if something like the following might be possible? I know its oversimplified but is the concept itself even feasible? The article above made no mention of the size of the co-processor so I'm assuming it might be the size of an A64 core. If they put it on the same chip like in the pic, wouldn't that eliminate the need for motherboard form factor modification?

Attachment 21816

Keep in mind my knowledge of the innerworkings of a CPU are limited, at best
 

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There is already an FPU on the chip. This would have to be disabled and a new formfactor fab of the architecture to add hardware (not an instruction set but hardware) to the CPU thus it would be like disabling the one built into the cpu in order to build another one onto the cpu.

An exercise in futility I would think.

R
 

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Quote:


Originally Posted by thenutty1

Here is an interesting (although not hugely informative) about what might be going into AMD's next chips, Opteron cited specifically. Maybe this is how AMD plans on getting a big performance boost?

Article link

I'm somewhat unfamiliar with what it takes to add a math co-processor, but is this something that could be implemented in the AM2 chips, or would it have to wait for a whole new architecture?

Math co-processors have been around since Intel 80486. I haven't studied current architecture for quite awhile (used to work on 8088 for Motorola doing low voltage development), but I'm assuming AMD current processors have a math co-processor already. I think what the article is suggesting is that Clearspeed's processor is much faster. If I'm reading this right, I believe they're suggesting that the Clearspeed would be used in addition to the current one, not replacing it.
 

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Ah, I see what your saying. I guess it would probably depend of the size of the co-processor and whether or not it is physically possible. I presuming it might be worth it cuz the article states that Clearspeed's chip is 25% faster than AMD's Quad Core chips, in terms of FP operations. It seems that would translate to a good bump in game performance!
 

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Quote:


Originally Posted by sccr64472

Math co-processors have been around since Intel 80486.

That is wrong information. Math co-processors have been around since before the 80486. The Intel 80386 microprocessor used an optional math coprocessor (the 80387). The Intel 80286 used an optional math coprocessor (the 80287). In point of fact the original IBM PC included a socket for the Intel 8087 floating point coprocessor and was a popular option for people using the PC for CAD or mathematics-intensive (database, astronomical, etc.) calculations. In that architecture, the coprocessor sped up floating-point arithmetic on the order of fifty-fold.

All modern processors have an internal FPU built into the chip. This clearspeed certainly could be a parallel acellerator of the current processor. However, I doubt that it would be used in terms of the current processors. I also doubt that it would be inserted into the CPU. Considering the format I have just researched I would hazard a guess that it will be an additional chip such as the 8086, 8088, 80286 and 80386 employed.

However as shown, there is the possibility of an add-on pci board with the parallel acellerators installed.

Regard:

http://www.clearspeed.com/downloads/...d_FPF_2004.pdf

R
 

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Discussion Starter #11
Ya, I think you are correct.

Quote:


The CSX600 is supplied in a 1,011 pin thermallyenhanced
flip-chip Ball Grid Array (BGA) package. It has
1.8V I/Os and a 1.2V low power core.

I guess that would be tough to fit on-chip lol. I guess it was just my wishfull thinking when I saw this, that I could use it for my personal computer someday
 
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