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No surprises here GEIL Evo X 3200 CL16 (GEX416GB3200C16DC) works at advertized speeds and settings as well (despite being the most disgusting looking modules I've ever seen
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)
Hynix MFR.

What is rather surprising is that despite we are supposedly not even at the limits of the IMC, there are rather obvious differences between the different CPU specimens. The 1800X PR CPU I used for this run requires > 100mV higher VDDCR_SoC voltage than the 1700 CPU I've used in previous runs, even on the same memory modules.

At the same 925mV voltage, which the 1700 is completely stable the 1800X PR is unable even to post. 975mV is required to make it to post costantly and full stability requires 1025mV (setpoint). What makes it even more interesting is the fact that the 1800X PR has significantly higher leakage (29%), than the 1700 which I specifically binned for low leakage.

 

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Quote:
Originally Posted by Praz View Post

Hello

The VRM Spread Spectrum setting modulates the VRM switching frequency around the set point. This has no bearing on the bus speed.
Makes sense. But since this option was mentioned as having an impact on bus speed I wanted to clarify that it did not when I tried.
 

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I'm having a strange experience overclocking. I can do 3.9GHz no sweat, but adding even a quarter multiplier (39.25) is unstable even if I add another 50mV to the Vcore (i.e. 1.40 -> 1.45). It's not making much sense to me. The VF curve can't be that steep can it? I'm using P-state overclocking - could that be part of it? I'll try generic multiplier overclocking next, but I was curious if anyone has ever seen this.
 

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@The Stilt: Since you are a strong advocate of leaving LLC at Auto/0, could you answer my question about what kind of overshot to expect?

Does 1.35v LL02 overshoot to (much) higher voltage than 1.375v LLC0?

(I wish I knew where to put the probes on the back of the CPU then I would just measure all this stuff myself.)
 

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Quote:
Originally Posted by pantsoftime View Post

I'm having a strange experience overclocking. I can do 3.9GHz no sweat, but adding even a quarter multiplier (39.25) is unstable even if I add another 50mV to the Vcore (i.e. 1.40 -> 1.45). It's not making much sense to me. The VF curve can't be that steep can it? I'm using P-state overclocking - could that be part of it? I'll try generic multiplier overclocking next, but I was curious if anyone has ever seen this.
In one of my tests I needed to add a whole 0.1 v to go from 4.00 to 4.05 GHz. Seems quite steep to me.
 

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Quote:
Originally Posted by The Stilt View Post

...

At the same 925mV voltage, which the 1700 is completely stable the 1800X PR is unable even to post. 975mV is required to make it to post constantly and full stability requires 1025mV (setpoint). What makes it even more interesting is the fact that the 1800X PR has significantly higher leakage (29%), than the 1700 which I specifically binned for low leakage.
This reminds me of a question that has been hanging in my attention background: Why does progressively higher leakage (1700 --> 1800X) correlate with progressively higher maximum clock frequency?
 

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Quote:
Originally Posted by bluej511 View Post

You need to enable wpump header in qfan controls or wherever it is if you plugged your pump in there. Mine still won't give me rpms though
Thanks so much, my waterpump owes you it's life.
thumb.gif
 

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Quote:
Originally Posted by Timur Born View Post

In one of my tests I needed to add a whole 0.1 v to go from 4.00 to 4.05 GHz. Seems quite steep to me.
Oh wow ok. Thank you for the reply.
 

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Quote:
Originally Posted by Timur Born View Post

@The Stilt: Since you are a strong advocate of leaving LLC at Auto/0, could you answer my question about what kind of overshot to expect?

Does 1.35v LL02 overshoot to (much) higher voltage than 1.375v LLC0?

(I wish I knew where to put the probes on the back of the CPU then I would just measure all this stuff myself.)
That depends on the current drawn by the domain on which the load-line adjustment is applied to.
If the voltage overshoots by 10-20mV (which it based on my experience does) when the load-line is set to "Auto" (±0%), then the voltage overshoot will be:

((1.425 / 2) / 1000) * Idd

If the current drawn by the domain (Idd) is 100A, then the overshoot will be 71.25mV (81.25 - 91.25mV including the existing 10-20mV overshoot). "Level 2" translates to -50% (i.e. / 2).
 

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Quote:
Originally Posted by kaseki View Post

This reminds me of a question that has been hanging in my attention background: Why does progressively higher leakage (1700 --> 1800X) correlate with progressively higher maximum clock frequency?
Because these chips have already been pushed so far at stock, that we're already hitting the voltage limits (rather than the usual thermal or clock limits). Silicon with higher SIDD generally requires less voltage at ISO frequency and has at least somewhat better voltage scaling. They draw more current and run hotter than the silicon with lower leakage, but in case the silicon isn't thermally limited that's not a disadvantage but an advantage.

There is a reason why they are binned this way at the factory as well
wink.gif
Same was done with Vishera 9k-series CPUs. Using high leakage silicon is most likely the only way to produce 1800X models with their 4.1GHz MSCXFC, without breaching the reliability thresholds for VDDCR_CPU.
 

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Quote:
Originally Posted by LittleVulpix View Post

HyperX Fury CL15 2400MHz. ( kit number is HX424C15FBK4/64 )
2933 whit 4 x 16 module of 2400 memory ? lol , i i realy do not understand anymore, whit this cpu it's all like trowing a dice, like in D&D!!
 

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DREAMS OF GETTING A 4k STABLE OC



SHATTERED!!!

@ProTekkFZS

With the Pstate adjusting Vid are you still using some offset as well ?
In the end i would love to be able to set a 50% clock state coz it seems you need very little to take it from underclock to Pstate0
 

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No CPU OC.
No BLCK adjustment.
Just going for RAM CLK.

Now on 3200MHz, gonna keep testing and then lower timings and OC CPU.



+rep
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The Stilt
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, thank you for your shares
thumb.gif
.
 

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Quote:
Originally Posted by The Stilt View Post

Because these chips have already been pushed so far at stock, that we're already hitting the voltage limits (rather than the usual thermal or clock limits). Silicon with higher SIDD generally requires less voltage at ISO frequency and has at least somewhat better voltage scaling. They draw more current and run hotter than the silicon with lower leakage, but in case the silicon isn't thermally limited that's not a disadvantage but an advantage.

There is a reason why they are binned this way at the factory as well
wink.gif
Same was done with Vishera 9k-series CPUs. Using high leakage silicon is most likely the only way to produce 1800X models with their 4.1GHz MSCXFC, without breaching the reliability thresholds for VDDCR_CPU.
Thank you for the clarification. +rep, I think, but I didn't see any change.
 

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Quote:
Originally Posted by The Stilt View Post

((1.425 / 2) / 1000) * Idd

If the current drawn by the domain (Idd) is 100A, then the overshoot will be 71.25mV (81.25 - 91.25mV including the existing 10-20mV overshoot). "Level 2" translates to -50% (i.e. / 2).
Thanks for the answer. Where does that 1.425 in your calculation come from? Did you assume 1.425v Vcore setting instead of my 1.35v example?

And while I have your attention:
wink.gif


Why does my 1800X throttle down to x35.3/35.8/36 on different cores during *non* AVX ITB/Linpack loads. Thermal and current don't seem to be the issue, especially since it stays at x37 for hours using AXV, Prime95 or Realbench under higher current.
 

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Quote:
Originally Posted by Timur Born View Post

Thanks for the answer. Where does that 1.425 in your calculation come from? Did you assume 1.425v Vcore setting instead of my 1.35v example?

And while I have your attention:
wink.gif


Why does my 1800X throttle down to x35.3/35.8/36 on different cores during *non* AVX ITB/Linpack loads. Thermal and current don't seem to be the issue, especially since it stays at x37 for hours using AXV, Prime95 or Realbench under higher current.
No, 1.425 is the default Rll in mOhms.
Load-line affects the Rll (virtually) and Rll and the Idd together define the change in the voltage.

Most likely you are hitting the TDC limit. That's the most common reason why Ryzen throttles below the MACXFRC.
 
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