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Old crazy guy
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Discussion Starter · #1 · (Edited)
These are the custom power plans I've made for my 5950x.
They should work as well for the 3000 series (let me know if you test it).

The temperature in idle for the CCD should be kept at a comfortable 35c without the hacksaw graph in HWInfo.
Both are allowing max boost clock on my 5950x.

Please check before and after with AIDA64 memory benchmark; if there's something wrong the latency could increase by 1 nanosecond.

Best would be to use Process Lasso to switch specific applications to use the Ultimate profile only when needed

Let me know if you experience issues.

AMD Ryzen™ Balanced LowPower

Modified out of the Balanced plan so it has the Power Slider.
It's a nice compromise between performance and power consumption in the middle setting for the slider.
Quite reactive to user input; should behave same as Balanced or better. No CCD temp spikes for low usage threads but temperatures can quickly go up with load.
Slider to the max will keep the vCore high and will be a bit more reactive, in the middle vCore should lower but not that often.

NEW 25/01/2021 v8:
  • Small modification, now it's very responsive also after idling
Version v8:


AMD Ryzen™ Ultimate Performance

Modified out of the Ultimate Performance plan so it doesn't have the Power Slider.
It's a no-compromise for performances, slight increased power consumption but yet nice temperatures in idle.
There are few CCD temps spikes, CPU die temp will fluctuate but shouldn't go up and down too quickly.

NEW 23/01/2021 v5:
  • Reverted back to autonomous mode, high CPU-z scores
  • Same AIDA memory latency as Ultimate
  • Disabled core parking as the AIDA latency hit is too big and couldn't reduce it, also possibly a source of issues I can't reproduce

Version v5:


AMD Ryzen™ Balanced Snappy

Modified out of the Balanced plan so it has the Power Slider.
It's a power hungry profile focused on responsiveness with autonomous mode enabled.
High temp spikes and high CPU usage, vCore almost always to max.

NEW 25/01/2021 v1:
  • Initial release
Version v1:

How to install

Download the POW file.
Start a Command prompt with Administrative privilege (search for command prompt in start menu).

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Import the plan with "powercfg -import filename.pow":

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Replace the directory name as needed.

Tools

QuickCPU

Highly recommended if you want to make your own customizations or compare with other profiles


First versions (outdated):

The first one is modified out of the Balanced profile so it has the Power Slider.
It's a nice compromise between performance and power consumption in the middle setting for the slider.
Min state on my 5950x: 2200 MHz and 0.9V


The second one is modified out of the Ultimate Power profile so it doesn't have the Power Slider.
It's a no-compromise for performances, slight increased power consumption but yet nice temperatures in idle.
Min state on my 5950x: 2880 MHz and 0.95V

 

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Hi!
Can i use 24/7 your balanced profile dor gaming and desktop use for a 5900X?
Also when benchmarking, should i change profile? it affects scores?
Thanks in advance
 

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Old crazy guy
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3,327 Posts
Discussion Starter · #3 ·
Hi!
Can i use 24/7 your balanced profile dor gaming and desktop use for a 5900X?
Also when benchmarking, should i change profile? it affects scores?
Thanks in advance
There are trade-offs; you are probably going to loose something with the Balanced with the Power Slider in the middle.
Maybe just a tiny bit with the slider to the max.

I think Process Lasso free is supporting performance mode with automated power profile switching.
That's for me the best solution.

The Ultimate gives a little boost, I'd always switch to it when benchmarking.

Ultimately, best way is to bench by yourself all the Balanced with the slider in the middle/max against the Ultimate.

I'm using a clean Windows install for benchmarks so I didn't compared them as in my main install the benchmarks have too much run variations.
 

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I'm using Windows High Performance power plan. My 5900x idles at a nice cool 28.5C in Windows with RyzenMaster running and multiple browser windows open. Oh, that's on air with the Noctua NH-D15 also. :)
 

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talking about power plans, here's my custom version, no core parking, low latency, high boost, good idle. 3900x open loop
has worked really good with PBO on my 2700x, had to change a few values for the 3900x


2474878
 

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Nice! I installed the ryzen ultimate power plan hoping it can keep my curve optimizer settings more stable on my 5950x.
 

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Old crazy guy
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Discussion Starter · #8 · (Edited)
Seems I have found the key to have CPPC2 behave properly :D

View attachment 2475111

No more temperature spikes with low core usage, clocks going down to 2200 MHz and both VIDs and vCore below 1.0V.
All the temps goes down to 36c in idle.
And when I mean idle that's with Chrome with hundreds of tabs and some other stuff open in the background.

If you want to modify your custom plan the key is to set the "Heterogenous thread scheduling policy" to "Prefer performance processors" and "Heterogenous short running thread scheduling policy" to "Prefer efficient processors".
This is valid only for the Balanced plan with the power slider in the middle; I strongly advise against using it with the slider to the max for better performances.
It will mess up all the settings and the vCore and temps will stay high with a lot of spikes in CCD temp with low usage threads.
Use instead the Ultimate Performance; it will still set vCore always high and temps higher but will schedule properly the threads and will not have huge spikes in CCD temps.

View attachment 2475115
 

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Old crazy guy
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Discussion Starter · #9 ·

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Old crazy guy
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Discussion Starter · #10 ·
Very nice temperatures in general and stable and flat CCD temperature in idle:

2475131
 

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Overclock the World
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Ooh, fantastic work !
Can you see on effective clock, some of the threads or CCX and full CCDs - going into hibernation mode ?
They will be fully grayed out like here

This is crucial in order to achieve higher frequency :)
 

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Old crazy guy
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Discussion Starter · #12 ·
Ooh, fantastic work !
Can you see on effective clock, some of the threads or CCX and full CCDs - going into hibernation mode ?
They will be fully grayed out like here

This is crucial in order to achieve higher frequency :)
I'm not sure cause I'm not confident I didn't messed up my HWInfo layout :)
But I think while testing on the benching install they were greying out, not sure...
If someone could test would be nice.

In Ryzen Master they are sleeping but maybe it's not the same:

2475141
 

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Overclock the World
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I'm not sure cause I'm not confident I didn't messed up my HWInfo layout :)
But I think while testing on the benching install they were greying out, not sure...
If someone could test would be nice.

In Ryzen Master they are sleeping but maybe it's not the same:

View attachment 2475141
Usually HWInfo should show the same thing for you ~ but CPPC and preferred cores have to be enabled in the bios
Effective clock sleep state will be detected if the core stays longer in sleep bellow 1%
Often it can also be put to sleep on maximum boost state. Low idle like visualized is not needed for it to function
But sillicon stress lowers, if deep hibernation is working

HWinfo before launch, this setting needs to be enabled
Main menu bottom right
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If you can optimize the low idle power state - there is a little gain to get,
as there is a powerstate between hibernation and frequency boost
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This should lower inter-core latency a tiny bit

The key to the boost is not only utilizing/exploiting an more aggressive "low->peak" boost state
But also having fully sleeping cores as foundation. Else the mode won't be triggered
The Bios needs to have C-Sates, DF-States, and Package C6 states working
(later ones you can enforce in the future with ZenStates by IrusanovBG/infraredbg [OCN])

1 CCD users seems to be peak perfectly at 7% idle state
2 CCD users are different.
But curve optimizer and fMAX/boost override will shift the boosting curve and so that little number

I do think it's possible to make an universal powerplan which does utilize this
Don't think there is any reason to have "power sliders" as for "slower intercore perf" , you can just utilize the DPM throttle state inside the same SMU menu in AMD CBS
Which effectively lowers how fast the CPU will achieve max frequency and is usually used for notebooks or can be used for mining farms
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Overall, by comparing intercore latency (Purple = my current)
You can skip all the low power powerplans, as they effectively throttle where there shouldn't be throttle
For ITX systems, U or G series notebooks ~ AMD has already optimized it and there is a triggereable setting in the bios

At the end, i do think that you/we users can exploit this boost bump futher
The position you put the bump, is the position you should enable chipset interleaving on
Be it 256kB or 512kB :giggle:
 

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Old crazy guy
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Discussion Starter · #14 ·
I should have all that's needed enabled in the BIOS but right now I'm back with the Master and doing some testing so I'm not 100% sure.

Could be also this BIOS version, F31, which could have something messed up.

The problem with the idle state is that below 100% will not work in autonomous mode and then use P-States with the Win scheduler instead of CPPC2.
And this is bad for temperatures and responsiveness.
You'll see clocks and voltages going down but the temperatures are telling another story; the CPU is not doing internal gating.

I'm considering to explore it for the Ultimate Performance profile but as you said it's hard to find a universal sweet spot.
Thinking about adding more of this exotic power management stuff in my tool, OCMaestro.

Anyhow for the Balanced LowPower plan it's a great milestone, have to test yet for performances but doesn't seem to be greatly impacted.
 

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Overclock the World
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I should have all that's needed enabled in the BIOS but right now I'm back with the Master and doing some testing so I'm not 100% sure.

Could be also this BIOS version, F31, which could have something messed up.

The problem with the idle state is that below 100% will not work in autonomous mode and then use P-States with the Win scheduler instead of CPPC2.
And this is bad for temperatures and responsiveness.
You'll see clocks and voltages going down but the temperatures are telling another story; the CPU is not doing internal gating.

I'm considering to explore it for the Ultimate Performance profile but as you said it's hard to find a universal sweet spot.
Thinking about adding more of this exotic power management stuff in my tool, OCMaestro.

Anyhow for the Balanced LowPower plan it's a great milestone, have to test yet for performances but doesn't seem to be greatly impacted.
That OCMaestro name sounds great :)
PackageC6 state, i know sadly seems to bug out.
Cores go only in a low power state, only after one workload, even if the powerplan utilizes the low idle state

If you can, ask infraredbg here for the zenstate alpha, so you can finetune the powerplans a bit by utilizing the PackageC6 state override functionality
You should be able to also play around with per CCX frequency OC (CCD Delta) and combined with the forced sleep functionality ~ be able to work on the "speed" how fast the cores boost. Well you know :)

If you want, deconstruct these two powerplans
~ EDIT: fixed the link
the ComputerBase one, i was using as foundation ~ but CPPC is borked on Matisse.
The sz one ~ also from ComputerBase (funny) has functional CPPC for Matisse, but i don't know if it's useful for Vermeer
The idle_mod version, you can try to learn from it the idle state ~ as the exploit is working very well & benchmark results are at worst 0.1ns consistent , after set up
It just has a problem that after the idle state, the powerplan is boosting too slow
Something surely can be done ~ soo i share you both as foundations for research. I think they will help you optimize yours well

Sadly i can not relate to what you have experienced
Low voltage = low powerdraw = low heat, on my side
Once stuff actually does deep sleep
Both shared are far away from optimal ~ soo i hope you can find the positive points on them and reinvent the wheel a bit :p
 

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Old crazy guy
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Discussion Starter · #16 ·
That OCMaestro name sounds great :)
PackageC6 state, i know sadly seems to bug out.
Cores go only in a low power state, only after one workload, even if the powerplan utilizes the low idle state

If you can, ask infraredbg here for the zenstate alpha, so you can finetune the powerplans a bit by utilizing the PackageC6 state override functionality
You should be able to also play around with per CCX frequency OC (CCD Delta) and combined with the forced sleep functionality ~ be able to work on the "speed" how fast the cores boost. Well you know :)

If you want, deconstruct these two powerplans
the ComputerBase one, i was using as foundation ~ but CPPC is borked on Matisse.
The sz one ~ also from ComputerBase (funny) has functional CPPC for Matisse, but i don't know if it's useful for Vermeer
The idle_mod version, you can try to learn from it the idle state ~ as the exploit is working very well & benchmark results are at worst 0.1ns consistent , after set up
It just has a problem that after the idle state, the powerplan is boosting too slow
Something surely can be done ~ soo i share you both as foundations for research. I think they will help you optimize yours well

Sadly i can not relate to what you have experienced
Low voltage = low powerdraw = low heat, on my side
Once stuff actually does deep sleep
Both shared are far away from optimal ~ soo i hope you can find the positive points on them and reinvent the wheel a bit :p
Thanks for sharing, I'll check it out :)
But I see only one "sz_ryzbal_v4.pow" plan inside the zip.

Of course I don't do proper QA eheh
I've left min unparked cores to 100% for AC...
Now the cores are parking but not in idle... have to check why and if it's a good thing or not (probably not).
HWInfo still refuses to show the parking state but QuickCPU and the Resource Monitor are now showing the parked state.

Low voltage = low powerdraw = low heat; don't think it's like that.
You are assuming low powerdraw and this is not necessarily true.

I think under the hood in P-State mode there's more power draw.

P-State: 2200 MHz, VIDs 0.9V, vCore 0.9V
CPPC2: 3600 MHz, VIDs 0.95V, vCore 1.4V

At these low levels a difference of current draw from 0.1A to 0.3A can make a world of difference and easily double the powerdraw despite the lower voltage.

In CPPC2 the temperatures are about 2c lower on average.
You need a 5950x where you can clearly see the cIOD impact on CPU Tcl/Tdie.
Also the CCDs have a 2c degrees and more lower average and min.
The reported power draw I don't think is reliable; it's what the processor is telling and could be blah blah.

Also I'm pretty sure only in CPPC2 mode the CPU is doing internal gating shutting down dynamically what is not actively used.
It's not much but it's enough to contribute on those 2 degrees improvement.
 

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Overclock the World
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Thanks for sharing, I'll check it out :)
But I see only one "sz_ryzbal_v4.pow" plan inside the zip.

Of course I don't do proper QA eheh
I've left min unparked cores to 100% for AC...
Now the cores are parking but not in idle... have to check why and if it's a good thing or not (probably not).
HWInfo still refuses to show the parking state but QuickCPU and the Resource Monitor are now showing the parked state.

Low voltage = low powerdraw = low heat; don't think it's like that.
You are assuming low powerdraw and this is not necessarily true.

I think under the hood in P-State mode there's more power draw.

P-State: 2200 MHz, VIDs 0.9V, vCore 0.9V
CPPC2: 3600 MHz, VIDs 0.95V, vCore 1.4V

At these low levels a difference of current draw from 0.1A to 0.3A can make a world of difference and easily double the powerdraw despite the lower voltage.

In CPPC2 the temperatures are about 2c lower on average.
You need a 5950x where you can clearly see the cIOD impact on CPU Tcl/Tdie.
Also the CCDs have a 2c degrees and more lower average and min.
The reported power draw I don't think is reliable; it's what the processor is telling and could be blah blah.

Also I'm pretty sure only in CPPC2 mode the CPU is doing internal gating shutting down dynamically what is not actively used.
It's not much but it's enough to contribute on those 2 degrees improvement.
Try Open Hardware Monitor - Core temp, fan speed and voltages in a free software gadget
It's where most devs base their tracking methods of, and has a bit more assistance than HWInfo
Although HWinfo should show it with the flag ~ strange

I do think too that HWInfo , well overall the SMU calls are being told nonsense
Some stuff like PPT makes no sense - but it could be just that SMU calls are slower and an estimate is only being told
Well for many different reasons, i focus on "relative performance" and not the applied P-State frequency.

Technically even with the P-States set to 99% , which is what before Matisse users where using under low power idle plans
Internally like you mentioned, not only the usage but the p-draw was lower
Effective frequency was also lower, even on a 100% p-state

2200Mhz instead of 550mhz for Vermeer, looks like you are focusing p-states as low idle states ?
I really wonder why you can't go lower.
Oh i seems like grabbed the wrong 7zip, oops
 

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Old crazy guy
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Discussion Starter · #18 ·
BTW the Ultimate Performance profile can also achieve stable and low temperatures in idle with 32.8c min on CCD1.
A few temp spikes because that's what is meant to do, being very reactive:

2475156
 

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I dunno whats going on, but my vCore is almost all the time above 1.45 V, also with the v3 balanced plan provided by you.

v3 balanced plan (only idle):
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with your first balanced plan I have real idle.
 

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Discussion Starter · #20 ·
Try Open Hardware Monitor - Core temp, fan speed and voltages in a free software gadget
It's where most devs base their tracking methods of, and has a bit more assistance than HWInfo
Although HWinfo should show it with the flag ~ strange

I do think too that HWInfo , well overall the SMU calls are being told nonsense
Some stuff like PPT makes no sense - but it could be just that SMU calls are slower and an estimate is only being told
Well for many different reasons, i focus on "relative performance" and not the applied P-State frequency.

Technically even with the P-States set to 99% , which is what before Matisse users where using under low power idle plans
Internally like you mentioned, not only the usage but the p-draw was lower
Effective frequency was also lower, even on a 100% p-state

2200Mhz instead of 550mhz for Vermeer, looks like you are focusing p-states as low idle states ?
I really wonder why you can't go lower.
Oh i seems like grabbed the wrong 7zip, oops
Thanks, downloading!

The cores are not parking in idle so I'm assuming that is switching in P-State mode instead of staying in CPPC2.
It shouldn't, I hope it's working the same for everyone and not just on my BIOS/AGESA/profile...
Seems to be a zombie mode between autonomous and not autonomous; either way it works like a charm!

The core parking is really needed only for Boosting as it does indeed allow more power budget (true or not).
For now I guess it's a satisfying enough solution.

I'm using Open HW monitor in for OCMaestro as it's quite handy.
But indeed it's just doing SMU calls so maybe I'll just do it myself.
The problem is the overhead; a huge snapshot every refresh in a c# list which is quite CPU intensive to manage.
 
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