Overclock.net banner

Status
Not open for further replies.
201 - 220 of 679 Posts

·
DRAM Obsessor
Joined
·
1,034 Posts
One thing to seemingly keep in mind is..while the old way seemed to be to undervolt a bit so it would clock higher without hitting the FIT voltage, undervolting seems to do very weird things on Zen2. Everyone is reporting that an undervolt actually got them consistently higher clocks, but when actually benching the machines, the scores go way down. Games too.

One thread on reddit: https://www.reddit.com/r/Amd/comments/cdkbkk/psa_undervolting_does_not_retain_performance_with/

EDIT:I see you have already addressed the downsides of undervolting. NVM

So it seems while undervolting may help clocks, it isn't the answer for actual overclocking.

As far as the 'solution' I'd still be curious to hear it even in a PM. I work in electrical engineering and can get my hands on a bit of equipment :D I mostly work in RF, but still.
I think the problem may be undervolting too much.
 

·
Registered
Joined
·
15 Posts
Any information (outside the marketing material) related to Zen 2 is extremely hard to find.
Finding any information related to the IOD is as easy as finding reliable evidence about Sasquatch.

According to AMD the IOD has 24 Gen. 4 lanes in total, four 3.1 Gen. 2 USBs, two Gen. 3 SATAs and the usual misc IO (SMBUS, SPI, etc).

The CCDs used in Matisse are not the same used in the other products. The IOD might or might not be.
So basically it makes no difference what would actually be available, when there is no way to use it.
What do you mean that the CCDs are not the same between Matisse and the other products? I though that part of the idea behind the chiplets is that the CPU ones could be reused across all the non-APU product lines, like ThreadRipper and EPYC (Unless AMD wants to do an APU with an IO, CPU and GPU chiplets). Are you implying that Rome will use a different CPU chiplet than the one found in Matisse?


Regarding the IO die, what AMD said is that they use the same design for both Matisse IO die and the X570 Chipset, but Matisse one is manufactured using 12nm process whereas X570 uses 14nm. Sources:
https://www.techpowerup.com/256511/amd-ryzen-3000-matisse-i-o-controller-die-12nm-not-14nm
https://twitter.com/IanCutress/status/1138443875154944000
This pretty much means that X570 has an unused IMC while Matisse IO die doesn't expose some of the new I/O like 8 more USB Ports (As X570 has 12) or the multiplexed configurable 8 PCIe/8 SATA (Plus 4 dedicated SATA), which personally I believe that would be wonderful for two OCuLink Ports that depending on cable could be used for a 4x NVMe or a breakout cable for 4 SATA. Matisse IO die should also have slighty less power consumption given that it uses a smaller process.

I know that exposing the additional I/O is not possible in Socket AM4 because it shouldn't have enough unused/reserved Pins for a backwards compatible revision to begin with. However, that applies to AM4 products only, maybe with a redesigned package for a different pinout more of that I/O could be exposed. For example, the Zen based EPYC Embedded 3000 series exposed the full feature set of Zeppelin (32 Lanes instead of only 24 like on AM4, RDIMM support, and the multiplexed four 10G MACs that before EPYC Embedded launch were completely unknow), and there is also an embedded Raven Ridge version that exposes 4 DisplayPorts and 6 USBs, whereas in Socket AM4 they only do 3 and 4, respectively.
Given the fact that the Matisse IO die, if fully exposed, has enough I/O to drive a decently sized platform with no other Chipset or major controller help (Except the Super I/O), I find that an EPYC Embedded version would be an absolute monster. I even did a long rant about how I believe that for small to medium sized systems (mITX/mATX) you could happily drive the full platform with the Zen SoC I/O without needing a Chipset, which if you're interesed you can read here: https://forums.anandtech.com/thread...ike-ryzen-epyc-embedded-alternatives.2565304/
Matisse solves the Zeppelin weakness since Zeppelin had only 4 USB Ports, which were not close to enough for consumer usage (Even Server Motherboards like Supermicro ones had to use two USB Hubs in its EPYC Embedded Motherboards), but Matisse with 12 is excellent. However, due to lack of information, I don't know if it has less total possible PCIe Lanes (24 vs 32), if the USB Ports are dedicated or multiplexed on something else, and so on. Is hard to theorycraft my perfect Matisse SoC Motherboard without that info :(


In your personal opinion, do you find Zen 2 SoC potential if switched to another format interesing? While I understand that Socket AM4 was designed that way due to cost concerns, I think that it is limiting it a lot, which is the reason why I don't find satisfaction in that platform, yet fell in love with the EPYC Embedded line. I expect a Matisse based version to be even better, UNLESS AMD sticks to the previous generation pinout...
 

·
Meddling user
Joined
·
7,423 Posts
What brand of nvme drive do you have?
Sorry for delayed response, as post above yours had info, I thought I would point it out after I had something new to post. It is an Intel 660P 1TB in M2_1 of C7HWIFI.

I have not had to restore image of OS for few days now, as getting better at knowing what to set to get to OS when change OC profile. So this is same "image" of OS as yesterday, again only the known issue shows in CBS.log link.

I got lucky with my memory controller silicon. 3800 1:1:1 was np. Only way to reach it is with bclk at 101.8mhz as there is something in the bios that will not let you go above that. You get C5 error code as soon as you do. I know I have the head room for at least another freq step if not two @ 1:1:1. Im currently tightening 3733cl14 right now. Might be able to get it at 14-14-14-24-38-1T
Nice :) .

I can get 3800MHz, without BCLK, but not fully stable for me.

SOC: 1.075V, VDDG: 1.035V, VDIMM: 1.425V, VTTDDR: 0.7125V.


Pretty much all my profiles use :clock: The Stilt's :clock: 3466MHz timings, GDMD, 1T. Not yet at a stage for tweaking timings further on my end. I have been more concerned with profiling voltages for x target, seeing how PBO behave, tinkering with UEFI settings to see how it then reflect in Ryzen Master, ASUS Turbo V, POST process voltages, etc. I update this album with reasonable stability tested benches. None have Performance Bias, OS, any or other tweaks, just straight up UEFI setup/OS and tested.
 

·
Registered
Joined
·
1,732 Posts
Anyone already tried OCing 2x16 kits on Zen2? I only see 2x8 results so far.
 

·
Registered
Joined
·
1,432 Posts
Nice :) .

I can get 3800MHz, without BCLK, but not fully stable for me.

SOC: 1.075V, VDDG: 1.035V, VDIMM: 1.425V, VTTDDR: 0.7125V.


Pretty much all my profiles use :clock: The Stilt's :clock: 3466MHz timings, GDMD, 1T. Not yet at a stage for tweaking timings further on my end. I have been more concerned with profiling voltages for x target, seeing how PBO behave, tinkering with UEFI settings to see how it then reflect in Ryzen Master, ASUS Turbo V, POST process voltages, etc. I update this album with reasonable stability tested benches. None have Performance Bias, OS, any or other tweaks, just straight up UEFI setup/OS and tested.

Thanks for the share chap! Same here, i can only get it fully stable if i keep my ram at low temps. Even with CL14 :)
Maybe when you have some time you can try to blow a fan on them just to see if you can pass Ramtest for x % :)
 

·
Because I was inverted...
Joined
·
726 Posts
Not possible using the standard tools.
The FIT decisions are based on fused (silicon specific) parameters and models.
What tools are you using to view the fused parameters on the CPU? I'm a developer, and would love to figure out how to do this
 

·
Premium Member
Joined
·
20,323 Posts
Sorry for delayed response, as post above yours had info, I thought I would point it out after I had something new to post. It is an Intel 660P 1TB in M2_1 of C7HWIFI.

I have not had to restore image of OS for few days now, as getting better at knowing what to set to get to OS when change OC profile. So this is same "image" of OS as yesterday, again only the known issue shows in CBS.log link.
Thanks gups. I think Samsung are the ones having issue.
 

·
Premium Member
Joined
·
2,753 Posts
Discussion Starter · #210 ·
What tools are you using to view the fused parameters on the CPU? I'm a developer, and would love to figure out how to do this
Custom tools.

If you're a developer how has signed NDA with AMD, then you should already have access to partial fuse descriptions.
Obviously far from everything has been described.
 

·
Not New to Overclock.net
Joined
·
1,688 Posts
So I just installed my R5 3600 into my ASUS Prime X370-Pro running the latest 5008 BIOS (AGESA 1.0.0.2). I thought I would share an observation that might be helpful to some.

When I first boot up my machine after a CMOS reset or the CPU install, I can only boot with a very low RAM speed such as 2400 MHz. Otherwise I get stuck in a boot loop with no POST.

After the first boot, I'm able to set far higher speeds. I'm currently testing options around 3600 MHz with Prime95, with manually set matching FCLK.
 

·
Premium Member
Joined
·
2,753 Posts
Discussion Starter · #212 · (Edited)
Based on the testing I did, the higher-end single CCD SKUs could potentially benefit more from undervolting.
Thats because the two CCD SKUs seem to have one "prime cut" (high quality CCD) and one significantly lower quality CCD in them.
Again, that's based on a single sample however, similar behavior has been illustrated in the test made by other reviewers.

At ±0mV offset there is no stretcher activity under load, as expected. That'll change as the voltage drops.
Already at -25mV the weaker CCD has some stretcher activity present (core 14). At -50mV minor activity can be observed on cores 9, 13 and 14.
At -75mV the activity increases on cores 9, 13, 14 and activity also on core 11 can be seen. At -100mV all active cores on CCD1 have activity going on, the weakest cores (13, 14) are practically out.

Ideally there should be a way to detect the "effective" clock the CPU is running at, but so far I haven't been able to find one.

So undervolting Ryzen 3000-series isn't recommended in general, unless the performance is evaluated prior and post the changes (in multiple workloads).

Note:
Core 0, 4, 10 and 12 are factory harvests.
Cores 1 & 5 are the best cores of this CPU and by a huge margin.
No activity on them until -175mV offset.



















 

·
Registered
Joined
·
15 Posts
Those were some epyc pics. However, I think that every undervolting Zen 2 result I saw so far was @ stock clock. If along with the undervolt, clock speed was underclocked (At the cost of performance, obviously), would the clock stretchers go back to zero activity at same voltage?

From both performance and stability standpoint, would an hyphotetical 4.2 GHz with an average 20% clock stretcher activity or so due to undervolting perform better or worse, and consume more power or less, than one at 3.6 GHz with 0% clock stretcher activity? Basically, should people that want to save power at the cost of performance prefer to put the effort in the clock stretcher or reduce clock speed? Both choices reduces performance.
 

·
Registered
Joined
·
1,588 Posts
Based on the testing I did, the higher-end single CCD SKUs could potentially benefit more from undervolting.
Thats because the two CCD SKUs seem to have one "prime cut" (high quality CCD) and one significantly lower quality CCD in them.
Again, that's based on a single sample however, similar behavior has been illustrated in the test made by other reviewers.

At ±0mV offset there is no stretcher activity under load, as expected. That'll change as the voltage drops.
Already at -25mV the weaker CCD has some stretcher activity present (core 14). At -50mV minor activity can be observed on cores 9, 13 and 14.
At -75mV the activity increases on cores 9, 13, 14 and activity also on core 11 can be seen. At -100mV all active cores on CCD1 have activity going on, the weakest cores (13, 14) are practically out.

Ideally there should be a way to detect the "effective" clock the CPU is running at, but so far I haven't been able to find one.

So undervolting Ryzen 3000-series isn't recommended in general, unless the performance is evaluated prior and post the changes (in multiple workloads).

Note:
Core 0, 4, 10 and 12 are factory harvests.
Cores 1 & 5 are the best cores of this CPU and by a huge margin.
No activity on them until -175mV offset.
I've noted 2 other people with similiar observation of their 3900X samples. One CCD is golden and the other CCD is garbage in varying degree.
I think this is how AMD can hit TDP(105W) and as well advertise their BOOST frequency as sold. One CCD will usually hit them targets at times but the other will probably not have as much luck.
This will bode well for 3950X as both chips WILL HAVE TO be great bins to be able to hit targets. Though the low base-clock is a misnomer of things in the end so they can throw in some mediocre bins there.
 

·
Premium Member
Joined
·
2,753 Posts
Discussion Starter · #215 ·
Those were some epyc pics. However, I think that every undervolting Zen 2 result I saw so far was @ stock clock. If along with the undervolt, clock speed was underclocked (At the cost of performance, obviously), would the clock stretchers go back to zero activity at same voltage?

From both performance and stability standpoint, would an hyphotetical 4.2 GHz with an average 20% clock stretcher activity or so due to undervolting perform better or worse, and consume more power or less, than one at 3.6 GHz with 0% clock stretcher activity? Basically, should people that want to save power at the cost of performance prefer to put the effort in the clock stretcher or reduce clock speed? Both choices reduces performance.
Stretchers are not used in OC-Mode, which is activated by underclocking as well.
So if you want to run at Vmin all the time, you must use OC-Mode (i.e. no Turbo available).

The stock V/F on Matisse (above 3.6GHz) is absurdly accurate. The biggest issue is definitely the discrepancy between the different cores and the CCDs.

 

·
Registered
Joined
·
1,732 Posts
@The Stilt,
My MSI Godlike X570 warns me that "above 1.10V CPU SOC voltage the Gen4 speed will downgrade or fall back to Gen3 speeds". Any idea why this is, does ASUS do that too?
 

·
Registered
Joined
·
1,588 Posts
What do you mean?
As you observed with your 3900X which is 12core-24thread part @ 105W we get one "golden" chiplet one "turd" chiplet (requires lots more voltage to hit same target frequency)
The 16-core-32thread 3950X @ 105W should in theory have to have better chiplets to be able to hit it's advertised specifications at the same wattage. (though it does have lower base clock to make finding a pair easier to meet spec)
It might be two "gold" chiplets to be able to meet spec but we might see the same as with the 3900X with 1 good and one throw in whatever to fill the spot.

Just speculation and conjecture on how they might do it to be able to meet demand with available parts on hand from manufacturing depending on how many good vs bad chiplets they get.
 

·
Premium Member
Joined
·
2,753 Posts
Discussion Starter · #219 ·
@The Stilt ,
My MSI Godlike X570 warns me that "above 1.10V CPU SOC voltage the Gen4 speed will downgrade or fall back to Gen3 speeds". Any idea why this is, does ASUS do that too?
1.100V is the official guideline value from AMD.
I'm not sure if ASUS boards warn or not, but they don't automatically exceed 1.1V either.
 

·
Registered
Joined
·
1,732 Posts
Clear, I've seen it's setting 1.10V by itself when running XMP. I've tried 3733 16-16-16-36 2T (2x16 3200C14 kit) but it was throwing errors in 1iusmus's TestMem5. Incrased to 1.15V and it already did 2 passes.
 
201 - 220 of 679 Posts
Status
Not open for further replies.
Top