[nick name]

Ooooh a Matisse Timing Checker.

 

[upgraditus]

For 2 CCD SKUs, 2 DPC SR configuration seems to be the way to go.
Both the 3600 and 3700X did 1800MHz UCLK on 1 DPC DR config, but most likely due to the discrepancy of the two CCDs in 3900X, it barely does 1733MHz on those DIMMs.
Meanwhile with 2 DPC SR config there is no issue in reaching 1866MHz FCLK/UCLK. That's pretty unfortunate since 8GB DIMMs cannot be considered as desireable or future proof as 16GB ones, due to the 32GB limitation.
Sure 16Gb ICs exist nowdays (hence allowing 16GB SR modules), but none of them can come even close to B-die in terms of frequency and timings.

Phy at AGESA defaults, except ProcODT of 40.0Ohm, which is an ASUS auto-rule for Optimem III.
tRDRDSCL & tWRWRSCL cannot be set < 4 CLK when the UCLK is operating at the limit, but that doesn't seem to affect the latency too much.
4 CLK already provides 100% efficiency for intra BankGroup accesses, but obviously it would ideally be set to 2 CLKs. Same goes for disabling GearDownMode, which seems to de-stabilize UCLK when it is operating close to the limit.

Increasing cLDO_VDDP seems beneficial > 3600MHz MEMCLKs, as increasing it seems to improve the margins and hence help with potential training issues. On previous gen. products it was only useful for shifting the MEMCLK holes, which were
present on certain CPU, motherboard and DIMM combinations. But then again, we never did this kind of MEMCLKs on those parts.

Spoiler

And before you ask. No.
Matisse version of RTC will never be public, sorry

Impressive numbers, sitting here at 72ns+ with 3600 micron e-die Contemplating if I should at this point just fork out the extra for some b-bie...

 

[The Stilt]

Impressive numbers, sitting here at 72ns+ with 3600 micron e-die Contemplating if I should at this point just fork out the extra for some b-bie...

What kind of timings are they running at?
Surely you can improve the latency by tightening up tRFC and tRC for starters?

 

[upgraditus]

What kind of timings are they running at?
Surely you can improve the latency by tightening up tRFC and tRC for starters?

If I knew what I was doing then perhaps, I've been relying on info from others since the calc is of little use for this setup.

 

[Nighthog]

@The Stilt

Currently running Prime95 test to see stability of 1:1:1 2DPC-SR @ 3800Mhz with Micron E-die. with all stock voltages.
Looks Ok so far, only minor glitch was some mouse stutter/lag for a moment, but it went away when I put a load on the cpu. Will have too see if it comes back or whatnot.

I've found some buggy BIOS features that depending on which place you set the setting at you either get max 1800fclk/UCLK working(3600Mhz), but set it elsewhere in the BIOS enabled 1900fclk/uclk without issue(3800Mhz).
AMD CBS vs AMD OVERCLOCKING the later working better

I'm on a Gigabyte board.

 

[The Stilt]

@The Stilt

Currently running Prime95 test to see stability of 1:1:1 2DPC-SR @ 3800Mhz with Micron E-die. with all stock voltages.
Looks Ok so far, only minor glitch was some mouse stutter/lag for a moment, but it went away when I put a load on the cpu. Will have too see if it comes back or whatnot.

I've found some buggy BIOS features that depending on which place you set the setting at you either get max 1800fclk/UCLK working(3600Mhz), but set it elsewhere in the BIOS enabled 1900fclk/uclk without issue(3800Mhz).
AMD CBS vs AMD OVERCLOCKING the later working better

I'm on a Gigabyte board.

1900MHz FCLK/UCLK is really good.

Single CCD CPU should help somewhat too, thou.

 

[The Stilt]

If I knew what I was doing then perhaps, I've been relying on info from others since the calc is of little use for this setup.

Can't they do lower tRFC?
tWR you should be able to lower, but I'm not sure if that makes any difference.

 

[upgraditus]

Can't they do lower tRFC?
tWR you should be able to lower, but I'm not sure if that makes any difference.

Thanks for taking the time to offer pointers, I really appreciate it since I'm well out of my depth with understanding of timings.

Have taken tRFC back to 504 (where it was for my 3466 preset) and tWR down to 24 and will re-test. Not sure how low I can go with them or if there are rules regarding correlation with other timings.

Edit: down to 69.4ns with the above.

 

[Nighthog]

I can inform and note that too high off a SoC voltage results in instability and problems when running high FCLK/UCLK. I saw many try 1.200 -> 1.250 vSOC for testing/benching but with this system of mine it's just an overall issue when trying to run higher FCLK/UCLK in 1:1:1 mode. I saw no gains whatsoever running it high.

3800Mhz Mem with 1900FCLK/UCLK can't boot with ~1.200vSoC. If it boots is soon freezes I've noted. Lower it to 1.150V I see large amount of errors in memory testing. Lower it some more toward 1.100V and it gains stability which is "stock" on this board of mine. I could even lower it down to 1.000V and still run 3800Mhz 1900FCLK/UCLK and have found Geardown Disabled 1T works like this after finding the right procODT & DrvStr values. It seems like the lower you go the better it is for stability.
I thought increasing voltage would allow higher speeds but it was the opposite effect.

I tried to increase speed but didn't get more out of it yet for 1:1:1 mode still stuck at MAX 3800Mhz MEM & FCLK 1900Mhz 1:1:1 mode. But found geardown disabled does work with 1T timings with these still XMP timings that are horrible.

 

[gupsterg]

For 2 CCD SKUs, 2 DPC SR configuration seems to be the way to go.
Both the 3600 and 3700X did 1800MHz UCLK on 1 DPC DR config, but most likely due to the discrepancy of the two CCDs in 3900X, it barely does 1733MHz on those DIMMs.
Meanwhile with 2 DPC SR config there is no issue in reaching 1866MHz FCLK/UCLK. That's pretty unfortunate since 8GB DIMMs cannot be considered as desireable or future proof as 16GB ones, due to the 32GB limitation.
Sure 16Gb ICs exist nowdays (hence allowing 16GB SR modules), but none of them can come even close to B-die in terms of frequency and timings.

Phy at AGESA defaults, except ProcODT of 40.0Ohm, which is an ASUS auto-rule for Optimem III.
tRDRDSCL & tWRWRSCL cannot be set < 4 CLK when the UCLK is operating at the limit, but that doesn't seem to affect the latency too much.
4 CLK already provides 100% efficiency for intra BankGroup accesses, but obviously it would ideally be set to 2 CLKs. Same goes for disabling GearDownMode, which seems to de-stabilize UCLK when it is operating close to the limit.

Increasing cLDO_VDDP seems beneficial > 3600MHz MEMCLKs, as increasing it seems to improve the margins and hence help with potential training issues. On previous gen. products it was only useful for shifting the MEMCLK holes, which were
present on certain CPU, motherboard and DIMM combinations. But then again, we never did this kind of MEMCLKs on those parts.

Spoiler

And before you ask. No.
Matisse version of RTC will never be public, sorry

I'm surprised it even booted 1T with 2x16GB. I can run 3733 C16 2T any day but 1T, nope.

@Martin778

I think 4x8GB is in use as RTC shows 2DPC-SR.

@The Stilt

Thanks Roger and +rep :thumb: .

I can use your 3466MHz timings all the way upto 3600MHz 1:1:1, with very little bump on SOC/VDDG/VDIMM over stock, see this post which has Kahru RAM test with ~17000% and rerun.

At 3666MHz upto ~3000% is best I can get if stick to those timings. Increases in voltages, playing with ProcODT/RTT/CAD/PMU did not solve this.

So I too looked at what timings I need to loosen.

Benched SCL 4, it only seemed to lose me extreme low/high result on "Read" vs SCL 2, you can see below last row is 3666MHz with SCL 2 I have a result of 54846, where as same with SCL 4 never hit it, but also those 3 runs seem more consistent, as never got the 54134 as seen on a SCL 2 run.

Spoiler

This was where I got yesterday afternoon, hoping today can further improve timings.

PBO+150MHz (6x, 105W constraints) 3800MHz 1:1:1 data as WMV.

 

[chakku]

For 2 CCD SKUs, 2 DPC SR configuration seems to be the way to go.
Both the 3600 and 3700X did 1800MHz UCLK on 1 DPC DR config, but most likely due to the discrepancy of the two CCDs in 3900X, it barely does 1733MHz on those DIMMs.
Meanwhile with 2 DPC SR config there is no issue in reaching 1866MHz FCLK/UCLK. That's pretty unfortunate since 8GB DIMMs cannot be considered as desireable or future proof as 16GB ones, due to the 32GB limitation.
Sure 16Gb ICs exist nowdays (hence allowing 16GB SR modules), but none of them can come even close to B-die in terms of frequency and timings.

Phy at AGESA defaults, except ProcODT of 40.0Ohm, which is an ASUS auto-rule for Optimem III.
tRDRDSCL & tWRWRSCL cannot be set < 4 CLK when the UCLK is operating at the limit, but that doesn't seem to affect the latency too much.
4 CLK already provides 100% efficiency for intra BankGroup accesses, but obviously it would ideally be set to 2 CLKs. Same goes for disabling GearDownMode, which seems to de-stabilize UCLK when it is operating close to the limit.

Increasing cLDO_VDDP seems beneficial > 3600MHz MEMCLKs, as increasing it seems to improve the margins and hence help with potential training issues. On previous gen. products it was only useful for shifting the MEMCLK holes, which were
present on certain CPU, motherboard and DIMM combinations. But then again, we never did this kind of MEMCLKs on those parts.

And before you ask. No.
Matisse version of RTC will never be public, sorry

Any chance we may see some more presets find their way into ROG BIOS?

Also I've been hearing about ideal ProcODT for the new gen being between 30-40 now, Auto setting for me sets it to 60ohm which I have success with, would you anticipate any benefit to manually lowering it?

Interestingly enough it seems like a lot of the Auto settings coincidence with the DRAM Calc suggestions for previous gens, wonder if that had any influence on new defaults. Any ideas on what I should be able to tighten with 1DPC DR on a 1 CCD chip? I get errors dropping the tRCDRD to 16 and tRAS/tRC to 32/48.

Spoiler

As for MTC we have Ryzen Master now to display timings otherwise we'd all be begging!

 

[gupsterg]

@The Stilt

Forgot to ask, I see in RTC cLDO_VDDM don't see this on C7H, will this be exposed on AGESA 1.0.0.3 or later on C7H? what is this voltage? cheers .

Also I've been hearing about ideal ProcODT for the new gen being between 30-40 now, Auto setting for me sets it to 60ohm which I have success with, would you anticipate any benefit to manually lowering it?

1DPC-SR on UEFI 2406/2501 is 60ohms for me. 1DPC-SR on UEFI 0068 is 40ohms for me. Regardless of which UEFI I use out of the 3, 3600MHz needs ProcODT 40 or fails for me.

3666MHz showed signs of lower ProODT aiding it, dunno if red herring yet. Below is all same setup, only ProODT changed in stages from 40 to 30.

Spoiler

Above tests were with SOC: 1.043 VDDG: 0.968 VDIMM: 1.37 VTTDDR: 0.675.

I bumped VDIMM: 1.375 VTTDDR: 0.687 on ProODT: 30, got 585%

Spoiler

Then bumped SOC: 1.05 VDDG: 0.975 VDIMM: 1.38 VTTDDR: 0.675 on ProcODT: 30, got 728%.

Spoiler

My jaw was dropping, never got to OS, let alone to run RT on 2xxx with low end ProcODT.

 

[chakku]

@The Stilt

1DPC-SR on UEFI 2406/2501 is 60ohms for me. 1DPC-SR on UEFI 0068 is 40ohms for me. Regardless of which UEFI I use out of the 3, 3600MHz needs ProcODT 40 or fails for me.

3666MHz showed signs of lower ProODT aiding it, dunno if red herring yet. Below is all same setup, only ProODT changed in stages from 40 to 30.

My jaw was dropping, never got to OS, let alone to run RT on 2xxx with low end ProcODT.

Interesting finds indeed. Does 0068 default to 30ohm or is it still 60 and your existing memory timings/settings wouldn't boot anymore?

 

[gupsterg]

Interesting finds indeed. Does 0068 default to 30ohm or is it still 60 and your existing memory timings/settings wouldn't boot anymore?

1DPC-SR on UEFI 2406/2501 is 60ohms for me. 1DPC-SR on UEFI 0068 is 40ohms for me. Regardless of which UEFI I use out of the 3, 3600MHz needs ProcODT 40 or fails for me.

Regardless of UEFI used and if ProODT is defaulting to 60 or 40, I do not get POST failure at 3600MHz, I encounter stability issue in Kahru RAM Test with incorrect ProcODT. All other settings for context are the same, only once ProcODT is 40 or defaulting to 40, Kahru RAM Test will pass high % for 3600MHz C15 1T GDMD.

 

[Nighthog]

Bios set 53.3Ohm for my E-die 4x8Gb configuration and it worked all the way to 3933Mhz XMP profile perfect on my Gigabyte Aorus board.
But it's not the best value. 48Ohm is better after some time of comparison and lower might be even better. This kit loved 43.6Ohm on gen 1 B350 board and liked it even on the X470 board with gen 1 I had but that board had issues booting below 53.3Ohm so it wasn't ideal.

30-32Ohm aren't that good as I found they were worse than 48Ohm... But still there are values to be tested in-between them.

With gen 1 I found the lower procODT the better for memory stability as far as your CPU/motherboard combo could handle it the higher you tried for frequency.

 

[The Stilt]

Any chance we may see some more presets find their way into ROG BIOS?

Unless something very special emerges, then most likely not.
Frankly I see no need for them, as the timings themselves make very little difference (compare to previous gen).
The performance is defined by FCLK and UCLK and the maximum frequency those will depend on several different things (CPU specimen, CPU topology i.e. 1 or 2 CCD, motherboard and the DIMMs, in terms of the configuration and most likely PCB type too).

@The Stilt

Forgot to ask, I see in RTC cLDO_VDDM don't see this on C7H, will this be exposed on AGESA 1.0.0.3 or later on C7H? what is this voltage? cheers .

cLDO_VDDM is not adjustable on any platform, at least for the time being, and I just added it to see if AMD uses any auto-rules for it.

 

[gupsterg]

@The Stilt

Forgot to ask, I see in RTC cLDO_VDDM don't see this on C7H, will this be exposed on AGESA 1.0.0.3 or later on C7H? what is this voltage? cheers .

Unless something very special emerges, then most likely not.
Frankly I see no need for them, as the timings themselves make very little difference (compare to previous gen).
The performance is defined by FCLK and UCLK and the maximum frequency those will depend on several different things (CPU specimen, CPU topology i.e. 1 or 2 CCD, motherboard and the DIMMs, in terms of the configuration and most likely PCB type too).

cLDO_VDDM is not adjustable on any platform, at least for the time being, and I just added it to see if AMD uses any auto-rules for it.

I found for voltage "spend" and next to nothing performance gain, when using say 3600C14/3666C14 I was better off at 3600C15, need 1.425V/1.455 vs say 1.355V.

So far in testing nothing beats for performance/ease of gain "ability", PBO+150MHz 3600MHz using your 3466MHz timings, 1T GDMD. Simple set up of PBO, one step each on SOC/VDDG/VDIMM from default and nice gains in AIDA64, CB R15/R20, etc.

Thanks for the info as always .

When I target say 1933MHz FCLK board will not POST, not even with lowered RAM, have I hit CPU limitation, FW or god knows ?

 

[kazablanka]

I found for voltage "spend" and next to nothing performance gain, when using say 3600C14/3666C14 I was better off at 3600C15, need 1.425V/1.455 vs say 1.355V.

So far in testing nothing beats for performance/ease of gain "ability", PBO+150MHz 3600MHz using your 3466MHz timings, 1T GDMD. Simple set up of PBO, one step each on SOC/VDDG/VDIMM from default and nice gains in AIDA64, CB R15/R20, etc.

Thanks for the info as always .

When I target say 1933MHz FCLK board will not POST, not even with lowered RAM, have I hit CPU limitation, FW or god knows ?

Do you see any differences with +150 settings? I am on msi x570 ace and this settings does not do anything.
I use scalar x7 only.

My mobo sets the procOdt at 36,3 Ohms by default for 3600mhz.

 

[gupsterg]

Do you see any differences with +150 settings? I am on msi x570 ace and this settings does not do anything.
I use scalar x7 only.

My mobo sets the procOdt at 36,3 Ohms by default for 3600mhz.

All the R5 3600/R7 2700X data in CB is from C7H, the other Ryzen CPUs are from C6H.

PBO+200MHz 1669
PBO+150MHz 1665/1663
PBO+75MHz 1646
Stock is 1632

All R5 3600 results using RAM 3600MHz, 1:1:1, The Stilt's 3466MHz timings, 1T GDMD.

Spoiler

Upto PBO+100MHz I use 1x, PBO+150MHz just will not sustain MHz in Kahru RAM Test and bench in CB R15 with scaling if I do not use at least 4x, so I set 6x for over head in my mind, PBO+200MHz 10x was used, not tested it much. This post has some data as well.

 

[crakej]

Although I can run nice and tight at 3733 CL14 IF @ 1866 I get quite nice results....

If I try to run 3800/1900 only way it boots so far is to let bios apply awful auto timings like 22 26 26 26.

Also, I can select DOCP 4266, which is meant to be 19 19 19 19, it boots, but with same awful timings, not the XMP timings. Currently trying to get it to boot with 20 20 20 20, but no luck yet. Trying various voltages and timings but just don't know what I'm doing yet.

Tried CL15, GearDown off, tried T2 as well, but not sure how T2 effects things like voltage on this chip.

Do others have the bios enter slower timings than XMP for them?

Think I can probably refine my 3733 with help from the last few pages.

Thanks for extra information @The Stilt - always helpful!