It is defo UCLK in my case, even though I initially thought it was FCLK. Johan45 was the first to explain to me it is UCLK.Wanted to clear a common misconception people seem to have: The "Northbridge Frequency" displayed by CPU-Z is NOT the FCLK (fabric) frequency. Instead it is the frequency of the memory controller itself (UCLK). Normally both FCLK and UCLK operate at the same speed (MEMCLK). When FCLK and MEMCLK are desynchronised, UCLK will be set to 1/2 mode. Regardless if you lower or raise it below / above the MEMCLK. For example, if MEMCLK = 3200MHz and FCLK is anything else than 1600MHz, the UCLK frequency will be MEMCLK / 2 (i.e. 800MHz).
No third party software (for the time being) can monitor FCLK frequency.
Hi @The Stilt , not really what I found. First boot with a Ryzen 5 3600 in my C7H with Gskill flare x set to docp 3200 cl 14 the nb spped in cpuz read 1000, when I restarted znd set the fclk speed to 1600 it showed 1600 as nb speed in cpuz. Same as when set to 3600 mem speed and 1800 fclk speed.
For example VPII set say 3666MHz, which is 1833MHz RAM, FCLK will be 1833MHz if manually set, but as the UCLK will go MEMCLK/2 you should see ~917MHz. See the screenie in this post, I target 3533MHz (ie 1767MHz), 883MHz would be UCLK when MEMCLK/2=UCLK.
Thanks again :thumb: , fully appreciated :thumb: .
Nice , I cancelled my R7 3700X pre-order this morning, the R5 3600 is good enough fun for me .@gupsterg
Forgot I had my X370 C6H, updated BIOS to 7106 (AGESA 1002) AUTO OC + 200 MHz. Have not done any too much timings tightening and probably won't have time for the mean time (have to return chip). But anyways, was fun to meddle with. 3600 does seem to have more headroom.
P.S. Forgot C6H has the worst positioning for multimeter read points lulz
Be aware under load the Probeit points on C6H are affected by load line to planes (C7H isn't), there was a post by Elmor in the C6H thread and also should be in the OP of Ryzen Essential thread in my signature. You are better off setting a faster polling rate in HWINFO (~500ms or lower), then referencing the average SVI2 VCORE/SOC.
Yesterday to me felt wasted for me, I didn't get what I thought I'd get done. Any how this morning I am back testing what I'd like to be .
Without CPU OC this is how my CPU sits with MEMCLK/FCLK/UCLK 1:1:1:-
3533S SOC: 1.025V CLDO_VDDG: 0.985V VDIMM: 1.35V
3600S SOC: 1.025V CLDO_VDDG: 0.985V VDIMM: 1.355V
3666S SOC: 1.043V CLDO_VDDG: 1.003V VDIMM: 1.385V ProcODT: 48
Highest RAM profile is repeat pass in Kahru RAM Test of ~3000%, yet to run other tests. When combining it with PBO+150MHz it seems I need higher SOC & CLDO_VDDG.
3666S with PBO+150MHz PPT: 142W TDC: 95A EDC: 140A Scalar: 6x:-
SOC: 1.043V CLDO_VDDG: 1.003V fails ~400% tested twice in RAM Test
SOC: 1.050V CLDO_VDDG: 1.010V fails ~800% tested twice in RAM Test
SOC: 1.056V CLDO_VDDG: 1.016V fails ~1890% tested once in RAM Test
Upto PBO+100MHz I do not need to adjust scalar to have nice ACB of upto 4.3GHz in RAM Test. Over +100MHz I need to adjust this to have improved sustainable all cores frequency. +125MHz IIRC needs at least 4x, +150MHz seems right with 6x, not tried 7x yet. Below video will show clocks, etc.