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[THG] CPU Power Saving Slows SSDs

11928 Views 7 Replies 7 Participants Last post by  rapion125

Conclusion: Power Saving Can Reduce SSD Performance

However, our findings are significant, as they can affect users who may not even know they are running an SSD with the brakes on. In short: really fast SSDs that can deliver 200 MB/s or even more of throughput become limited by CPU performance due to power saving mechanismsâ€"or more precisely, they are bottlenecked by a limited availability of CPU time. This became obvious by switching the various power saving options on and off. We found that the sophisticated power saving mechanismsâ€"such as the Active State Power Management for PCI Express, or the deeper C states that switch off entire functional units within the CPU at a transistor levelâ€"have a noticeable impact on the performance of our X25-E flash SSD. Obviously, the latency added by utilizing the more complex power saving features is significant enough to have to wait for the system to pick up data.

The conventional power saving techniques, such as Enhanced SpeedStepâ€"which reduces clock speed and voltage during idle or low load periodsâ€"showed the least impact. This is also the case for C1E mode (enhanced halt). Thus, we recommend keeping both of these enabled, as they contribute to lowering CPU temperature while reducing power consumption. All of the sophisticated power saving mechanisms are questionable for fast, SSD-powered systems. We believe that it does not make sense to go for a hardcore flash SSD product, just to lose performance on the way due to sophisticated power saving features. Check your BIOS options should your SSD performance not be at the level you expect it.
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interresting ...
Interesting stuff.

I'll have to bench mine to see if it makes a difference for me
I am no coding genius, but shouldn't this not be happening? Unless the power saving features are some how effecting the south bridge and memory controller, the firmware and device controllers for the drives should (or are supposed to be) sophisticated enough to perform most I/O functions with limited need for CPU overhead, right? Or is this something more complicated then standard interrupts?
Yeah... shouldn't the transfers be happening via DMA? I guess it depends on the size of the transfers then. If it's a lot of small transfers, then I suppose this could make sense.
Seems this is probably more fault of the memory controller then the CPU or chipset. I imagine this would be much worse with RAID in stripes.
I never use power saving features. I would rather get the full performance I payed for.
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