Because the memory controller is in the CPU core instead of the northbridge on Athlon 64s, bus speeds are determined in an almost completely different manner than most people are used to. Hyper-Transport essentialy replaces the external FSB in Athlon 64s, it's the 800MHz 16bit x 16bit bidrectional link between the processor and the system (chipset). It's base frequency is 200MHz as determined by the PLL (frequency generator) and inside the chipset is goes by a multiplier, x4 on socket 754, and x5 on Socket 939. The CPU clock speed is then determined by another multiplier by the original HTT/FSB base frequency of 200, so for a 3000 you have 200MHz HTT x 10 CPU multiplier = 2000MHz CPU clock speed. Now, the memory bus is not determined by the HTT base frequency, or at least not directly. Since the memory controller is on the CPU die, the memory bus is determined by an internal DIVIDER of the CPU frequency, which while running "1:1" would be the same as the CPU multiplier giving you 200MHz real, or 400Mhz effective, hence the need for PC3200/DDR400 RAM. So instead of running in a ratio with the FSB, the RAM is actually running at just a lower speed of the CPU clock. Technical speaking when overclocking the Athlon64s, you aren't changing the FSB, you're changing the HTT base frequency, which is why it's actually correct to say 200HTTx10 instead of 200FSBx10. Athlon 64s still have a Fronst Side bus (that being the link of the memory controller to the on die cache) but it is also directly integrated into the core and runs at the core CPU frequency and is 128 bits wide.
