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Better signal integrity for higher clock speeds thanks to new features at chip level, such as Off-Chip Driver calibration (OCD) and On-Die Termination (ODT) Larger 4-bit
prefetch, additive latency, and enhanced registers.

EDIT and rep me if i was helpful
 

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DDR2 is the next step to higher performance DDR technology. DDR2 can boost designs with greater clock frequency and available bandwidth without increasing power consumption.

EDIT:
  • VDD = 1.8V, VDDQ = 1.8V
  • I/O = SSTL_18
  • 400 Mb/s/pin and 533 Mb/s/pin data rates
  • 3,200 MB/s and 4,300 MB/s for 64-bit systems
  • 4n data prefetch
  • 4 banks for 256Mb and 512Mb densities
  • 8 banks for 1Gb and 2Gb densities
  • Burst length of 4 or 8
  • WRITE latency = READ latency - 1 clock
  • Differential data strobe option
  • Duplicate RDQS data strobe option
  • READ latency: 3, 4, and 5
  • Posted CAS# additive latency: 0, 1, 2, 3, and 4 clocks
  • On-die termination (ODT)
  • Off-chip driver (OCD) output impedance calibration option
  • Pb-free FBGA packaging
 

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heh read what i just edited up there
thanks first rep i got

EDIT: hehe forgot one more thing:
Posted CAS and Additive Latency
These two, prevent data collisions within the memory while still able to transfer more read/write instructions per clock cycle.

Off Chip Driver Calibration
Increases signal integrity
 
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