Hi yet again, guys! I would like to share my knowledge with all of you regarding how SPD DDR3 must be correctly interpreted by software. There are two base JEDEC documents on DDR3 SDRAM standard:
JEDEC JESD79-3 and
JEDEC Annex K: Serial Presence Detect for DDR3 SDRAM. The first one is very useful on checking for standard timings for different speed bins of DDR3 memory and the second one is for programming them into SPD. So, if you need to know standard timing delays and speed bins you can refer to the first document. Anyway, let's open chapter "12.3 Standard Speed Bins" at page 171 (I used revision F of the document) and copy out them all:
- DDR3-800D 5-5-5-15-20
- DDR3-800E 6-6-6-15-21
- DDR3-1066E 6-6-6-20-26
- DDR3-1066F 7-7-7-20-27
- DDR3-1066G 8-8-8-20-28
- DDR3-1333F 7-7-7-24-31
- DDR3-1333G 8-8-8-24-32
- DDR3-1333H 9-9-9-24-33
- DDR3-1333J 10-10-10-24-34
- DDR3-1600G 8-8-8-28-36
- DDR3-1600H 9-9-9-28-37
- DDR3-1600J 10-10-10-28-38
- DDR3-1600K 11-11-11-28-39
- DDR3-1866J 10-10-10-32-42
- DDR3-1866K 11-11-11-32-43
- DDR3-1866L 12-12-12-32-44
- DDR3-1866M 13-13-13-32-45
- DDR3-2133K 11-11-11-36-47
- DDR3-2133L 12-12-12-36-48
- DDR3-2133M 13-13-13-36-49
- DDR3-2133N 14-14-14-36-50
Now let's run our favorite CPU-Z and check for information being displayed on the SPD tab (I used my Kingston DDR3-1333H module):
- 457 6-6-6-17-23
- 533 7-7-7-20-27
- 609 8-8-8-22-30
- 666 9-9-9-24-33
As you can see, the only correct timing set is "JEDEC #4" which is default for DDR3-1333H speed bin. In other words, according to JEDEC JESD79-3 standard CPU-Z should displays as follows:
- 400 6-6-6-15-20
- 533 7-7-7-20-27
- 533 8-7-7-20-27
- 666 9-9-9-24-33
JEDEC have never defined some kind of wired frequencies like 609 MHz, 457 MHz, etc for DDR3 memory. CPU-Z is buggy in accuracy both for DDR3 and DDR4 standards and it needs to be fixed definitely!
