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Here is mine but to get no errors running Blender or Cinibench I need 1.3125v at 46.5 46. I tried 1.35v at 47/46.5 and Blender would stop responding and sometimes Cinebench would error out. :(

2513900
 
About DPM , LCLK and similar
Let me drop you this little tool
Bios Modding - Google Drive Tool1007.zip (tool.exe)

Have fun with it :)
Single CCD can run
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To override allcore EDC throttle
You still should set Bios PBO EDC limit higher soo cache can boost up
But this overrides another stage of allcore throttling
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This is interesting for you , just the plotting is a bit strange to use
And this is what you surely will like to see
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Enjoy experimenting
Each of the 8 "Frequency Limiters" Sensors can be the cause of frequency loss
FIT PPT throttle usually appears because of something else, still searching for the value

DPM doesn't show up correctly and the ASRock ITX misses LCLK optionality to enable it. The Asus board had it
Some values are under a wrong multiplier but there are valuable things to check and read out
Effective Clock is correct for example
Also it shows fully how many CCDs and Cores you have ~ for all these mysterious samples out there
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Copyright belongs to the ASUS Forums as XOC tool
I forgot who published it and which team maintains it.
No credit belong to me, just want to make it easier accessible to people :)

Waiting for 1.2.0.3A for the ITX board, then i'm gonna check out what can be done for the public
113 Binning value is already good, 118 is fantastic - haven't seen 120+ so far
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DPM 2-1-1-2 doesn't show it
testing 2-2-1-1 too ~ but this is intercore stuff. SiSoftware Sandra is your best friend for such
This one is neat, but only ASUS boards let access to RAW VRM controller
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Apparently there should be an I²C port on the ITX , but i haven't checked
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MEM-OC thread, soo here are some valuable RTTs for Rev.E@1.6v or XMP under 56.50
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View attachment 2513725
I lack a lot of options on the ASRock bioses - but 1203A update needs to be out, before it has any modding potential or consideration
* on the Drive link above, AMI_FLASH Win can flash unsigned bioses ~ as long as the DeviceID remains identical. It bypasses AMDs SPI lock but is not able to cross-flash bioses
Backups of it are sector based and tiny ~ do no use it for backup purposes, unless you can stitch bioses together (HEX)
@Veii

What should I try for my 5950x?

2513903
 
Here's what I've got so far. Primaries of 14, 15, 15 15 do not like 1.53V. This all runs at 1.54. Temps stay below 40C without a cooler, but I am running a pretty efficient cooler now just for good measure.

I was manually setting vcore soc, and accidentally put it on auto. Turns out auto is wayyyy more stable, although it set the same damn voltage I was running before?? IDK

I reduced resistance as much as I could on procodt, but can't go lower than 53.3

These are both patriot 4400 kits (2x 2x8 kits) One pair of dimms was aquired second hand, and it shows a manufacture date of the year 2000. Huh? Other set says 2020 week 50. See attached thumbs... Also have the tiniest bit different timings. Some not reflected in these photos here, but visible in bios.

I decided on 3800 as anything higher seems to give me both higher and lower peak frames. (more inconsistent) I can get this stable at 4000 and 2000 fclk cl15, but like I said, performance is more spastic, though stable.

2513915

Font Display device Gadget Audio equipment Technology
Computer Font Gadget Audio equipment Technology
 
Been on this 5 months ago ~ now most can only run it since the WHEA suspender exists, but most of the community still is at that 2033 range. After 2067 the real struggle begins

It's hard to relink to soo many old posts , even more when a lot of the information where on twitter & i wiped them to free the @tag for something bigger
Complicated, i shouldn't be annoyed repeating ~ but it is repeating and repeating.
Never had WHEA #19 issues , got some once but only if i really have to be doing very stupid things

Although as comparison, working with a Dark Hero ~ it was nothing but WHEA#19 even on 1867 , with 1900 FCLK holes
It was painful, soo i can understand the annoyingness by some users
Gladly, i'm free from such ~ but then the Bios as exchange on ASRock is barebones and booring
The Asus ProArt made fun, but the reason i bought it for "Thunderbolt" is buggy on it's current state ~ while loosing the contact to my ASUS Rep
I shouldn't complain, after all was planing to retire
Thanks for clarifying.
I don't want to annoy you. I am just really frustrated. I got my board punched in fairly aggressive settings of another user, lowered voltages and had something nice and stable. Just the whea 19s drive me nuts. (I tryed to fix them with voltages for 10h+, there is just no real pattern. Only thing I noticed is that load doesn't matter - it's time / clockcycle based. Even in idle after a certain time a big pack drops. The time to that drop felt consistent.)
My chip runs 4000MT/s CL16-16-16-32 1:1:1 @ vsoc of 1,040v with only some usb dropouts, so I went to 1,070v and some more ccd_iod and everything is perfectly stable. I just did not want to do everything twice, so I thought I would wait for a fix. But there seems to be none. So I just punched in 3600 cl14. Still waiting for a fix from Gigabyte / AMD that is never coming.

So it seems to depend on the board? I swapped mine for the B550 Vision D, because it has the updated mem. topology. This should be easy. I bought top dimms and one of the boards with the best memory topology. I think I even got lucky on my chip.
 
In the case of b-dies with tCL 14 tRTP should either be 6, 7, or 8. Optimally it should be half or half minus 1 your tCL (ignore this if you have hynix chips). Mine is running ok at 7 and 3666/1833 but 6 needs more voltage I think, 7 is completely stable.

My current timings for comparison, in my case tRC 42 x tRTP 7 = tRFC 294, at 6 tRTP the refresh goes to 137ns at this speed and isn't totally stable. Setting command rate to 2t timing actually reduced my memory latency a hair so props to Veii for that recommendation.

2513922


Been using this tool for reference that Veii recommended.

 
In the case of b-dies with tCL 14 tRTP should either be 6, 7, or 8. Optimally it should be half or half minus 1 your tCL (ignore this if you have hynix chips). Mine is running ok at 7 and 3666/1833 but 6 needs more voltage I think, 7 is completely stable.

My current timings for comparison, in my case tRC 42 x tRTP 7 = tRFC 294, at 6 tRTP the refresh goes to 137ns at this speed and isn't totally stable. Setting command rate to 2t timing actually reduced my memory latency a hair so props to Veii for that recommendation.

View attachment 2513922

Been using this tool for reference that Veii recommended.

2513923


Are the 67 MT/s more worth going to 2t?

I assume you are running the patriot viper steels as well?
 
The V/F program doesn't read my CPU correct at all. It says best all core frequecy at 1037mv is 3300, I run 4400@1060 100% stable. Estimated voltage at 5000 is 1909mv, I gan run 4800@1.32V (stable but overheats in avx due to cooler.) My sil rating is 80. I run -30 CO at +50MHz, LLC medium, maybe some of this interferes?
 
In the case of b-dies with tCL 14 tRTP should either be 6, 7, or 8. Optimally it should be half or half minus 1 your tCL (ignore this if you have hynix chips). Mine is running ok at 7 and 3666/1833 but 6 needs more voltage I think, 7 is completely stable.

My current timings for comparison, in my case tRC 42 x tRTP 7 = tRFC 294, at 6 tRTP the refresh goes to 137ns at this speed and isn't totally stable. Setting command rate to 2t timing actually reduced my memory latency a hair so props to Veii for that recommendation.

View attachment 2513922

Been using this tool for reference that Veii recommended.

Your settings got me curious. This is what I came up with:

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:cautious: Had to bend over 3-4 times to reset cmos while I was eating ...

tRTP seems to be affected by gdm. I thought it was only tcl.

Make sure you test well, CL14 3667 always errored super late for me. Like over 1h into memtest.
 

Attachments

Your settings got me curious. This is what I came up with:

View attachment 2513926

:cautious: Had to bend over 3-4 times to reset cmos while I was eating ...

tRTP seems to be affected by gdm. I thought it was only tcl.

Make sure you test well, CL14 3667 always errored super late for me. Like over 1h into memtest.
Yeah I have the viper kit as well, I'm able to push it to 140ns refresh at 1800 mhz with trfc 252, trfc2 187 and trfc4 115 but I have the 16gb kit, your 32gb kit looks much nicer than mine but idk how low you can go with 32gb.

My poopy 32gb kit.

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It was Veii who recommended 2t timings because 1t with gdm enabled can ignore your timings that you set.
 
This opens quite some interesting doors :p

Now you got a 125... but my silicon quality is not that good, not sure how reliable is this metric eheh

View attachment 2513669

Also see my FIT VID is 1.5V and the Limit is a monstrous 52K:

View attachment 2513672
you guys are set, im HIT

(am i doing something wrong?)

your using this on a MSI board are you not?

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so i have the "worst" CPU here? tf are you guys doing that i missed somewhere lol...
 
Yeah I have the viper kit as well, I'm able to push it to 140ns refresh at 1800 mhz with trfc 252, trfc2 187 and trfc4 115 but I have the 16gb kit, your 32gb kit looks much nicer than mine but idk how low you can go with 32gb.

My poopy 32gb kit.

View attachment 2513928

It was Veii who recommended 2t timings because 1t with gdm enabled can ignore your timings that you set.
I am using 2 16gb kits ;). But I made sure to get a nice board.
I did not do soo much clocking yet wanted to wait for a whea 19 fix to do all of it on 4000. But I wanted to give you something to punch in.
 
hopefully we will get an agesa that is able to keep everything sync/trained with higher FCLK
Seems to have found the reason for stretching (or not stretching) clocks from boot to boot. Dont know how it exactly works, but after decreasing all CO values (abs) by 3-5, clocks normalized. Can't explain that phenomena atm, other than some static V/F curve formed at boot stage, taking current temps, power limits, etc into account, and used later by some DFS functionality. So when ambient temp rises, given that OC-ed DF cut a decent part off of a CPU total power budget, there's just lack of boosted P-states to met the "trained" conditions at high allcore load for the frequency the "dynamic" algorithm requested . Which condition exactly? I assume its the power, because temps are higher with lower abs. CO values (for obvious reasons), but the perfomance was not degraded at least, despite clocks shown are lower on average.
To put it simple - I see it as the "power clock stretching", similarly to "VID clock stretching" caused by low negative Vcore global offset

PS: Although, I realize that all of the above might turn out complete bulls**t, lol, it would be nice to hear any expert opinion about that ))
 
Win CPU silicon lottery
not so much in my case, since "if" i ran what these fellas were using a few pages back
right then well my cpu lottery is 80...lower than the default score it has...
and im WHEA free now. was getting WHEA 18 (never 19)
but still.... 18 was due to core and curve adjusting...
 
Here we go :)

  • 5950x @ 4700/4600 static OC, SMT enabled
  • 4x8GB memory sticks
  • Hwinfo open for all runs
  • consecutive runs
  • Flat CL 14-14-14-14 timings

View attachment 2513871
T1 setup-time
19723.4 H/S over 15min run
upto 627 H/S per core

View attachment 2513872
T1 GDM
19151 H/S over 15min run
upto 606 H/S per core

View attachment 2513873
T2
19413 H/S over 15min run
upto 616 H/S per core

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

19413 / 19151 = T2 is ~1.3% faster than T1 GDM in this benchmark
19723 / 19413 = T1 setup-time is ~1.6% faster than T2 in this benchmark
19723 / 19151 = T1 setup-time is ~2.9% faster than T1 GDM in this benchmark

No time to break down the numbers further, going out :)

But it seems like CPU mhz is king in pretty much every benchmark, dont waste to much of your power budget on SOC if your running PBO CO as the pure core clocks matters the most in the end...
Have also done some Aida numbers for my fastest T1 setup-time profile with my new CTR 24/7 settings (y)
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Impressive! 56 56 56 did the trick for 1T?
Yes

And when i change over to T1, i change nothing other than the following 3 things in bios:

tCKE 1 -> 9
commandrate T2 -> T1
setup-time 0 ->56 (all 3)

If i change more than these settings it wont boot.. Once its booted and settings are "saved" there is no hassels with restarts and/or cold/warm starts. But everytime i change something in the bios i have to go over this prosses again.

Low ProcODT is also needed for this to work.. So you need to finetune your voltages/settings to run this low ProcODT* with dualrank memory.. singlerank 16GB everyone can run T1 :)

* = i also needed a bios with ageisa 1.202 to manage these settings
 
Just learned this recently, tRC x tRTP = tRFC, do with this as you will but it seems to help.
Carefull with this. It will not work for everyone! Good example - my system: 3800MHz@CL16. I can run tRTP as low as... 5 (with tWR=10). :) And i have got tRC=48. So it mean that i may run tRFC=240? I tested before tRFC=264 and i can't complete TM5 even 3 cycles and got BSOD: Kernel Security Check. I think i can't even boot with tRFC=240.
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Estimated voltage at 5000 is 1909mv
My sil rating is 80
You need to press "Get Sil Quality" first only after that press "Get Volts". Without that data software will use default value in "Sil Quality" window.
 
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