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Well I would hold off doing futher testing until you can work out what going on with your RttPark, have you tried falling back to an earlier BIOS just to test RttPark ?
I've managed to get RttPark 3 posting and double-checked it on A1/B1 and A2/B2. But it required me to set the DDR4 speed to DDR4-2133.

I even default setting the whole BIOS and just tried running DOCP, which obviously posts, but then when manually selecting 6/3/3 it won't post again.

Not really sure what this tells me.... I'm going to save my updated profiles to a USB stick and now try rolling back to an older BIOS verison.

@Veii Not sure how helpful these pictures are but here is my memory for PCB
Image


Image


Image
 
@Veii Not sure how helpful these pictures are but here is my memory for PCB
Image
Last Picture is kind of usable
But rather make a birdview type of picture with more light (illuminating the traces ~ soo they reflect back light)
and from both sides of the dimm - because this is Dual Rank
You do not know which side is the primary and which is the back of it

It looks like typical A2, depends on the other side
EDIT:
Sadly this side is too blurry
Image

can not differentiate A2 from A1 or even A3

EDIT2:
Not every cam / lense can focus up close ~ soo a further one is fine too
But something like this - the traces reflect back the light
This here is an A0 ~ a custom but it's A0
2517740

2517741
If you can check the traces, you don't have to remove the heatsink
Just for dual rank, you have to check both sides ~ which of them is the primary one
 
Counting from left to right

Best pair dimm stick 1 = BP1
Best pair dimm stick 1 = BP2
Worse pair dimm bad stick = WPB
Worse pair dimm good stick = WPG

1 -------- 2 -------- 3 -------- 4
BP1 --- WPB --- BP2 --- WPG

Thats how I have them ordered, may help also...
@craxton my recommendation for putting best pair of sticks to worse slots was based on this post. @mongoled did I interpret you right? Are the slots on your diagram A1-A2-B1-B2?

Best way to determine is to test the sticks independantly, for me this is a must if you are running 4 sticks.
Do you only test frequency, primaries and VDIMM to determine stick order? Or do you go all the way and variate other voltages, resistances and other than primary timings? From what I gather at first you are testing 2 pairs separately, then test two sticks from worst pair separately. That is 4 times the usual memory OC process =/ I'm asking did you find any way to speed up the process? I'd appreciate a thorough guide 🤓
BTW since you test 4 times anyway, why won't you test just each individual stick?
 
@XPEHOPE3

Below is meant to signify only a change to tCL, but obviously other values have to be changed otherwise no post.

So tCWL, tRDWR & tWRRD were set to AUTO values,

everything else is identical

tCL is 15 in the first screenshot and 14 in the second screenshot
tCWL is 14 in the first screenshot and 12 in the second screenshot (has to change to the next optimum tCWL value)
tRDWR is 9 in the first screenshot and 10 in the second screenshot (has to change to the next optimum tRDWR value)
tWRRD is 4 in the first screenshot and 1 in the second screenshot (has to change to the next optimum tWRRD value)

Photograph Computer Light Product Screenshot
Photograph Product Azure Computer Font


From the above,

AIDA64 L1 latency improves when using tCL @15 instead of @14
DRAM Memtest improves when using tCL @15 instead of @14
Sisoft Sandra seems to within margin of error, though there is a distinct change in U0-C0T0 <> U2-C1T0 Data Latency

So why the improvement ? It looking that tPHYRDL is directly effecting the result, only way to really confirm it is to be able to force it to train at 26 when using tCL set to 14 but I have not found a way to achieve that!
 
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Reactions: XPEHOPE3
Last Picture is kind of usable
But rather make a birdview type of picture with more light (illuminating the traces ~ soo they reflect back light)
and from both sides of the dimm - because this is Dual Rank
You do not know which side is the primary and which is the back of it

It looks like typical A2, depends on the other side
EDIT:
Sadly this side is too blurry
Image

can not differentiate A2 from A1 or even A3

EDIT2:
Not every cam / lense can focus up close ~ soo a further one is fine too
But something like this - the traces reflect back the light
This here is an A0 ~ a custom but it's A0
If you can check the traces, you don't have to remove the heatsink
Just for dual rank, you have to check both sides ~ which of them is the primary one
Tried to get some better lighting, any of these easier to work with?
Image


Image


Image


Image

When you say traces do you mean the small bits of metal?

I'll get some better pictures, I took the above before seeing your example.
 
@craxton my recommendation for putting best pair of sticks to worse slots was based on this post. @mongoled did I interpret you right? Are the slots on your diagram A1-A2-B1-B2?

Do you only test frequency, primaries and VDIMM to determine stick order? Or do you go all the way and variate other voltages, resistances and other than primary timings? From what I gather at first you are testing 2 pairs separately, then test two sticks from worst pair separately. That is 4 times the usual memory OC process =/ I'm asking did you find any way to speed up the process? I'd appreciate a thorough guide 🤓
BTW since you test 4 times anyway, why won't you test just each individual stick?
E7C35v2.1.pdf (msi.com) page 5, and yes, order is correct as per my diagram

A1 ----- A2 ------- B1 ----- B2
BP1 --- WPB --- BP2 --- WPG

Best pair dimm stick 1 = BP1
Best pair dimm stick 2 = BP2
Worse pair dimm bad stick = WPB
Worse pair dimm good stick = WPG

I also did it the long way, brief explanation, as I did not buy my 2 pairs of sticks at the same time I found settings that were stable for the 1 pair, these were 14-14-14-14-1T.

When I got the second pair I simply chucked them in and tried to run at the same settings which failed.

From these I started testing the new pair in the same manner I tested the first pair.

Through this testing I found out that the new pair were not as good as the second pair, so I tested each dimm separately.

Testing was real quick using TM5, just set tRCDRD to 14 and see what would happen, after an hour a so of playing I found that tRCDRD @14 was not possible, whatever I changed with regards to powering the dimm, voltages, resistences etc, all I could achieve was shifting where the errors would appear.

Once I set tRCDRD to 15 TM5 would pass at a breeze without having to play with other settings.

I simply used my 24/7 settings for the good pair, dropped tRCDRD to 15, then did any fine tuning that was needed

:)
 
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@mongoled
So... you've got your good kit in A2/B2 originally, got bad kit, put it to A1/B1, found that tRCDRD 14 isn't stable anymore, switched sticks according to your method and again found that tRCDRD 14 isn't stable. Meaning switching sticks might not have provided any benefit compared to running relaxed settings with original stick order of bad-good-bad-good. Am I missing something?

Also I thought it's strange that tCL=tCWL+2 runs easier than tCL=tCWL, as "how can running tighter timing can be easier?". But you seem to agree with Nighthog on this.
 
Hello guys again :)
still struggling with FCLK 2000/MCLK 200
What I did found, can't go lower on ProcODT than 36.9 otherwise PC will not boot.
min. VSOC voltage must be set to 1.08750 V otherwise WHEA error
ClkDrvStr changed from 40 to 24
CLDO VDDP changed from 0.9500V to 0.900V - made no difference
VDDG CCD changed from 1.050V to 0.960V (just found this needs to be higher than 0.960V, otherwise WHEA error again).
As you can see error is still number 6, but sporadically I can also spot error number 0.
Any tips would be greatly welcome.

2517753
 
As you can see error is still number 6, but sporadically I can also spot error number 0.
From Veii's error descriptions and from your timings one can suspect wrong tRDWR and tWRRD. tRDWR should be at least 10 for you, but most probably 11. tWRRD might be good according to Veii's rules, but for 4 dimms it might also need a bump to 4 or 5.
Try setting on Auto both settings and see what the board would recommend.
 
Hello guys i need advice for sub timings

I have a Crucial Ballistix RGB CL16 kit BL8G36C16U4BL,M8FE1

Micron Rev.E C9BLM A2 LAYER

2517757


I have those timigs and my system is %100 stable for an hour i also tested before 2 hours of memtes5 1usmus config it was stable as well.

cant lower tRFC
also tRC
trdds
trddl
tfaw also good
maybe i can try to change tWR

Now which timings shoud i change.

I tried to change tRP 12 tRAS 21 it wasnt stable i got errors instant.

Maybe i can change tCWL to 13 or 12

I also have 4x8 sticks(ALL SR) I cant do stable 3800 because of 4x8 stick config i also have bad motherboard which is Asus prime B550m-k

And Advices?

Thanks.
 

Attachments

From Veii's error descriptions and from your timings one can suspect wrong tRDWR and tWRRD. tRDWR should be at least 10 for you, but most probably 11. tWRRD might be good according to Veii's rules, but for 4 dimms it might also need a bump to 4 or 5.
Try setting on Auto both settings and see what the board would recommend.
Thanks for the tip :)
Auto settings set it to 9 and 3, I tried to set it manually to 11 and 5 (tRDWR/tWRRD) but sadly no difference. Still error 6.
 
enable GDM.
People with GDM enabled rarely if ever get help here. Most of the knowledge here (incl. the error descriptions above) gets accumulated on GDM off setups.

@deadfelllow
5 cycles of 1usmus_v3 config are not enough to ascertain stability. 25 is recommended, no less than 20.
How did you know you can't lower tRFC? Wasn't it posting or was it not stable?
Also did you try using SD/DD timings 1-5-5-1-7-7 or 1-5-4-1-7-6? Those when higher actually might enhance performance. But can easily prevent posting or stability.

Also you get tPHYRDL 28 from training and who knows how much it is on your B memory channel (check in ZenTimings please). You might be better off relaxing some of the timings (for example, tCL to 15 just like @mongoled did some posts above, or tRRD_/tFAW back to like 6/8/24) to make tPHYRDL get trained to 26/26 setup (for A/B memory channels). That should improve Aida latency if you are after that.

Also I thought to point you to this list, but you've already beaten every 4*8 Micron there(y) Or rather would beat when you pass longer TM5 stability test and maybe y-cruncher test
 
@mongoled
So... you've got your good kit in A2/B2 originally, got bad kit, put it to A1/B1, found that tRCDRD 14 isn't stable anymore, switched sticks according to your method and again found that tRCDRD 14 isn't stable. Meaning switching sticks might not have provided any benefit compared to running relaxed settings with original stick order of bad-good-bad-good. Am I missing something?

Also I thought it's strange that tCL=tCWL+2 runs easier than tCL=tCWL, as "how can running tighter timing can be easier?". But you seem to agree with Nighthog on this.
Will get back to you on this later ..

:)
 
@XPEHOPE3 Ok, surprised that I got some help here then :D because I have various issues with GDM disabled above 3600Mhz.
Suppose I will stay at 1967 FCLK then and 56.5ns being reported in AIDA64.
Getting FCLK/MCLK 2000Mhz stable seems to be real pain in the ass.
 
2517767


VDDG CCD too low? PBO off, CPU is at stock

or maybe win corrupted already due to my tinkering....
2517768
 
Well I would hold off doing futher testing until you can work out what going on with your RttPark, have you tried falling back to an earlier BIOS just to test RttPark ?
So I've spent some time doing some testing mate.

First thing I did was roll back to an earlier BIOS with AM4 AGESA V2 PI 1.2.0.1 Patch A. After this all I did was load BIOS optimized defaults, put RAM on 1.4v and 3800 and rebooted. Obviously posted fine. I then tried RttPark 3, no post.

So I put it down to 3200, which is what RAM is rated for, posted fine. Slowly kept pushing it up and it kept posting till 3400.

Upgraded back to AMD AM4 AGESA V2 PI 1.2.0.3 Patch A (latest BIOS) and did the same thing, and it worked up to 3400 as well. Weird thing is when I was trying to get it to post on this BIOS earlier I was having issues o_O

So, not sure what to think. I don't think it's AGESA, it must either be my mobo, memory or a combination of the two. Obviously the above testing was with everything on BIOS auto other than VDIMM and the memory frequency. Loaded my safe CL16 GDM Off profile (at 3400 instead of 3800) and here it is booting with 6/3/3

Image


Does anyone know if RttPark hits a higher frequency "block" is it just the RAM quality or something? For now it seems if I go above 3400 I need to be on RttPark 1.

Moving on from this I've driven myself almost insane trying to get flat 15 passing a stability test. Maybe my memory just isn't good enough.

Image


That was the closest I have got and I've driven myself mad making small changes to the right hand side, and loosening some timings, but no go.

I've got CL16 profiles with GDM on that are stable, so for now I guess I'll just focus on improving the timings on my GDM disabled CL16 profile.

Thanks for all the help to the regular posters in here, I've learned a bit and while I might be out of my depth for flat 15, or my memory genuinely not good enough, never say never. I might be back at 15 at some point :p
 
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