5800X3D Owners

Sptz · Oct 26, 2023

eighty20 said:
Man, 1T off is a pain, no matter what combination I tried, I couldn't pass 1usmus without Setup. Still have whea 19 during absolut config but i guess a bit more vsoc and vdimm would fix it. And mismatch phyrdl again
View attachment 2633031

Aren't those voltages awfully low for what you're demanding of your ram and vrm?

This is what I have on 3733 + GDM Enabled - 100% fully stable for months

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I may be wrong but you'd be hard pressed to get away with those timings and clock at such low voltages

eighty20 · Oct 26, 2023

Sptz said:
Aren't those voltages awfully low for what you're demanding of your ram and vrm?

This is what I have on 3733 + GDM Enabled - 100% fully stable for months

View attachment 2633048

I may be wrong but you'd be hard pressed to get away with those timings and clock at such low voltages

Idk other way to test besides tm5 then some yruncher.

This 2t gdm off seems ok after using for awhile. None of this is stress for days so probably not really stable but I haven't any weird happen in game.

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Anyway, I'm gonna try your setting see if works on mine.

PJVol · Oct 26, 2023

Blameless said:
I did start to see clock diverge from the reported global limit around 110A EDC, but the L3 clock behavior still mirrors the core clock behavior, which doesn't imply much with regard to which one is the cause and which one the effect. Why would lowering EDC cause the L3 to become the limit? The anomaly of the actual limit being below the reported global limit doesn't prove anything either way...for all I know the EDC limiter is triggering before the FIT_PRE_voltage limiter that seems to be dictating the global limit, or responds in such a transient manner that it's partially filtered out when calculating the other limits.

I don't know what's the point of testing with dpm disabled if it just creates further uncertainty, beyond the obvious impact on some non-dpm functionality.
And please, don't use the naming from zenptmonitor - it's painful to read )
"Fit voltage" and "Fit-Pre Voltage" ARE voltages, not frequencies.

Blameless said:
I also found a load where the EDC limit could induce clock stretching without hitting the reported global frequency limit:

I found the 1st screenshot very intetesting...
Don't you think the behavior of the infrastructure limit labeled as CCA in my monitor app fits the description of "High Temperature Clock" shown in the main HWInfo window?
(I might have mixed up the last two, i.e. 7th is CCA and 8th is actually HTFMAX)
Curious about Peak_CCLK in this screenshot was 4300. Did it hold when Tctl >= 85° ? Did you notice when this limit was engaged?

The thing is, from what I could tell, there are only two reliable labels sources came from old pmtable versions for Matisse and Renoir. All others are basically made up empirically.
Matisse and early Vermeer pmtables has only six freq.limits in a following order:
PPT, TDC, THM, PROCHOT, VOLTAGE, CCA.
Later two more were added, GLOBAL and HTFMAX, which already presented in other reliable scheme for the APU (370001 and 400005) with a total of 11 limits:
GLOBAL, STAPM, PPT fast, PPT slow, PPT apu, TDC, THM, HTFMAX, PROCHOT, VOLTAGE, CCA.
The Vermeer version with 8 limits (380905 and 380904) appeared if I remember correctly in agesa 1.2.0.x and I doubt anyone has exact labeling scheme apart from NDA people.

Blameless · Oct 26, 2023

PJVol said:
I don't know what's the point of testing with dpm disabled if it just creates further uncertainty, beyond the obvious impact on some non-dpm functionality.

It's a matter of convenience. This is a system I actually use, not my test bench, and I normally have LCLK DPM disabled because it faster that way. Outside of updates/testing it gets restarted maybe twice a month.

The only thing DPM enabled vs. disabled seems to change with regard to the L3 clock behavior is the point at which the core/L3 clocks and global clock limit diverges (right from the start at an EDC limit of 140A with the Linpack binaries I'm using with LCLK DPM enabled) and the point at which serious clock stretching appears (sub-40A EDC limit with LCLK DPM enabled).

With LCLK DPM enabled, I'm mostly PPT or thermally limited until very low EDC limits.

PJVol said:
And please, don't use the naming from zenptmonitor - it's painful to read )

I'm trying to use what's listed because I'm not always certain what the ZenPTMonitor names correspond to elsewhere. There are active values that are clearly not represented in PBO2 Tuner's PMT monitoring and values that are clearly referncing the same thing that have different names.

PJVol said:
Don't you think the behavior of the infrastructure limit labeled as CCA in my monitor app fits the description of "High Temperature Clock" shown in the main HWInfo window?
(I might have mixed up the last two, i.e. 7th is CCA and 8th is actually HTFMAX)
Curious about Peak_CCLK in this screenshot was 4300. Did it hold when Tctl >= 85° ? Did you notice when this limit was engaged?

I'm not sure what CCA is an acronym for in this context, but with LCLK DPM enabled it doesn't track with "High Temperature Clock" at all, the CCA frequency was well below 4300 at 85C. With LCLK DPM disabled, the CCA frequency doesn't seem affected by temperature alone, I have to be hitting EDC or some other limit.

The High Temperature Clock limit is what I think (with LCLK DPM enabled) is engaging at 77-78C and reaches 4300 at 85C as I mentioned in post 8003. The only frequency limit shown in PMTMonitor at these temperatures with LCLK DPM enabled at light load is 'voltage'. 85C seems to be an end-point or mid-point (hard to say for sure without another test), not the start. I think you thought I was refering to Hardware Thermal Control earlier; I'll try to be more clear about which value I'm talking about.

PJVol said:
The thing is, from what I could tell, there are only two reliable labels sources came from old pmtable versions for Matisse and Renoir. All others are basically made up empirically.
Matisse and early Vermeer pmtables has only six freq.limits in a following order:
PPT, TDC, THM, PROCHOT, VOLTAGE, CCA.
Later two more were added, GLOBAL and HTFMAX, which already presented in other reliable scheme for the APU (370001 and 400005) with a total of 11 limits:
GLOBAL, STAPM, PPT fast, PPT slow, PPT apu, TDC, THM, HTFMAX, PROCHOT, VOLTAGE, CCA.
The Vermeer version with 8 limits (380905 and 380904) appeared if I remember correctly in agesa 1.2.0.x and I doubt anyone has exact labeling scheme apart from NDA people.

Thanks for the info.

Do you have links to the pm_table documentation?

T[]RK · Oct 26, 2023

For some reason i can't try this "LCLK DPM" option\trick in ASUS BIOS (in AMD CBS => NBIO Common Options => SMU Common Options). There is only "Auto" and "Manual". It can't be "Disable". If i select "Manual" it will open list with a lot of sockets.

Blameless · Oct 26, 2023

T[]RK said:
For some reason i can't try this "LCLK DPM" option\trick in ASUS BIOS (in AMD CBS => NBIO Common Options => SMU Common Options). There is only "Auto" and "Manual". It can't be "Disable". If i select "Manual" it will open list with a lot of sockets.

Wrong location. The values in the SMU page allow you to choose between LCLK DPM levels for different NBIO channels, overriding the default behavior, if LCLK DPM is enabled.

The setting that disables LCLK DPM entirely (and triggers the bug/undocumented behavior) is usually in the AMD Overclocking -> LCLK Frequency Selection (or something to that effect) section.

eighty20 · Oct 26, 2023

Got my 1T GDM off somewhat stable so i did a bunch of benchmarks for fun.

103.6bclk, stock PBO, CO -0, offset -0.05vcore,auto LLC, LCLK DPM disable, L1/L2 enable.

Had to switch to 4k to get every bm in.

~~Seems blur after uploaded on ocn, this one is bit clearer~~ nvm, managed to get the full size in

Edit1: passed a couple absolut cycles, and i forgot to open zentimings. Testing with lower rc and other stuff now lol.

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Edit2: added AIDA64 smt on vs off.
SMT ON

SMT OFF

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Owterspace · Oct 26, 2023

There is nothing wrong with 2T.. you can run lower tRFC I find.. I like to run C15.

eighty20 · Oct 26, 2023

Owterspace said:
There is nothing wrong with 2T.. you can run lower tRFC I find.. I like to run C15.

yeah I just wanna see if I can do it. Wanted to get 120ns for RFC but bclk is messing it up a bit.

T[]RK · Oct 26, 2023

After installing Alphacool Eisbaer 360 AiO and with old Noctua NT-H1 thermal paste (same 0.12 mm layer) i was able to get this results.

Multi: 14 575 pts
Single: 1 494 pts

No OC, no CO, no offsets, memory in 3200 MHz JEDEC. CPPC Enabled, CPPC Preferred Cores also enabled, DF Cstate - Disabled, Spread Spectrum disabled. Nothing special.

But for some reason i can't get same (or even better since... well... 360 AiO) result in 3DMark CPU Profile benchmark. 7321 points was top (with positive vCore = +0.01875!). But i got 7400+ with Air cooler before... Something wrong and i can't understand what exactly. Results in CPU Profile was even lower then 7300 points untill i re-enabled "AMI Native NVMe Driver Support" in BIOS. It help (i guess) with 1 thread - from 898-900 to 903.

Here is my post with results:

5800X3D Owners

Scroll Down For Gaming Results If Not Interested In Details TLDR: 5800X3D is a monster at gaming, is easily OCd, and runs hot and beats even a tuned 5950x in most games; for general computing the 5800x, and more importantly now, the 5700x trounce it when OCd as well but cannot match it in...

www.overclock.net

Temp during max and 16 threads was 83.75°C and 84.00°C and frequency higher then 4300 MHz (close to 4400 MHz).

With AiO i got 75.75°C and 76.00°C, but result is lower! How it's even possible? =))

But Cinebench results are better, yes.

Blameless said:
The setting that disables LCLK DPM entirely (and triggers the bug/undocumented behavior) is usually in the AMD Overclocking -> LCLK Frequency Selection (or something to that effect) section.

Will look. Usually i ignore AMD Overclocking part.

bmtmis · Oct 27, 2023

That setting for LCLK DPM is 100% not on my X570 Aorus Master, can't seem to find it

T[]RK · Oct 27, 2023

O.K., tested it. On ASUS ROG Crosshair VIII Dark Hero (BIOS v4602) this setting located in "Advanced" => "AMD Overclocking" => "LCLK Frequency Control"

LCLK DPM

LCLK Power Management

Available options are:
1. Auto (Default); Description saying that Auto = Enabled.
2. Enabled;
3. Disabled;

When enabled - automaticly lower LCLK frequency to save power. Disabled = Fixed LCLK.

NOTE: If "LCLK DPM" will be disabled, it will automaticly hide "LCLK DPM Enhanced PCIe Detection".

I run few tests:

Cinebench R23:

Multi Core: 14 367 pts
Single Core: 1 487 pts

3DMark CPU Profile:

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Max threads: 7 228
1-thread: 895

Temps during Max and 16 threads: 71,13°C and 71,25°C.

PBO2 Tuner monitor:

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LCLK_EFF when idle.

So, it's either description is wrong or setting work wrong. It was Disabled, but instead of fixed value - it lowering it which confirmed by monitoring, temperature during load and final results.

Now, let's test with LCLK DPM Enabled:

Cinebench R23:

Building Window Table Comfort Interior design

Multi Core: 14 612 pts
Single Core: 1 493 pts

3DMark CPU Profile:

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Max threads: 7 329
1-thread: 903

Temps during Max and 16 threads: 75,13°C and 75,38°C.

So, performance higher with this option Enabled. PBO2 Tuner monitor also show LCLK_EFF behavior exactly the same - lowering when idle.

Blameless · Oct 27, 2023

T[]RK said:
So, it's either description is wrong or setting work wrong.

I'd guess that ASUS disabled the functionality, possibly to avoid the bug.

What happens if you manually set LCLK frequency control to 594MHz for both?

T[]RK · Oct 27, 2023

Blameless said:
What happens if you manually set LCLK frequency control to 594MHz for both?

Need to test. Why 594 MHz anyway? Default setting look's like 593MHz.

Also, look's like i finally find reason why HWiNFO64 got lower effective clock. Now it look like this:

Colorfulness Product Font Rectangle Screenshot

OMG, people you have NO IDEA. It was damn HDD. =) I disconnected it and tested without it - and BOOM - correct results! Boot time also faster now - 8,1 sec (without fast boot).

It's not over yet! In addition to that i disable Nahimic Service which spin like crazy CPU\AiO fans during each boot.

Here is another Cinebench R23 run with all thing combined:
LCLK DPM = Enable
DF_Cstates = Disable
HDD Disk = Disconnected
Nahimic Service = Shut down

Multi Core: 14 696 pts
Single Core: 1 495 pts

eighty20 · Oct 27, 2023

T[]RK said:
Need to test. Why 594 MHz anyway? Default setting look's like 593MHz.

I set mine at 1000 to test it. 1200 doesnt boot.

Got lower pts in cb23 multi after disable n set LCLK auto. Changed it to 1000 improved a bit but still 20-30pts lower than auto.

LCLK enable
103.6bclk, stock PBO, CO -0, offset -0.05vcore,auto LLC, L1/L2 enable

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And disable Data Scramble gave me blues screen.

PJVol · Oct 27, 2023

Blameless said:
I'd guess that ASUS disabled the functionality, possibly to avoid the bug.

More likely this setting itself is the bug and in fact doing something else. Probably somewhere in agesa DXE. I don't remember when exactly it was appeared in setup.
LCLK is floating between 292 and 592mhz anyway.

There are also DPM settings in the CBS->NBIO submenu, and if you have SMU Debug Tool, you may set min/max DPM states manually from OS via HSMP mailbox.
The command is 0x12, argument 0x30n0m, where n and m are max and min DPM states in a 0-2 range, where 0 - 300mhz, 1 - 400mhz, 2 - 593mhz, i.e. 0x30100 will set min 300 and max 400 for the nbio instance #3 ( seems like all single ccd vermeers have this instance ID). Although even setting both to 2 still won't prevent power saving fo me.

Blameless said:
The only thing DPM enabled vs. disabled seems to change with regard to the L3 clock behavior is the point at which the core/L3 clocks and global clock limit diverges (right from the start at an EDC limit of 140A with the Linpack binaries I'm using with LCLK DPM enabled) and the point at which serious clock stretching appears (sub-40A EDC limit with LCLK DPM enabled).
With LCLK DPM enabled, I'm mostly PPT or thermally limited until very low EDC limits.

I mean changing EDC within "TDC-limit - EDC limit" range, in your case 90-140, because it starts to limit TDC if set below. Anyway, thanks for tests, they convinced me that at least CCA freq. is where it should be in my tool.

Blameless said:
Do you have links to the pm_table documentation?

No, and based on а very brief conversation with Mаrtin some time ago, suсh documents are subject to even striсter control than just ndа.
All we have and use are two old projects, both having fully labeled pm tables in the sources.
If curious, look here

GitHub - hattedsquirrel/ryzen_monitor: Monitor power information of Ryzen processors via the PM table of the SMU

Monitor power information of Ryzen processors via the PM table of the SMU - hattedsquirrel/ryzen_monitor

github.com

Blameless · Oct 28, 2023

T[]RK said:
Why 594 MHz anyway?

Because it's the lowest setting that is above the stock range.

eighty20 said:
I set mine at 1000 to test it. 1200 doesnt boot.

Even 1000 is extremely high and probably a serious risk for I/O data corruption.

eighty20 said:
And disable Data Scramble gave me blues screen.

Data scramble should never be disabled as it dramatically improves the stability of the memory interface and should have no overhead.

This is the most concise explanation I can find, and it applies equally to AMD platforms (and pretty much anything else not transmitting purely random data): Data Scrambling - 009 - ID:655258 | 12th Generation Intel® Core™ Processors

Most modern platforms use it and do not expose settings to disable it.

PJVol said:
More likely this setting itself is the bug and in fact doing something else. Probably somewhere in agesa DXE. I don't remember when exactly it was appeared in setup.

It's in the oldest firmware I have that supports Vermeer, not sure if it was available earlier, and exists to at least AGESA 1.2.0.A. All of my boards (a mix of ASRock, MSI, and Gigabyte, currently) have this setting somewhere, and all of them behave the same way with it disabled. I'm pretty sure my ASUS Crosshair VIII Impact had it as well, even on the 3000 series, but I killed that board (twice) quite a while back and can't retest.

PJVol said:
No, and based on а very brief conversation with Mаrtin some time ago, suсh documents are subject to even striсter control than just ndа.
All we have and use are two old projects, both having fully labeled pm tables in the sources.
If curious, look here

GitHub - hattedsquirrel/ryzen_monitor: Monitor power information of Ryzen processors via the PM table of the SMU

Monitor power information of Ryzen processors via the PM table of the SMU - hattedsquirrel/ryzen_monitor

github.com

I used to be able to view some of it related to the APUs at kernel.org, but they revamped the site recently and I've been having trouble finding the same info again.

T[]RK · Oct 28, 2023

Blameless said:
Because it's the lowest setting that is above the stock range.

O.K., got it. Are there any way\method to calculate it? Is it connected to something (like Infinity Fabric and DDR?) or 593 MHz is just maximum by itself? Just weird look number...

Anyway
Today i tested cold boot and 3DMark CPU Profile (no Cinebench R23 since after cold boot i can run only one banchmark):

Max threads: 7 341
1-thread: 902
Max threads temp: 74,49°C
16-threads temp: 74,87°C

Almost all frequency lines are straight. Very nice!

So, at this point it's obvious that current limit is temperature. Room temp is ~25-25,5°C.

And another run with -30 CO on all cores (via PBO2 Tuner) to eliminate high temperature from CPU work itself (since i can't change room temperature). And via BIOS it should be even better:

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Max threads: 7 567
1-thread: 904

All frequency lines pretty much straight lines:
Max threads: 4 448,96 MHz (Max temp: 69,38°C)
16 threads: 4 448,96 MHz (Max temp: 69,75°C)
8 threads: 4 448,96 MHz (Max temp: 63,75°C)
4 threads: 4 448,96 MHz with small bump at start with 4 548,94 MHz (Max temp: 58,50°C)
2 threads: 4 548,94 MHz with drops to 4 448,96 MHz (Max temp: 57,13°C)
1 thread: both 4 548,94 & 4 448,96 MHz (Max temp: 56,75°C)

So, with 360 AiO and -30 CO temperature limit pretty much was eliminated and not triggered. Max temperature probably should not go higher then 70°C.

I think it's possible to low temperature on 5°C more with better TiM and with offset waterblock bracket (mainly). I sent Alphacool message about it. Maybe they might share drawing or dimensions of their bracket for laser cut.

P.S. Yeah, i DON'T LIKE water in my PC, but i must admit that it very powerful (especially with copper radiator like Alphacool).

PJVol · Oct 28, 2023

T[]RK said:
Almost all frequency lines are straight. Very nice!

Yeah... mine looks jagged, so I guess I lost the lottery

Blameless · Oct 28, 2023

In the 3DMark CPU profile, the frequency consistency with anything more than two threads is mostly the power profile one is using. Temperature is relevant too, if it's getting into the upper 70s or higher.

At one or two threads, things like timer serialization, how one has driver interrupts setup, and background tasks can matter. Of course, disabling C6 also makes those tests pretty flat.

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