Wasn’t sure which thread category to make this in but I was curious. I see a couple people say that “65280 (1024 multiples) is the proper way of setting REFI so it doesn’t skip refreshes” and I was wondering how true this is, what benefits it has (if any) and why?
tREFI 65280 or 65535
niko_
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Wasn’t sure which thread category to make this in but I was curious. I see a couple people say that “65280 (1024 multiples) is the proper way of setting REFI so it doesn’t skip refreshes” and I was wondering how true this is, what benefits it has (if any) and why?
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It honestly doesnt matter as much as you might think it may.
If you watch BuildZoid he sets 65432 for his 48GB kit on an Intel 13900K because it's easy to enter lol. And that guy knows a HELL of ALOT more than 99.999999% of the people on this forum.
If you watch BuildZoid he sets 65432 for his 48GB kit on an Intel 13900K because it's easy to enter lol. And that guy knows a HELL of ALOT more than 99.999999% of the people on this forum.
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65280 for Ryzen related to some or other timing interval thing with tREFI, that happens on AMD. It was discussed around a year ago. The 65535 is because Intel IMCs uses multiples of tREFIx9 (255) and then for some or other reason you subtract 1. I can’t remember what it was, but bianbao explained it.
The recommendations I made come directly from Veii (AMD) and bianbao (Intel). I don’t know how big of an impact they make, but there’s no reason not to set them optimally when it only takes a second to do.
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Would you happen to know where i can find this?
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There are posts on OCN, but I wouldn’t be able to search for them right now.
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Also the fact that buildzoid is absolutely not an expert when it comes to DDR5 memory OCing.. posting a ton of videos and being extremely knowledgeable on PCB breakdowns does not make you an expert in every single area.
His Intel memory timing suggestions were atrocious. He was pretty solid with DDR4, and maybe he's cleaned up his DDR5 knowledge, but taking his word as gospel is wrong.
The reason you subtract 1 from the tREFI is due to ASUS BIOS using "0" as "1", or as a value itself, if I remember Bianbao's explanation correctly.
tRFC mini DDR4 WIP - Google Sheets
This should help you get started. Check the "Veii's Shenanigan's" tab for some timing rules, and how to calculate them. Much of this requires actual leg-work and learning; if you want someone to tell you exactly what timings to set, then that timing sheet won't help you too much. Takes a bit to get adjusted because there is DDR4 stuff mixed in, but poke around.
Also, be careful who you take advice from around here. There are a lot of people who try to sound like they know a lot more than they do, and have zero idea what they're talking about.
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Why would the timing registers even exist if they are dictated by "rules" and calculations?
Have anyone of you who recommend these timing rules actually taken the time to benchmark the impact? Last time I did, I tried tREFI 65024 vs 65535 and found 65535 to be very slightly faster in PYPrime despite 65024 being "optimal".
Have anyone of you who recommend these timing rules actually taken the time to benchmark the impact? Last time I did, I tried tREFI 65024 vs 65535 and found 65535 to be very slightly faster in PYPrime despite 65024 being "optimal".
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Who said 65024 is optimal for Intel?
65535 is divisible by 255 (tREFIx9), so not sure where 65024 came from; the 65280 is an AMD IMC thing.. apparently there is a reason behind it, but I’m not an AMD guy.
I'll just leave it here.
I'm also not sure about 65280 on AMD. But I might have a clue why it is suggested.
I'm also not sure about 65280 on AMD. But I might have a clue why it is suggested.
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I think it was anta777 or 1usmus
EDIT: by searching for 65024 I found it quickly: https://www.overclock.net/threads/o.../threads/official-intel-ddr4-24-7-memory-stability-thread.1569364/post-28884106
It was anta777, and for a very similar reasoning to what I'm seeing for 65280. I expect Veii tested his idea just as extensively as anta777 did before posting it here.
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I don’t know why you’d run tREFIx9 @ 127 on Intel, though, when we are can run tREFIx9 @ 255 (256). Anta doesn’t really explain that. Now if there’s a reason to run tREFIx9, which leads to why 65024 is a better number, then I guess I’d understand that better. The lower tREFIx9 appears to be what drives his optimal value for tREFI.
I will say that there is more reasoning behind running the values in a way that is easily divisible. It’s a bit deeper than just looking at raw performance numbers in a benchmark — keeping tREFI divisible by your tREFIx9 is for it to fit in with other timings in case of delays.
Running it “optimal” or “accurate” could mean that you don’t get a microstutter once in a while. I don’t think the minuscule performance gain in synthetics is worth it.
We simply don’t know enough.
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A microstutter in a game context is a frame that takes 10 - 1000 milliseconds, or 10000 - 1000000 microseconds
A memory refresh interval cycle of 65535 ticks takes 30 microseconds or so, depending on memory frequency.
There's absolutely no way a memory refresh intervall miss causes a compound delay that's 300 - 30000 times longer.
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You’re arguing very specifically over semantics, and also as if you can’t have misses consecutively in a row. I’ll go with what Bianbao said, regarding the tREFI being lined with tREFIx9 to keep it aligned with other timings in case of delays.
The raw performance is there by going beyond/out of “optimal” range, but I don’t see how higher numbers in synthetic benchmarks is somehow a justification that it’s completely fine. Like I said, we simply don’t know enough. I personally don’t think the miniscule gains in synthetic benchmarks is worth cranking the tREFI out of range.. however I don’t see anyone recommending 65024 for a 255 tREFIx9, only for 126 (7). 65536 (5) is divisible by 255 tREFIx9, so that’s “optimal” anyway.. 131071 (2) is the same thing, and then double again for max tREFI.
I guess my point is: if you’re running 255 tREFIx9, then 65535 is divisible, so this back-and-forth is pointless.
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65535.
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If this “synchronicity” between REFI and RFC would have even the slightest significance, it would be described in at least one technical documentation - JEDEC or micron datasheets for example. At one time, back on DDR4, I studied JEDEC and the micron datasheet for RFC and REFI (as well as ddr5 jedec), and there is not the slightest mention of the multiplicity of one to the other or any kind of synchronicity. For this reason, there can be no talk of any stutters at all.
Also ask yourself why such simple logic was not implemented in the BIOS when we set the timings to Auto? The answer is it doesn't matter
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There's also the question of how often memory is accessed. I doubt the access patterns to DRAM are so intense that there are 0 idle cycles in one tREFI period, at least for most gaming loads.
I personally don't bother reading the datasheets, and rather just increase/lower timings until I encounter stability or performance issues. Weirdly enough that seems to work out better than following "timing rules".
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