[ApT01]

Can't POST when i set GDM off 2T.
Any ideas?

Try tRDWR=9, t=tWRRD=3

 

[ApT01]

Been lurking on this thread for a while now. This is what I managed to get mine to:

Micron Rev.E C9BJZ 3000C15 DR kit @ 3800 16-20/8-18-21-60 1T GDM Off
Vdimm:1.4v
Vsoc:1.13v
Cldo_vddp:0.95v
Vddg_ccd/iod:0.9v/1.05v
Cpu 1.8v:1.85v

Everything is very stable and I don't get any WHEAs but I can't seem to tighten it any more despite going through a myriad of settings. Is this it, have I reached the limits of my hardware? Does anyone see anything glaringly wrong in my settings? Any help would be appreciated.

 

[ApT01]

Running CL16 and tCWL 14 can be the cause of some stability problems when lowering RCDRD, this also why RDWR is at 11. Becareful with WRRD 1 with DR it can cause system to hang when RDWR is at 8/9 you may need WRRD at 2 or 3. So first try to change tCWL from 14 to 16.

Not sure if there is a difference between SR and DR C9BJZ but I'm sure RCDRD can go lower to 19 and be stable.
You can also do me a favor and save me some time by running 50 cycles on this. Can change tWTRL/S to 4/8 adjust tWR 16 and RTP 8 if you need to should be more stable

I followed your advice with setting tCWL=16 and I was able to tighten timings some more. I tried tRCDRD at 19 but I get dozens of error 6 instantly. This is where I'm at now:

If I try to tighten them anymore I get multiple error 4s with occasional 5,3 and 14. Though it only errors after a couple of cycles. Any ideas?

 

[ApT01]

Thanks but unfortunately it won't post :/

I've got DR C9BJZ sticks like you, try my settings. You can set tRP to 16 since your sticks seem to be fine with it. Vdimm@1.4v

If this is stable you can up the vdimm and try for CL15/14.

 

[ApT01]

Ok, after a lot of tests these days it's almost stable on my end. Almost because of 1 error right in the end of this test:
View attachment 2615798
What could this be? Any ideas of values I should change?

Try cldo_vddp 0.9v, add +1 to trcd_rd and maybe trp and trc too, that should give you some more stability. If that is stable you can start with lowering trdwr,twrrd to 9,4 or 8,3 and scls to 4,4.

 

[ApT01]

Got this kit of 3600c16 rev.E for super cheap on sale some time back.
Apparently all the newer 3600 kits come with the 4400MT/s ICs(confirmed by thiaphoon burner).

Not really much of an upgrade to my 3000c15 sticks.

 

[ApT01]

That is very good result for ZEN 2. If you can get 3866 to run on that IMC then you can do 3866 CL15 you will only need +/-1.45V
View attachment 2617231 View attachment 2617232

Yes but unfortunately IF hits a hard wall above 1900, I've tried many things but not once has it even booted up above that. Honestly I'm just happy it runs 1900 at all.

 

[ApT01]

I tried RTTs 24/40/60 - 20 - 24 - 24 with VDRAM 1.45V, but no luck even with more loose timings. VDRAM actually changed nothing, similar results to using 1.4 vDRAM (1.39V on sensors is 1.4V).

You need to up tRCDRD and tRP by atleast +1. Your current settings are too tight for rev e and are being autocorrected by GDM.

 

[ApT01]

I did google and others claimed GDM disabling caused post issues as well. Some claimed more voltage is required.

I can't enable anything until RAM is stable. That would introduce additional points of failure. If you believed the CPU side of this was causing the instability of the IMC what would you check/change? Most options are left on auto with PBO disabled.

Have you tried playing around with the ProcODT, RTTs or Drive Strengths?. Try and see if ProcODT at 32 or 36 ohms makes any difference. Maybe up ClkDrvStr to 40 if that doesn't work.

 

[ApT01]

At 2000 OS will run but it's quite unstable, I get screen blinks, half-loaded windows and pages, black screens, reboots and a lot of WHEA 19 errors each second.

Sounds like IF instability more than ram. Try to increase VDDG to 1.05V , CPU1.8V to 1.9V and a lower ProcODT.

 

[ApT01]

Error #4 after 42 cycles in 1usmus v3... Which is related to #14 again.

Spoiler: HWInfo, ZenTimings, TM5

View attachment 2651696

Guess VDIMM is too high at 1,47V or I need to play around with VTT again. With the #4 error now, kinda unsure on VTT anymore. Guess I'll do 1,46V VDIMM next.

I'll keep TM5 running for now, to see if anything else fails. (And to maybe wait for a reply if I should change anything else.)
For my next run I guess I'll set tRTP/ tWR to 8/ 16, IOD to 1,07V, VSOC to 1,17V and VDD18 back to 1,92V. I won't immediately notice if that works out for IF stability, will need to test that by actually using the system to play BG3 with a friend (to see if the microphone issue still happens).

Those really late error 4 & 14s on rev E are most likely too tight tWR/tRTP. Also you shouldn't need more than 1.4v for 3800c16.

 

[ApT01]

Just got home, 164 cycles of 1usmus v3, no errors (yet..?).
Set it to 200 last time because I knew I would only be able to check it right now.

Spoiler: HWInfo, ZenTimings, TM5

View attachment 2651938

It was the tRTP/ tWR... Now it would prolly make sense to "reset" the DrvStrs to 24/24/24/24 and the ProcOdt to 36,9 right? Or is this irrelevant?
Now that I know that this works out, I maybe can try to see if I can get a lower tCL/tRCDRD to work. For that I would have to play with voltages again, I'll see how I feel about this.
I'll also prolly set tRFC back to 551, it looks prettier 😅

200 cycles, damn thats a lot! If you error out on cycle 200 then you'd have to suspect cosmic rays or the rotation of the earth as causes lol.

Anyways, if the current settings work then its best not to touch them. And as far as tCL goes, it scales with voltage but honestly it doesn't make much of a difference and tRCD only depends on the IC bin and doesn't scale at all. I still think you're using too much voltage for you're current settings. Maybe try to drop it near 1.4v.

 

[ApT01]

Probably a Buildzoid viewer since I see tRAS at 21 and for Samsung B-die that maybe fine but I would not recommend that for Micron RAM.
Correct RC can improve performance on Micron Ram and lower latency.
View attachment 2651982

I'm interested in this bit, I've always done the leave tRAS at 21 thing as well. Could you tell me which benchmarks you used to test? I want to try and see if I can replicate it. My current timings are tRP-12,tRAS-21,t-RC-54

 

[ApT01]

I tested this with Veii sometime back unfortunately most of the old screenshots posted in this thread seems to be no longer be available.

It is however easy to test using AIDA64 just keep all variables the same and use the above formula record before and after results.
It is recommended to ignore the first AIDA64 results and repeat the test I usually ran an average of 5 ignoring the first one.

So I did the testing as you suggested and this is what I got;

AIDA64

tRP-12,tRAS-21,tRC-54

Run # | R | W | C | L
1 , 55751 , 30399 , 53774 , 66.8
2 , 55658 , 30400 , 53799 , 66.9
3 , 55655 , 30399 , 53830 , 66.8
4 , 55548 , 30399 , 53716 , 66.9
5 , 55497 , 30399 , 53827 , 66.7

tRP-12,tRAS-45,tRC-57

Run # | R | W | C | L
1 , 55912 , 30399 , 53882 , 66.8
2 , 55542 , 30399 , 53727 , 66.9
3 , 55478 , 30399 , 53272 , 66.8
4 , 55525 , 30400 , 53612 , 67.0
5 , 55444 , 30399 , 53679 , 66.8

There doesn't seem to be much difference at least for me. Is there any timing I should have set differently?

 

[ApT01]

Seems tRP,tRAS and RC is not according to the formula I used.

tCL =14 Then tRAS should be 42
tRTP same has RCDRD so 18
RC = 60

if tCL 15 then tRAS=45 RC =63
I keep tRCDWR, tRCDRD and tRP the same

Try those settings but also good if you post Zentimings. Try running Y-cruncher or Linpack xtreme and see if you have any performance gains.

Edit.
Finally! I managed to find the post and all the pictures are working.

https://www.overclock.net/threads/official-amd-ryzen-ddr4-24-7-memory-stability-thread.1628751/post-29080326

I used tCL-15,tRP-12, then according to the formula:- tRAS-45 and tRC-45+12=57.

I'll try redoing the tests using the same primaries you used.

 

[ApT01]

Seems tRP,tRAS and RC is not according to the formula I used.

tCL =14 Then tRAS should be 42
tRTP same has RCDRD so 18
RC = 60

if tCL 15 then tRAS=45 RC =63
I keep tRCDWR, tRCDRD and tRP the same

Try those settings but also good if you post Zentimings. Try running Y-cruncher or Linpack xtreme and see if you have any performance gains.

Edit.
Finally! I managed to find the post and all the pictures are working.

https://www.overclock.net/threads/official-amd-ryzen-ddr4-24-7-memory-stability-thread.1628751/post-29080326

I used tCL-15,tRP-12, then according to the formula:- tRAS-45 and tRC-45+12=57.

I'll try redoing the tests using the same primaries you used.

Finished testing it:

I copied your primary timings as follows:-

Here are the results:-

AIDA64
Run # | R | W | C | L
1 , 55672 , 30399 , 53514 , 66.8
2 , 55204 , 30399 , 53302 , 66.7
3 , 55268 , 30399 , 53355 , 66.8
4 , 55199 , 30399 , 53315 , 66.9
5 , 55221 , 30399 , 53328 , 66.9

y-cruncher 0.8.3- pi5b
Run 1: 340.874s
Run 2: 340.921s
Run 3: 340.402s

and I also ran y-cruncher on my original timings(tCL-15,tRCD-18/8,tRP-12,tRAS-21,tRC-54):-

y-cruncher 0.8.3- pi5b
Run 1:338.736s
Run 2:339.159s
Run 3:338.429s

 

[ApT01]

Looks like your original settings is faster.

Have you tried tWR 16 and tRTP 8? it may work since you adjusted the primary timings.

I use to run tWTRS at 2 as well something that most Samsung B-die cant do but it proved unstable at higher FCLK so had to increase that to 3.
View attachment 2652306

I tried but 16/8 wouldn't work due to my motherboard's limitation. I recently redid my ram oc to aim for a lower voltages all around. 16/8 was on the edge of stability(sometimes no errors, sometimes 1 error/75 cycles of 1usmus) and my motherboard only allows 50mv adjustments on vDIMM and also has no LLC(who came up with this design). So I couldn't fine tune the voltage and get it fully stable.

But interestingly enough, as you already mentioned in an earlier post, CL15 seems to be the sweet spot because PHYRDL finally came down to 26(which I couldn't manage with an even tCL) and that somehow completely negated the lost performance from going CL14>CL15.

Spoiler

 

[ApT01]

So I've spent better part of my day after work doing some benching and trying to answer my previous questions.
I did a Linpack Extreme 10G for 1.5h to get steady state on my AIO to not mess with the early results and I also tested in Windows 11 safe mode to have more consistent results due to much lesser variability.

@The_King is absolutely right that tRAS = tCL x 3 and tRC = tRAS + tRP gives quite solid results on rev. E vs just tightest timings. That said, I've noticed that you run tRP in sync with tRCDRD/WR and found that tightening tRP helps.

Also lowering tRC out of sync of the tRC = tRAS + tRP formula improves y-cruncher results but impacts Linpack.
All other timings from my previous post are the same.

View attachment 2652368


Next I've tried to see how SCL timings affect this and it's a bit of a mixed bag between the benchmarks.

View attachment 2652369

I have not got time to test more and I know this is not that comprehensive test and I've tried to limit variability as much as was reasonably possible at the time and will test further along with some other timings. It's quite a time consuming process.

Now I am stumped. Looking at yours and @The_King 's results there is apparently some performance to be had by running the timings in sync but somehow it evades me.

I tested the following timings which according to your findings should give me the best performance;

this is what I get with y-cruncher 5b;
Run 1: 339.936s
Run 2: 339.467s
Run 3: 339.956s

which is still slower that what I got with tRAS-21,tRC-54.

Any ideas on what to change guys?

 

[ApT01]

@ApT01 I think it comes down the variability in your test methodology. I found that Ryzen is quite sensitive to temp which results in clock stretching so on cold boots I tend to score best results since my AIO water is cold which will skew results for first batch of benchmarks and will make them seem like they are better even though they are worse because the score will gradually go down as the cooler approaching the steady state so all benching results will be invalid. I also did all test in Windows Safe mode as I found it to have very consistent results (for these particular benchmarks, many other stuff will not even run there).
That's why I bothered to blast Linpack for many loops before doing benchmarking for this. Only thing I can't control is my room temp. All the results are also listed in the order I tested them so the room was also getting gradually warmer.

Thats the thing right, I tested Linpack with each set of timings sequentially having plenty of time inbetween runs, so heat soak can't be the issue. And I use a stripped LTSC install so background processes wouldn't interfere. Have you done any benching at tRAS 21, tRC-54 ?