[Veii]

Well darn it. I can tell you this kit won't do 1T GDM off.

And I've never read anywhere about GDM changing tCWL to tCL. What literature is that from?

And the Aida latency was 63ns first run. 62.9ns second run. And then settled at 62.8ns last few runs.

I have to browse through the documents again. It was on an Samsung JEDEC sheet
GDM changes:
tCWL=tCL
uses tCKE
allows tRTP only be an even number
and i'm a bit unsure still on the first 4 primaries till tRAS (rounding up)

But i'm pretty sure on tCL=tCWL , usually ZenTimings should've detected that
Maybe upgrade to 1.1.0 and recheck
One thing that also is awkward, is your PowerDown mode
Normal one for 4 dimms, Alternative is for 2 dimms
Not going to judge on SD, DD's as people still have random results with these

Aida64 latency is a bit high tho
I'd suspect sub 61ns
GDM off 2T would work too, just tCWL 14 would break one ruleset
it would result in tRC 40
While it might pass with tRC -2 for Single Rank, it's not "perfect" yet with tCWL 14 :/

A2 Vipers with a lot of ClkDrvStrength should get GDM disabled :thinking:
I mean you pretty much have a new stable set, soo you can test what it needs to get GDM off
To what i remember GDM adds exactly 2ns , you might be sub 61ns already ~ IF you get 1T to work
2T should be about equal to 1T when no autocorrection happens

This all assumes i'm right with GDM, but i'm pretty sure it did.
We'll figure it out later, tCWL 11 would break it for sure and tCWL 16 too
tCWL 14 might be just borderline fine ~ although it should be 12 without GDM

 

[Veii]

Tried this set but as usual my kit won't do RCDRD 14 no matter what and requires 1.58V to not bsod instantly. Seems way faster than my standard timings (62.2 vs 62.8 ns); 61.0 ns in "fast degradation" mode(4725MHz on two cores)

Try tRCD_WR 9 , tRCD_RD 15 to average it out
Problem is, tRCD_WR 9 breaks it
i can't let you use odd tWR to offset it ~ i think even with GDM disabled, it doesn't let me use tWR 13
Retry with 2T instead 1T

Someday we'll figure it out, but odd number tRCD breaks calculation
Main issue is that tWR can't be odd, even if tRTP can and we can somehow work to get tRP be an exact even number
Sit on it today along time ,, but unless tWR can be an odd number ~ there is no way how it can work with tRCD 15
Always end up with tRP as .5 value
Same for tCL 15, doesn't work without having another odd number ~ which must be tWR.

Well anyways , try tRCD_WR 9 - for tRP at least to be correct
tRCD_RD 15 with tRCD_WR 8 pushes required tRP as 11.5
tRP 12 should work, but then that odd _WR breaks tRC math
If one little thing is off, it needs a whole redesign

 

[rares495]

Try tRCD_WR 9 , tRCD_RD 15 to average it out
Problem is, tRCD_WR 9 breaks it
i can't let you use odd tWR to offset it ~ i think even with GDM disabled, it doesn't let me use tWR 13
Retry with 2T instead 1T

Someday we'll figure it out, but odd number tRCD breaks calculation
Main issue is that tWR can't be odd, even if tRTP can and we can somehow work to get tRP be an exact even number
Sit on it today along time ,, but unless tWR can be an odd number ~ there is no way how it can work with tRCD 15
Always end up with tRP as .5 value
Same for tCL 15, doesn't work without having another odd number ~ which must be tWR.

Well anyways , try tRCD_WR 9 - for tRP at least to be correct
tRCD_RD 15 with tRCD_WR 8 pushes required tRP as 11.5
tRP 12 should work, but then that odd _WR breaks tRC math
If one little thing is off, it needs a whole redesign

Yeah, can't use odd tWR or tCWL>12. I'll try 2T. Problem is that forces GDM on.

I need to buy a better memory kit though this isn't half bad for $120. Perhaps I'll get that sexy F4-4400C19D-16GTZKK if the price makes sense vs Viper steel 4400.

 

[rares495]

Yeah, can't use odd tWR or tCWL>12. I'll try 2T. Problem is that forces GDM on.

I need to buy a better memory kit though this isn't half bad for $120. Perhaps that I'll get that sexy F4-4400C19D-16GTZKK if the price makes sense vs Viper steel 4400.

Nevermind. It doesn't force GDM on. Latency decreased a bit, 62.1 vs 62.2 though that might be run to run variance.

 

[nick name]

I have to browse through the documents again. It was on an Samsung JEDEC sheet
GDM changes:
tCWL=tCL
uses tCKE
allows tRTP only be an even number
and i'm a bit unsure still on the first 4 primaries till tRAS (rounding up)

But i'm pretty sure on tCL=tCWL , usually ZenTimings should've detected that
Maybe upgrade to 1.1.0 and recheck
One thing that also is awkward, is your PowerDown mode
Normal one for 4 dimms, Alternative is for 2 dimms
Not going to judge on SD, DD's as people still have random results with these

Aida64 latency is a bit high tho
I'd suspect sub 61ns
GDM off 2T would work too, just tCWL 14 would break one ruleset
it would result in tRC 40
While it might pass with tRC -2 for Single Rank, it's not "perfect" yet with tCWL 14 :/

A2 Vipers with a lot of ClkDrvStrength should get GDM disabled :thinking:
I mean you pretty much have a new stable set, soo you can test what it needs to get GDM off
To what i remember GDM adds exactly 2ns , you might be sub 61ns already ~ IF you get 1T to work
2T should be about equal to 1T when no autocorrection happens

This all assumes i'm right with GDM, but i'm pretty sure it did.
We'll figure it out later, tCWL 11 would break it for sure and tCWL 16 too
tCWL 14 might be just borderline fine ~ although it should be 12 without GDM

Oh, I'm not using Vipers. I'm using the TridentZ 4400C19 kit.

And the white papers say tCWL has to beven not that it gets set to tCL.

Besides if tCWL got set to tCL when using GDM then I wouldn't need to raise tRDWR to 10 when I lower tCWL to 12.

 

[Veii]

Nevermind. It doesn't force GDM on. Latency decreased a bit, 62.1 vs 62.2 though that might be run to run variance.

Eehm
Compare this to your 61ns picture
especially the Cache :thinking:
here Read and Copy are better by a big chunk
Perfect set would put Write to 30400MB/s. In perfect scenarios we would also hit 60800MB/s on Read, but the architecture here is the issue.

 

[rares495]

Eehm
Compare this to your 61ns picture
especially the Cache :thinking:
here Read and Copy are better by a big chunk
Perfect set would put Write to 30400MB/s. In perfect scenarios we would also hit 60800MB/s on Read, but the architecture here is the issue.

61ns is dual core. That fks lots of things except for latency cuz write/read bandwidth is influenced by the CPU cores/frequency. Can't really compare. Perhaps I'll try to run it on 8 cores at a lower frequency like 4650 or something.

 

[Veii]

Oh, I'm not using Vipers. I'm using the TridentZ 4400C19 kit.
And the white papers say tCWL has to be even not that it gets set to tCL.
Besides if tCWL got set to tCL when using GDM then I wouldn't need to raise tRDWR to 10 when I lower tCWL to 12.

Last point makes sense, hmmm
It should break with tCWL 14 anyways.
I wonder :thinking:

But even tWR bothers me . . .
I can't get tCL 15, tRCD 15 sets to work that way :wheee:

 

[nick name]

Yeah, can't use odd tWR or tCWL>12. I'll try 2T. Problem is that forces GDM on.

I need to buy a better memory kit though this isn't half bad for $120. Perhaps I'll get that sexy F4-4400C19D-16GTZKK if the price makes sense vs Viper steel 4400.

I can only recall seeing one person with a Viper kit that can run 3800 14-14-14-14 and at 1T GDM off too. Pretty much every 4400C19 Viper kit I can remember seeing performed the same as a 3600C15 kit.

And the TridentZ 4400C19 is $20 cheaper than what I paid a month ago. And folks are saying prices are going to continue to drop.

 

[Veii]

61ns is dual core. That fks lots of things except for latency cuz write/read bandwidth is influenced by the CPU cores/frequency. Can't really compare. Perhaps I'll try to run it on 8 cores at a lower frequency like 4650 or something.

You got me haha
Nah it's fine
Soon 1usmus should release his ClockTuner-Ryzen tool, then you can play with it
CCX Delta difference on 6c CCX/12c is 100mV , on 8c CCX/16c it should be 75mV

For now i was just curious if that set works, especially that low tRFC which it requires
Got my information
Will finish tomorrow more sets, which are easier to run
but i have no idea how to work with tCL 15, tRCD 15
EDIT:
I might push one more test round with tCWL 10 out there
We'll see if it's necessary

 

[nick name]

The Read bandwidth in the 1T the screenshot is higher than the average. The average of several runs is closer to 61300 MB/s.

 

[nick name]

Oh and I get a lower latency when I use a static OC of 45 CCD1 and 43.5 CCD2. It drops below 62ns.

 

[rares495]

Oh and I get a lower latency when I use a static OC of 45 CCD1 and 43.5 CCD2. It drops below 62ns.

Yup. This is also a CPU frequency "contest".

 

[Veii]

The Read bandwidth in the 1T the screenshot is higher than the average. The average of several runs is closer to 61300 MB/s.

I'm strongly confused. How can you hit 61800MB/s without BLCK OC when the maximum is 60800MB/s :thinking:
Are these Dual Rank by any chance ?

Oh and I get a lower latency when I use a static OC of 45 CCD1 and 43.5 CCD2. It drops below 62ns.

Yep you get some boost on a static OC

 

[nick name]

I'm strongly confused. How can you hit 61800MB/s without BLCK OC when the maximum is 60800MB/s :thinking:
Are these Dual Rank by any chance ?
Yep you get some boost on a static OC

No BCLK and not dual-rank but I am using BankGroupSwap. I grabbed a screen before I starting re-running the Write test and it never hit that number again and almost every run was above 61000 MB/s with maybe two runs at 60800 MB/s but I'd say an average of all at close to 61300 MB/s.

I enable BankGroupSwap for the extra bandwidth and I don't care about the few extra FPS in games I play.

Edit:
Just did more runs after several reboots and I haven't seen numbers as high as I did. All much more close together around 60800 MB/s ~ 61100 MB/s.

 

[nick name]

Yup. This is also a CPU frequency "contest".

You know it's funny. The latency doesn't drop until I get to 45 on CCD1. If I use 44.75 it's higher than 63ns and then once I get to 45 on CCD1 it drops below 62ns. I know we're talking about 1ns, but it's funny.

 

[Veii]

No BCLK and not dual-rank but I am using BankGroupSwap. I grabbed a screen before I starting re-running the Write test and it never hit that number again and almost every run was above 61000 MB/s with maybe two runs at 60800 MB/s but I'd say an average of all at close to 61300 MB/s.

I enable BankGroupSwap for the extra bandwidth and I don't care about the few extra FPS in games I play.

Edit:
Just did more runs after several reboots and I haven't seen numbers as high as I did. All much more close together around 60800 MB/s ~ 61100 MB/s.

mm~
To what i learned, is that Alt should be used for 2 dimms and Normal one for 4 dimms

You can try to drop tRDWR to 9 and tWRRD up to 3.
It should still be +2 of tRCD_RD/2=7, soo i think it can work
Well, i might make another even more extreme set for you to try tmr. But this current set of timings should be scaleable up in MT/s without breaking

You know it's funny. The latency doesn't drop until I get to 45 on CCD1. If I use 44.75 it's higher than 63ns and then once I get to 45 on CCD1 it drops below 62ns. I know we're talking about 1ns, but it's funny.

This is likely because of the CCX delta
There was always something awkward in per CCX OC, noticed around March.
Gladly 1usmus seems like hit the same research pattern on his ClockTunerRyzen Tool ~ soo this anomaly is pretty much a confirmed thing
Different core size of CCX scale with a different delta between them
There are good and bad CCD's but between CCX, there is a frequency delta ~ like an own characteristic of it

6core CCX liked 75-100mhz in between, while for the with equally bad CCX "founders" 3600 ~ 100Mhz delta worked better and it let me push it beyond 4.2
Else it was pretty much was limited to 4175, hit 4275 @ 1.25v AVX after figuring out the CCX Delta in between
This likely could be your case, a tiny instability between them ~ or let's just say a "sync" issue
try 150mhz between them with 75 between CCDs, else just 50 between CCDs and 100 between CCX

 

[nick name]

mm~
To what i learned, is that Alt should be used for 2 dimms and Normal one for 4 dimms

You can try to drop tRDWR to 9 and tWRRD up to 3.
It should still be +2 of tRCD_RD/2=7, soo i think it can work
Well, i might make another even more extreme set for you to try tmr. But this current set of timings should be scaleable up in MT/s without breaking

This is likely because of the CCX delta
There was always something awkward in per CCX OC, noticed around March.
Gladly 1usmus seems like hit the same research pattern on his ClockTunerRyzen Tool ~ soo this anomaly is pretty much a confirmed thing
Different core size of CCX scale with a different delta between them
There are good and bad CCD's but between CCX, there is a frequency delta ~ like an own characteristic of it

6core CCX liked 75-100mhz in between, while for the with equally bad CCX "founders" 3600 ~ 100Mhz delta worked better and it let me push it beyond 4.2
Else it was pretty much was limited to 4175, hit 4275 @ 1.25v AVX after figuring out the CCX Delta in between
This likely could be your case, a tiny instability between them ~ or let's just say a "sync" issue
try 150mhz between them with 75 between CCDs, else just 50 between CCDs and 100 between CCX

When running dual-rank I can't seem to use BankGroupSwap. I haven't tried thoroughly enough to say it's impossible for me though. Or maybe that is a thing.

Where I got my info is from that AMD write up a while back.

https://community.amd.com/community...community/gaming/blog/2017/07/14/memory-oc-showdown-frequency-vs-memory-timings

And I can't set tRDWR less than 10 with tCWL at 12. I've tried. Sad face.

 

[pipes]

With setting in screenshot can boot but Stick at BIOS tuf screen

Inviato dal mio MI 9 utilizzando Tapatalk

 

[pipes]

tuf and asus are done with me, last time I buy asus cards ...

Inviato dal mio MI 9 utilizzando Tapatalk