Overclock.net banner

6 GHz SRAM Memory Introduced By IBM

1.7K views 25 replies 15 participants last post by  uberjon  
#1 ·
Image


Quote:


A new state of the art SRAM chipset is responsible for this achievement. The 6 GHz speed is almost twice the speed of today's SRAMs. SRAM's usage is to hold frequently accessed data used by the processor. The faster the access, the faster the data transfer from SRAM to CPU.

Its been a long time effort for researchers to be able to overcome the process variability, especially variations that occur when a device is used in conjunction with other devices in an array making it possible for data to be lost. IBM researchers have come up with a novel hardware-based solution in order to reduce or even correct all problems problems and improve performance for various applications by using 8T SRAM arrays.

Source: FudZilla
 
#2 ·
"Dude, I overclocked my L2 cache by 400MHz!"
 
#4 ·
Nice.

But whatever could they mean by almost twice the speed of current available SRAM?

(BTW - Anyone heard of RAM on GPU's being OC'd anywhere close to GHZ?)

Unless they mean.. PERFORMANCE wise.. and not just actual MHZ. But even so, if its as effective in ratio to current SRAM, then 6GHZ should make it FAR faster..
not just 2 times as...

Perhaps I'm thiking of something else
Image
 
#6 ·
Quote:


Originally Posted by Grim
View Post

Nice.

But whatever could they mean by almost twice the speed of current available SRAM?

Anyone heard of RAM on GPU's being 3 GHZ?

Unless they mean.. PERFORMANCE wise.. and not just actual MHZ. But even so, if its as effective in ratio to current SRAM, then 6GHZ should make it FAR faster..
not just 2 times as...

Perhaps I'm thiking of something else
Image


Yup, you are thinking of something else. GPU's and main memory are DRAM. DRAM needs to be refreshed constantly. This is SRAM which doesn't need to be refreshed.

Quote:


Originally Posted by bl!nk
View Post

Isn't L1 your FSB? Not sure though.

Not even close. One is memory and the other is a bus.
 
#10 ·
No.... cache speed and FSB have nothing to do with each other. Main memory RAM and FSB are related.

L1 is super fast/expensive memory. L2 is very fast memory. Both are intergrated into the CPU. Then there is main memory or "RAM".
 
#11 ·
Quote:


Originally Posted by DuckieHo
View Post

No.... cache speed and FSB have nothing to do with each other. Main memory RAM and FSB are related.

L1 is super fast/expensive memory. L2 is very fast memory. Both are intergrated into the CPU. Then there is main memory or "RAM".

Are you positive? I could have sworn I read somewhere on here that L1 speed=CPU speed, and FSB speed=L2 speed. *goes a searching*
 
#14 ·
Quote:


Originally Posted by pauldovi
View Post

(Version 1.10)

The FSB is the speed of the L2 (level 2) cache. L2 Cache is largest chunk (desktop CPUs only) of memory on the CPU. This is what directly communicates with your system memory. From the L2 cache the data is moved to the much smaller, but also much faster L1 (level 1) cache. CPU speed is normally referred to as the speed of the L1 cache.

In order to determine your CPU speed, you multiply the FSB by its multiplier.

For example:

266.66Mhz FSB x 9 = 2.40Ghz

The 2.40Ghz is the speed of the L1 cache.




From pauldovi's overclocking post.
 
#15 ·
I think they still seem to think Mhz is everything. Take a 2.0 Ghz core2 and compare it to a P4 EE at 3.6( or did they run at 3.4?) You can still say the same thing about memory, I know it is new and all but in most cases ddr3 is slower than ddr2, which is why they're making them so fast with better production, but not better design?? Hell by the time it matters though we probably will have moved onto some new wave of the future technology for RAM.
 
#16 ·
Quote:


Originally Posted by bl!nk
View Post

From pauldovi's overclocking post.

Hmmm... does this apply to K8 architecture since they don't use a FSB?
 
#18 ·
Quote:


Originally Posted by Whodie
View Post

I think what pauldovi was trying to say is the L2 access time is dependant on your FSB.

In other words, the higher the FSB, the faster data arrives and can be processed through the L2.

L2 memory itself I doubt is classified in mhz terms, it would seem more logical for it to be classified in nano second access times.


Hmm, makes sense.
 
#19 ·
Quote:

Originally Posted by Whodie View Post
I think what pauldovi was trying to say is the L2 access time is dependant on your FSB.

In other words, the higher the FSB, the faster data arrives and can be processed through the L2.

L2 memory itself I doubt is classified in mhz terms, it would seem more logical for it to be classified in nano second access times.
Well.... nanosecound access time = 1/MHz
Image
 
#20 ·
L1 is the closest cache to the core. L2 is second closest and largest on current chips. L3 is AMD quad core only (i think maybe some xeons or C2Q but im not sure) and is used for all chips, it is the largest on the die and furthest from the core(s.) L1 is fastest since it is all about latency and the cache controller has less to control. L2 is second and L3 third int he same manners.

The above was for those asking questions about L caches.
 
#21 ·
Quote:

Originally Posted by Licht View Post
L1 is the closest cache to the core. L2 is second closest and largest on current chips. L3 is AMD quad core only (i think maybe some xeons or C2Q but im not sure) and is used for all chips, it is the largest on the die and furthest from the core(s.) L1 is fastest since it is all about latency and the cache controller has less to control. L2 is second and L3 third int he same manners.

The above was for those asking questions about L caches.
An old Intel chip had L3 as well.
Image
 
#22 ·
Building on what Licht said - L1 and L2 cache run at core speed. The difference being that L1 is very close to the core and L2 is farther away from the core so L2 will have a higher latency. L3 cache resides even farther away than L2 and so will have even higher latencies than L2. L3 cache has been used before in previous P4 Extreme chips and are used in Itanium chips. AMD is also using L3 in their quad-core chip but since that has yet to be released, we won't know how their L3 performs.

The FSB is the bus that the chip uses to communicate with the Northbridge and runs much much slower than the core speed, which is why the cache is there in the first place to reduce the bottleneck of the slow data transfer.

The potential problem with this stuff is that it has a higher transistor count per SRAM cell than the normal SRAM cells. The SRAM cells are 6T SRAM arrays so that each SRAM cell uses 6 transistors whereas these are 8 transistors per cell, representing a third more resources. Thus, 6MBs of this stuff will use the same number of transistors as 8MBs of the regular transistors. So if this is carried over to CPU use, we'll either see much smaller amounts of this stuff or the chips will be a LOT more expensive since the die size will be much bigger.

To give you a rough idea of latencies:

Register's = ~0.5-2.0ns
Level 1 Cache = ~1.0-4.0ns
Level 2 Cache = ~5.0-20.0ns
Level 3 Cache = ~20.0-30.0ns
Main Memory = 35.0-50.0ns
Hard Drive = 5.0-10.0ms

Taken from a post by The_Manual
 
  • Rep+
Reactions: Licht
#23 ·
Quote:

Originally Posted by Whodie View Post
I think what pauldovi was trying to say is the L2 access time is dependant on your FSB.
Technically pauldovi is wrong. L1 runs at 1:1 with your CPU speed in modern CPUs, but it didn't always.

Grabbing numbers from the air, I seem to recall 1:1 and 1:40. 1:1 is L1, 1:40 is L3(snagged that from an article about why a specific server board sucked; it had on-motherboard L3 that was slower than PC1600 memory).
Image
AMD's Quad-core L3 is much much faster, since it's still located on the die.

Sometime around when P3's were out, Intel made a CPU that ran the L1 at a ratio, in an attempt to let the rest of the CPU reach a much higher speed.
 
#25 ·
Quote:


Originally Posted by Licht
View Post

How effective was it?

It had horrible performance per ghz, sometimes falling behind the ~450mhz P3's. Can't quite recall which, but the ratio was either 1:2 or 1:2.5

I think it might've been 1:2.5, which means often it skipped even more clocks.

But that was the beginning of the 'More clockspeed!' era, so for marketing at the time, it made sense.
 
#26 ·
Quote:


Originally Posted by Cheetos316
View Post

Building on what Licht said - L1 and L2 cache run at core speed. The difference being that L1 is very close to the core and L2 is farther away from the core so L2 will have a higher latency. L3 cache resides even farther away than L2 and so will have even higher latencies than L2. L3 cache has been used before in previous P4 Extreme chips and are used in Itanium chips. AMD is also using L3 in their quad-core chip but since that has yet to be released, we won't know how their L3 performs.

The FSB is the bus that the chip uses to communicate with the Northbridge and runs much much slower than the core speed, which is why the cache is there in the first place to reduce the bottleneck of the slow data transfer.

The potential problem with this stuff is that it has a higher transistor count per SRAM cell than the normal SRAM cells. The SRAM cells are 6T SRAM arrays so that each SRAM cell uses 6 transistors whereas these are 8 transistors per cell, representing a third more resources. Thus, 6MBs of this stuff will use the same number of transistors as 8MBs of the regular transistors. So if this is carried over to CPU use, we'll either see much smaller amounts of this stuff or the chips will be a LOT more expensive since the die size will be much bigger.

To give you a rough idea of latencies:

Register's = ~0.5-2.0ns
Level 1 Cache = ~1.0-4.0ns
Level 2 Cache = ~5.0-20.0ns
Level 3 Cache = ~20.0-30.0ns
Main Memory = 35.0-50.0ns
Hard Drive = 5.0-10.0ms

Taken from a post by The_Manual

actually if i recall. the latencies have nothing to do with the distance from the core (almost) but the fact that.

the cpu core looks first at l1 for data
then l2
then l3 (if it exists)
then ram.

but if the data is found in l1 it doesnt have to go clear threw l2-ram to find it. causing it to be able to process it faster!

im sure other factors apply i.e. the speed of that cache/etc