Building on what Licht said - L1 and L2 cache run at core speed. The difference being that L1 is very close to the core and L2 is farther away from the core so L2 will have a higher latency. L3 cache resides even farther away than L2 and so will have even higher latencies than L2. L3 cache has been used before in previous P4 Extreme chips and are used in Itanium chips. AMD is also using L3 in their quad-core chip but since that has yet to be released, we won't know how their L3 performs.
The FSB is the bus that the chip uses to communicate with the Northbridge and runs much much slower than the core speed, which is why the cache is there in the first place to reduce the bottleneck of the slow data transfer.
The potential problem with this stuff is that it has a higher transistor count per SRAM cell than the normal SRAM cells. The SRAM cells are 6T SRAM arrays so that each SRAM cell uses 6 transistors whereas these are 8 transistors per cell, representing a third more resources. Thus, 6MBs of this stuff will use the same number of transistors as 8MBs of the regular transistors. So if this is carried over to CPU use, we'll either see much smaller amounts of this stuff or the chips will be a LOT more expensive since the die size will be much bigger.
To give you a rough idea of latencies:
Register's = ~0.5-2.0ns
Level 1 Cache = ~1.0-4.0ns
Level 2 Cache = ~5.0-20.0ns
Level 3 Cache = ~20.0-30.0ns
Main Memory = 35.0-50.0ns
Hard Drive = 5.0-10.0ms
Taken from a
post by The_Manual
