[wuttman]

Any suggestions for further timings / latency improvement?

tFAW

 

[gabian]

Hi

I spend time to make this stable. With 2x16GB Gskill 3800C14. I try to tight everything to the minimum.

Is there anything useless in my timings ? (like too tight for being usefull)

On TM5 ram is heating at 49c, Karhu and TM5 are OK, but may be too hot for daily ?

 

[TimeDrapery]

Spoiler

@TimeDrapery

Allow me to answer for him. Probably those settings are Asrock boards related only.

Thanks for the reply!

The settings @Veii is referencing are talked about in some of AMD's EPYC tuning guides found on their public site

I always assumed they're exposed in AMD CBS because of the requirements to make the BIOS settings found in there... Common 😂😂😂😂😂

It would be nice to know what these options actually impact on CPUs that aren't EPYC...

You listening, AMD? If they impact nothing on Ryzen, why expose them? Lazy mobo vendors?

 

[TimeDrapery]

Spoiler

Pretty much the same thing i tell everyone
Have a stable main set, before starting

First focus on weakening RTT_PARK, to something lower
Soo dimms heat up less / you can then use more voltage to push things / and the PCB has less strain
Also helps you get procODT a bit lower

Then after that's done, increase close to everything
tRRD, tWTR, tWR, tRTP
and try to get these flat primaries stable
AFTER you are already done with pushing frequency up ~ with a weaker 16-16-16 set

It can happen that you need to losen tRFC a bit, as tighter primaries will demand more voltage and so cause more strain
It's expected that the PCB won't be thaat stable (the main reason you should weaken your powering in the first place to lower heat and strain a bit, before continuing)
Later you can at any time tighten down tWR, tRTP & tRFC without issues
But bad primaries will be masked by tens of thousand possible issues with powering or tertiary timings ~ soo focus on your primaries at the very end staring again with a "weaker" but tested secondary's baseline

Same thing, tRCDRD 14, go go go
I can do it with weak A0 PCBs - so you can do too
Before all that, get that GDM away and run 2T , soo your odd i think BZ ? timings patterns make sense. They don't on GDM on

Many dimms generally need increased tWR and added tWRRD delay
Later one you got covered
They also want tRDWR = tRCDavg /2 (+1)
+2 for dual rank , +1 & tWRRD for many dimm single rank

You mask issues with tRC, it's 48 for you but you run +2 there
Get it stable at 48, and if it isn't possible, you have other timeouts in the chain

You run tRRD_L as 8,
Up tWTR as 5-14 instead of 4-14
I think your 1-4-4-1-7-7 is the "masking" issue here
move down to 1-4-4-1-6-6 for many dimms or dual rank scenarios
1-5-5-1-7-7 can work as it's still single rank, but 1-4-4-1-6-6 although slower is a bit better here

Also be sure to binn your dimms individually, and put the weakest set on the main (master) position (slot 2 & 4)
But the weaker ones to the (slave) set , 1 & 3

tRFC mini works for 8gb dimms, but it looks without checking correct
Be sure to hold tRFC 2 & 4 correctly ~ for whatever tRFC you pick

Didn't investigate why it didn't work. But the XOC CornerJack got it posted & running on 2167 FCLK

Soo it surely is a possible thing - i just didn't go further than 2133, when 2133 had 8:1 or even 16:1 mode bugging out and autocorrecting up to 210ns
Will give it another shot or maybe get a better DIMM-PCB and then try again. Am already beyond the limits of these cute A0s

In 1 month when ASRock's "single" bios engineer get's it together

You still have a bit of playroom , and vdroop on LLC - for purely CTR usage

Spoiler: CTR Optimum

View attachment 2486372

You can achieve this by adding negative CO & balancing it with positive vcore
Keep in mind, on the "not so new" versions, adding any vcore offset ~ will bug it out and run 1.55v through it. Soo be sure to test it or don't use any vcore offset at all
Too big negative CO, will fake the results and cause actual crashes ~ same for too big vcore offset will push too much voltage through the chip ~ as it goes as "additive voltage"

I started with 1072 Silver Sample ~ don't have such a good unit
Also use the high-perf powerplan for now and disable DF states , if you want to use CTR

Up to you, if you use strong RTT_PARK, then you should use less VDIMM ~ generally speaking
If you have thermal headroom and get RTTs weaker (which i think still is the better option & worth it fixing the powering)
You can push higher voltage and soo lower timings

Update ZenTimings, unsure if these are Dual Rank 4 dimms or 2x 32gb
You want to increase ClkDrvStr higher to 60-120 (for dual rank) or 40-60 for 4x16gb "single rank"
something like 40-20-40-20, 60-20-40-20, or trying out 60-20-20-20 with SETUP Timings of 2-2-12

I think your result is already good, just that tRCDRD 15 is bothering
Likely want to increase tRRD, tWTR, tWR & tRTP till 14-14-14-14 is stable
Else just lower tRTP to 6, or run a higher tRFC of 294 @ tWR 14, tRTP 7

Really depends, usually you want to run SD, DD's as 1-4-4-1-6-6 for "many dimms or dual rank"
But your result is already good ~ except the high procODT which limits you
Oh you surely want to run cLDO_VDDP to 900mV & lower CPU VDDP (VDDP in tweakers paradise) to 900mV , 880mV or 860mV (up to what your sample allows you)
cLDO_VDDP shouldn't be higher than 900mV
Maaybe 920-960-1000-1080
SOC is GET, the rest is SET
But i think you are perfectly fine with 900mV cLDO_VDDP

Take a read at

AMD max overclocking voltage

Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...

www.overclock.net

and scroll further down
There is a low power set. The voltages should work for you
but CPU VDDP is what you surely want to lower to the lowest possible ~ under Tweakers Paradise (VDDP)
The rest is cLDO_VDDP for PHY

Thanks for the reply!

I'll set GDM to Disabled and Command Rate to 2T, loosen subs, and do my best to get a flat 14 timing set running stable...

What advantages does 2T offer versus 1T/GDM Enabled? Less autocorrection activity and, thusly, better performance?

 

[wuttman]

Lower\weaker park

First focus on weakening RTT_PARK, to something lower

Forgive the brainlet, weaker means lower divider or lower value itself?

 

[mongoled]

Lower\weaker park

Forgive the brainlet, weaker means lower divider or lower value itself?

RZQ/1 is "stronger" than RZQ/3

Using a "stronger" RttPark value with vDIMM > 1.48v can lead to dimm death especially if they are A0 pcb's ....

So its preferable to use a weaker RttPark value when adding more vDIMM voltage

 

[Veii]

Great post, but please amend this as you say "weakest" twice.

oops, fixed
Thank you~

Is it mean, that i need to "find" correct voltage?

It means, that every board has split SOC Mosfets and so a Loadline for their controller
What is read out under load matters ~ at least matters for the "minimum" rating i tried to push out as overview couple of months ago

Likely a better CPU can do better, but i think it's a decent orientation point
Lower might or might not post, but the written values are one which worked for sure

@Veii
I would like your help.
I am trying to lower the L3 latency, but without success.
Any suggestion?
View attachment 2486408

Tried EDC 400 ?
And both cTDP and Package power limit to 400W inside AMD CBS - NBIO - SMU ?
Else i am not sure i can help you with finetuning and working with CurveOptimizer
At least not without sitting together and looking over your shoulder. Something around that idea
No really, no idea how to help you ~ except suggest to use a big negative allcore CO and give it near 40-50mV positive vcore

Also disabling DF states and likely downgrading, as SMU 56.50 killed L3 cache performance , in comparison to 56.44 for example.
1.1.9.0 or 1.2.0.0 where "ok" ~ IF you lift the EDC upwards soo internal limits lift
(it still will follow the FUSE EDC limit, just use more allcore voltage, by the broken nature of how PBO functions since Matisse)

Any suggestions for further timings / latency improvement?

View attachment 2486410

tRDWR down at least one, with added tWRRD of at least value 2 or higher
In the future then getting a flat CL14-14-14 set , or a 3800C15-15-15 set for the beginning

You listening, AMD? If they impact nothing on Ryzen, why expose them? Lazy mobo vendors?

The exact opposite of your writing ~ is my intention
Brands keep locking them down further and further. We have only 10-12% of what can be set
EPYC == AM4
Same IO-Die , same CCDs

What functions there, functions here
I haven't gotten to unlock this bios, and miss ASRocks old charm of proving an unlocked AMD CBS & PBS
MSI, Gigabytee and Asus users have twice the options i can play with & they do change things
Inter-core things are not easy to track ~ same as Ram Performance -> IPC bump, is not easy

 

[wuttman]

& lower CPU VDDP (VDDP in tweakers paradise) to 900mV , 880mV or 860mV (up to what your sample allows you)

MSI bios doesn't have it?

 

[RonLazer]

MSI bios doesn't have it?

No, even on the Unify-X.

 

[TimeDrapery]

Spoiler

...

Also disabling DF states and likely downgrading, as SMU 56.50 killed L3 cache performance , in comparison to 56.44 for example.
1.1.9.0 or 1.2.0.0 where "ok" ~ IF you lift the EDC upwards soo internal limits lift
(it still will follow the FUSE EDC limit, just use more allcore voltage, by the broken nature of how PBO functions since Matisse)

...

The exact opposite of your writing ~ is my intention
Brands keep locking them down further and further. We have only 10-12% of what can be set
EPYC == AM4
Same IO-Die , same CCDs

What functions there, functions here
I haven't gotten to unlock this bios, and miss ASRocks old charm of proving an unlocked AMD CBS & PBS
MSI, Gigabytee and Asus users have twice the options i can play with & they do change things
Inter-core things are not easy to track ~ same as Ram Performance -> IPC bump, is not easy

I believe ya, you are doing great work and I appreciate you!

I figured we're missing quite a bit of options in most publicly available BIOS considering the EPYC and Ryzen similarities... That's very disappointing but it is what it is

Considering the similarities between the CPUs with regards to CBS -> SMU Options one thing I'm wondering is what the cTDP limits are on Ryzen processors

For example, EPYC CPUs have upper and lower limits users can configure their systems within... What would these limits be on Ryzen systems?

 

[T[]RK]

Likely a better CPU can do better, but i think it's a decent orientation point
Lower might or might not post, but the written values are one which worked for sure

I tested (just in case) my current config with TM5 (25 cycles) and it pass without errors. But when i decided to test CB20 - i got crash after few seconds.

And first my guess was that not enough CPU voltage at CLDO_VDDP, VDDG CCD\IOD, so i switched from 860-900-940 to 900-940-980. Since RAM was tested and it pass long test without error. New run of CB20 crashed again, a bit later, but still! I tested RTTs 6\0\7 - no effect. I loaded Default XMP profile and no problem - CB20 pass. So, problem was in RAM, not in CPU and i switched back my voltages. Then i load my Tuned XMP profile again and changed EXACT ONE value - ProcODT 34.3 => 36.9 (one step UP). CB20 Pass. So, now all values are correct. Interesting, that i was able to run 3DMark Time Spy at ProcODT 34.3 and no crash. Only CB20 make high enought load for crash.

 

[Veii]

MSI bios doesn't have it?

No, even on the Unify-X.

They do, all MSI boards have it - it's only hidden from the user
More people need to force the department to "unhide" it inside AMITSE - soo AMIBCP change stticks
or just AMIBCP change it to 900mV - which will 100% work on all CPUs
Lower than 900mV is required for 2100 FCLK stability, but 2100 runs at 900mV too

Considering the similarities between the CPUs with regards to CBS -> SMU Options one thing I'm wondering is what the cTDP limits are on Ryzen processors
For example, EPYC CPUs have upper and lower limits users can configure their systems within... What would these limits be on Ryzen systems?

They should be identical to the PPT limit
I haven't tested if an override there overrides PPT limits ~ like the ECO mode does (Although ECO mode does DPM LCLK slow it down ~ inside infinity fabric)
This thread and discussion with CapFrameX ~ especially this picture

Watch the SiSandra Inner-Core link differences and benchmark result differences

I tested (just in case) my current config with TM5 (25 cycles) and it pass without errors. But when i decided to test CB20 - i got crash after few seconds.

• 3600 - <1060mV
• 3800 - <1075mV

FCLK , is still inside the CPU
Technically a memory crash can be cpu voltage stability
Not only vcore , but also can be vcore

Rule of thumb was +3 steps on 2700X over the lowest AVX2 stable voltage ~ to cover the higher strain of FCLK OC
Determine minimum working voltages with y-cruncher (Key-Combination: 1-7-0 , looping 4 cycles everything = 48min)
Cinebench is a lightweight load in comparison to all AVX2 tests y-cruncher has
OCCT AVX2 Extreme, only ticks the box of "extended linpack test under large dataset ~ making internal heat destabilize voltage splitting of VDDG" == crash or stability issues
Before all that, y-cruncher will tell you with all 9 tests enabled, if anything major is broken to begin with

This also includes CTR "predicted" voltages, which fully break once AVX2 adds own voltage offset ontop of loadline offset
But CTR has something newly interesting soon after 2.1 RC5 or likely "freeby RC6" ~ to combat such
(pushing you to my 5ghz allcore TM5 screeny ~ reposted here)

High SOC will require high procODT
There are minimum and maximum limits with it
High proc allows usage of "less SOC and less VDIMM" but low voltages only work with "low" procODT
Bit of a paradox

 

[shaolin95]

Really depends, usually you want to run SD, DD's as 1-4-4-1-6-6 for "many dimms or dual rank"
But your result is already good ~ except the high procODT which limits you
Oh you surely want to run cLDO_VDDP to 900mV & lower CPU VDDP (VDDP in tweakers paradise) to 900mV , 880mV or 860mV (up to what your sample allows you)
cLDO_VDDP shouldn't be higher than 900mV
Maaybe 920-960-1000-1080
SOC is GET, the rest is SET
But i think you are perfectly fine with 900mV cLDO_VDDP

Take a read at

AMD max overclocking voltage

Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...

www.overclock.net

and scroll further down
There is a low power set. The voltages should work for you
but CPU VDDP is what you surely want to lower to the lowest possible ~ under Tweakers Paradise (VDDP)
The rest is cLDO_VDDP for PHY

First of all THANK YOU for the detailed explanation. Really appreciated
I tried dropping procODT a little but I get reboots even doing the AIDA mem test.
Same thing if I try to do 1-4-4-1-6-6
I am not very clear on the voltages recommendations so I took a photo to share with you of my current settings. And also the newer version of Zen Timings

 

[RonLazer]

They do, all MSI boards have it - it's only hidden from the user
More people need to force the department to "unhide" it inside AMITSE - soo AMIBCP change stticks
or just AMIBCP change it to 900mV - which will 100% work on all CPUs
Lower than 900mV is required for 2100 FCLK stability, but 2100 runs at 900mV too

Can I just edit that value in AMIBCP and save the BIOS file again and it will work? Do you have any guides on this?

 

[SesioN]

tFAW

But isn't the rule for tFAW as follow:

tFAW (tRRDS *4 <= best value <= tRRDS *6

If that's the case, then my tFAW is already maxed out?

tRDWR down at least one, with added tWRRD of at least value 2 or higher
In the future then getting a flat CL14-14-14 set , or a 3800C15-15-15 set for the beginning

Okay thank you, I will see how the RDWR and WRRD changes affect stability and results. I'll let you know.

I don't think that hitting 14-14-14 is possible. As soon as I change tRCDRD to 14 I start getting errors on testing.
So unless it's possible and worth to relax some others settings that might help with this I can't do it.

(And my memory is quite hot, I'm like 52-53C at full load and that's at 1.48V)

 

[GribblyStick]

@Veii

Ok, let me get this straight:
In terms of CPU we should try the power settings you shared earlier, plus:

Uncore OC off (don' remember where. In Advanced/AMD CBS/?)

Advanced/AMD CBS/NBIO Common Options/SMU Commen Options
DF C-States off disabled
cTDP Control -> 400
Package Power Limit -> 400
APBDIS disabled
CCLK DPM = 0 (Efficiency mode En 0 is performance optimization)
NBIO DPM options are there but no idea what to set.

Advanced/AMD CBS/CPU Common Options
global C-States enabled

Advanced/AMD Overclocking/Precision Boost Overdrive
PBO limits manual or motherboard limit?
if manual EPC 400, TDC90, PPT also 400?
There is also the fmax enhancer option in the extreme tweaker menu, not clear to me whether that should be on or off.
Max boost set to 200, seems better to lower all core negative offset than to lower the max boost?

Then for CO is this about right?
-30 all core would be considered very good
-15 good
-5 to 10 would be more realistic

offset on the main menu then +0,03 or lower to match the negative CO?
And then run TM5 to confirm the effective and target clock are identical.
And check y-cruncher/cinebench/CTR/games/etc for stability.
Then CPU VDDP in Tweaker menu as low as possible( to test via benchmarking)

Also, do you have on estimation on safe relations for RTT_PARK/ProcODT/VDIMM/CAD resistances yet?
IIRC you went all the way up to 1,7. So Past VDIMM 1,5 you want at least RTT_PARK/3?
For 1,7 I would then guess you need at least RTT_PARK/6 or even 7.
I guess it's not that simple because I am pretty sure I already had 1,5 with RTT_PARK even OFF.
Also depends on the particular PCB. I understand you want weaker RTTs to go higher in VDIMM in order to get a higher IC.
It's not so clear to me where to draw the line in actual numbers.

 

[Ramad]

Can I just edit that value in AMIBCP and save the BIOS file again and it will work? Do you have any guides on this?

CPU VDDP on MSI motherboards can't be controlled by the user. If you mod the BIOS to show the option, the motherboard does not understand or display the value correctly. There is also no read/probe for this voltage rail under Hardware Monitor. The default value is 900mV or 950mV which works fine for ZEN+ and up, it was useful to set this voltage down to 855mV on ZEN (first Ryzen) in the beginning but had no effect on later AGESA releases (that is back in 2017/2018).

 

[SesioN]

View attachment 2486455

Isn't tRFC suppose to be X times of tRC? so either 252 or 294 for you.

 

[SesioN]

tRDWR down at least one, with added tWRRD of at least value 2 or higher
In the future then getting a flat CL14-14-14 set , or a 3800C15-15-15 set for the beginning

So I tried lowering tRDWR by 1 while increasing tWRRD by 2 or even 4. Sadly that resulted in a no boot situation where a CMOS clear was needed.

 

[craxton]

@Veii apologies to tag as i literally see your swamped with tags/questions daily,

but i tried 2033fclk 1:1 mode, and well..

anyhow, my Question is "does this look correct"? no errors from any tests at all.
but, around two months ago something was mentioned that i have some error correction happening somewhere,
while i was away from my pc (around 9 days away from it) and i cant find this post. ill wait for your response.

just let me know IF you dont mind to look over this. (yes best score ive gotten, C/O -15 with +60mv offset)
pc will crash or do random things while anything less than 60mv, core voltage in hwinfo never goes over 1.41.