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AMD Hynix DDR5 Overclocking Guide

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#521 · (Edited by Moderator)
Updated post 513, edited voltage sync text order, instead of as found in ASUS section of UEFI, to AMD section of UEFI. In spoiler added link to screenshots of voltages within AMD Overclocking and AFAIK these help strings are dictated by AMD.

* edit *

Reading Shamino's am5oc capability.docx out of c9_ocpak_0327, highlighted is voltages VDD = VDDQ = VDDIO. (The OCTool in ZIP has been superseded, use with caution/not at all, ZIPs from OP here)

Text Screenshot Number Font Software

* edit 2 *

tRCD within AMD Oveclocking menu allows separate value for WR RD, value is entered as hexadecimal.

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#523 ·
@kyton

Seems about right to me.

tREFI has quite a significant effect, original setup compared to Buildzoid's timings you weren't going to gain much due to just that IMO.

You could increase FCLK, that should improve some aspects of result, but don't expect big gains.

I'd opt to lower SOC voltage. I don't think you need 1.25V for that RAM setup. SOC is a part of CPU power limits, so in a benchmark related to CPU frequency you may see a loss in performance running high SOC. I have seen this with my 9600X, but that does have lower stock power limits than 9800X3D.

VDDP seems high also for the RAM setup in use.

Maybe you have been comparing your results to where "Core tunings Configuration for gaming" has been set to "Legacy", thus leads to improved results in AIDA64.

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#524 ·
gupstergv2.0 said:
@kyton

Seems about right to me.

tREFI has quite a significant effect, original setup compared to Buildzoid's timings you weren't going to gain much due to just that IMO.

You could increase FCLK, that should improve some aspects of result, but don't expect big gains.

I'd opt to lower SOC voltage. I don't think you need 1.25V for that RAM setup. SOC is a part of CPU power limits, so in a benchmark related to CPU frequency you may see a loss in performance running high SOC. I have seen this with my 9600X, but that does have lower stock power limits than 9800X3D.

VDDP seems high also for the RAM setup in use.

Maybe you have been comparing your results to where "Core tunings Configuration for gaming" has been set to "Legacy", thus leads to improved results in AIDA64.
Click to expand...
Core tunings Configuration for gaming i have left on Auto. Otherwise PC has been pretty stable. Curve Optimizer is set at -30
 
#525 ·
#530 ·
One thing I find missing in memory threads is information highlighting what we set in BIOS as timings is. I do not understand all timings or all aspects.

The number we set in BIOS for DRAM timings is number of clock cycles or ticks (except tREFI). The number of clock cycles/ticks is a time duration. What this time duration (clock cycles or ticks) will be as nanoseconds (ns) is based on memory clock. CL30 @ 6400MT/s is not the same ns as CL30 @ 6000MT/s, entering any DRAM timing in this calculator will give the ns for that timing parameter.

In post 513 spoiler DDR5 tuning has timing parameters and how we may set them. Sometimes the lowest setting may not be optimal for all use cases.

In below screenshot is ~165MB/s test speed in Kahru, I had seen in a looser setup ~168MB/s.

Font Software Number Technology Screenshot

I then back tracked on settings. I adjusted tWTRS to 6, still ~165MB/s, then tried tWTRS to 8, still ~165MB/s. So then I set tRC as tRCD+tRP+tRTP+2, which also made tRAS looser, as I was doing tRC-tRP, this resulted in ~168MB/s.

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Then I went back to lowering tWTRS to 6, still ~168MB/s, when I set tWTRS to 4 it dropped to ~166MB/s.

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Benching in AIDA64 the original profile which had ~165MB/s in Kahru vs any that showed ~168MB/s in Kahru was no loss or gain, each compare was within run to run variance.

I also tried the looser setup of tRAS, tRC and tWTRS on a 6200 profile and saw the same thing, too tight on those timings I lost MB/s in Kahru, AIDA64 bench was same regardless.
 
#531 ·
Electronic device Technology Computer hardware Electronics Electronic component
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Anything else I can do here?
tCL wont hit 28 even at 1.5V stable - rather not pump more voltage into my DIMMs - temps top out at 61 C during stress testing. tRFC wont budge beyond 484. Chip will not do 1:1 at 6400.
Hynnix M die 16gbit
 
#532 ·
L36 said:
View attachment 2690399 View attachment 2690400 View attachment 2690402

Anything else I can do here?
tCL wont hit 28 even at 1.5V stable - rather not pump more voltage into my DIMMs - temps top out at 61 C during stress testing. tRFC wont budge beyond 484. Chip will not do 1:1 at 6400.
Hynnix M die 16gbit
Click to expand...
37 or 36 tRCD, 34, 32 or 30 tRP, tRAS is wrong it should be tRP+tRTP, tRTP can probably be 10 or even 8, set tRAS and tRC accordingly, the rest is about as tight as it can be.

If these are SR DIMM's set all tRDRD and tWRWR (except SCL) as 1, they are unused on SR DIMM's. Not necessary but makes it look a bit cleaner and easier to see what is what. Does tPHYRDL match 33/33 on both sticks / channels?
 
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#533 · (Edited)
Imprezzion said:
37 or 36 tRCD, 34, 32 or 30 tRP, tRAS is wrong it should be tRP+tRTP, tRTP can probably be 10 or even 8, set tRAS and tRC accordingly, the rest is about as tight as it can be.

If these are SR DIMM's set all tRDRD and tWRWR (except SCL) as 1, they are unused on SR DIMM's. Not necessary but makes it look a bit cleaner and easier to see what is what. Does tPHYRDL match 33/33 on both sticks / channels?
Click to expand...
Tried that already. I tried tweaking tRCD, tRP. Any values below 37 starts to act up. What frequently happens is my TPM gets reset and mobo hangs when going into BIOS, random system hangs. Not stable at all.

Also FCLK at 2200 1.21 V SOC appears to be stable which is to my surprise. It used to refuse to boot anything over 2167 @ 6400 with same/higher/lover VSOC value.

I feel like this CPU has some kind of black hole when memory is at 6400. Nothing runs right and always unstable. Could be the mobo...

I'll try other tweaks and report back. Thank you.

EDIT
tRTP wont budge beyond 12. 10 will train and boot but with throw error 6 in Test Mem on occasion. Tweaked tRAS and tRC. Latency went down a little bit just with proper tRAS and tRC tweaks.

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Electronic device Technology Computer hardware Electronics Electronic component
 
#534 ·
L36 said:
Tried that already. I tried tweaking tRCD, tRP. Any values below 37 starts to act up. What frequently happens is my TPM gets reset and mobo hangs when going into BIOS, random system hangs. Not stable at all.

Also FCLK at 2200 1.21 V SOC appears to be stable which is to my surprise. It used to refuse to boot anything over 2167 @ 6400 with same/higher/lover VSOC value.

I feel like this CPU has some kind of black hole when memory is at 6400. Nothing runs right and always unstable. Could be the mobo...

I'll try other tweaks and report back. Thank you.

EDIT
tRTP wont budge beyond 12. 10 will train and boot but with throw error 6 in Test Mem on occasion. Tweaked tRAS and tRC. Latency went down a little bit just with proper tRAS and tRC tweaks.

View attachment 2690459 View attachment 2690460
Click to expand...
You could try what happens if you relax tRRD and tFAW a little. I run 6/6/24 at 6400 and 8/8/32 at 8000 as lower is possible but it becomes very sensitive to stability issues and isn't really worth it all that much. And there's rumors tFAW has a floor of 20 on AM5 and thus 16 doesn't do anything even tho I still haven't seen any actual proof of that.
 
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#535 ·
Hello all, I need some help.

I'm struggling with timings for my Gskill 64GB Triden Z Neo RGB M-Die Kit.

The default timings are CL 32-38-38-96

I've been able to get it down to 32-38-38-28. This is at 2133 FCLK

I can't seem to get it to CL 30, or Cl 28. Won't even boot at CL 28. Lots of errors on TM5 On Cl 30, so tons of instablity.

I was able to get my 32gb kit to Cl 28 pretty easily, but these don't seem to want to go below CL30.

Any help here would be greatly appriciated. What do I need to change? Any issues with my voltages?

I'm on a Ryzen 9 7950x3d - AM4 platform.

Attempted to disable GDM seems to introduce a lot of instability FYI.
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#536 ·
Imprezzion said:
You could try what happens if you relax tRRD and tFAW a little. I run 6/6/24 at 6400 and 8/8/32 at 8000 as lower is possible but it becomes very sensitive to stability issues and isn't really worth it all that much. And there's rumors tFAW has a floor of 20 on AM5 and thus 16 doesn't do anything even tho I still haven't seen any actual proof of that.
Click to expand...
so, try wtrs at 5 and tfaw 20?
 
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#537 · (Edited)
Few questions.

1) I've matched VDD and VDDQ but theres lots of discussion about matching/unmatching VDD/VDDQ AND VDDIO and I can't really ever find a answer on what is "good" and what is "bad".

My understanding is:
VDD = helps with timing
VDDQ = helps with frequency

2) I seen lots of people with much lower tRAS and tRC but I can never get them stable if I don't follow these rules:

tRAS = tRP+tRTP
tRC = tRCD + tRAS

Curious if the rules are just infact guidelines and it's possible to lower.
 
#538 · (Edited by Moderator)
@genelecs

Not got all the answers to your questions, don't know if my answer is correct.

Right at the end of this page is section DRAM sub-system.

So we've got memory controller > PHY > DRAM .

Out of Micron DDR5 PDF, page 321.

Text White Number Font Diagram

From what I understand so far.

VDDIO is memory controller voltage.

VDDP is DDR PHY voltage.

VDD is memory chips voltage.

VDDQ is memory chips IO voltage.

Now for the timings.

Translating the DDR5 PDFs into simple explanations I find hard, I can't say I fully understand them. Even with DDR4 when I read them some things sunk in others not.

Before I started posting in this thread, and being new to DDR5 and expecting others would have shared info, I looked at Veii and anta777 past posts.

You will see they discussed timings you have questions on. You can filter the thread down to their posts by clicking the 3 dots on right of a post and picking only show this user. To get context around the post open the post in another tab and you'll see all post in that tab and can go back to other tab to look again just at x persons posts.

In one such post anta777 said tRAS = tRC-tRP , that is JEDEC rule.

I have marked the JEDEC profile section from SPD from one kit I use (the other is also same for this context).

White Number Screenshot Document

You can go tighter, but check if you get a gain in performance or not. Without making my post bigger, we may not see an error when too tight on timings, but if the memory controller is overriding it / error being corrected / we're getting "silent errors", you may not be getting any performance, don't rely on one benchmark to think this gives me gain, IMO some will because of just how they are.

You will see some discussion on tRC as well in this thread by the two I mentioned, but also in Intel DDR5 thread.

My current DDR5 tuning "cheat sheet" is below.

tCl = Set as desire, can only be even.
tRCD = Set as desire, within AMD Overclocking menu separate tRCDWR and tRCDRD can be set, value is entered as hexadecimal.
tRP = Set as desire.
tRAS = tRC-tRP (JEDEC), tight tRCD+tRTP, only if tRC=tRCD+tRP+tRTP.
tRC = Higher tRCD+24+tRP+tRTP, middle >=tRCD+tRP+tRTP, lowest tRAS+tRP. See notes as tRCD+tRP+tRTP+2 maybe more optimal.
tWR = Lowest 48, multiple of 6.
tREFI = To be confirmed.
tRFC = Set as desire, see notes.
tRFC2 = To be confirmed.
tRFCsb = To be confirmed.
tRTP = Set as desire, lower than 12 unstable.
tRRDL = Lowest 8 (JEDEC).
tRRDS = Lowest 8 (JEDEC).
tFAW = Lowest 32, as rule is 4xtRRDS.
tWTRL = Lowest 16, as rule 4xtWTRS or 2xtRRDL.
tWTRS = Lowest 4, see notes as 4 maybe too tight.
tRDRDscl = Set as desire, match to tWRWRscl, lower than 4 unstable.
tRDRDsc = [Auto] is 1, lowering not possible.
tRDRDsd = Only relevant for dual rank, set as desire, match to tWRWRsd.
tRDRDdd = Only relevant for multi rank (4 DIMMs), set as desire, match to tWRWRdd.
tWRWRscl = Set as desire, match to tRDRDscl.
tWRWRsc = [Auto] is 1, lowering not possible.
tWRWRsd = Only relevant for dual rank, set as desire, match to tRDRDsd.
tWRWRdd = Only relevant for multi rank (4 DIMMs), set as desire, match to tRDRDdd.
tWRRD = To be confirmed.
tRDWR = To be confirmed.

tCWL = No setting, "Auto" rule make it tCL-2.

Notes:-

tRFC lowering value best gains, tRFC table from HardwareLUXX OP.
tREFI increasing value best gains.

tRC set to tRCD+tRP+tRTP seems too tight, as causes loss of mem speed in Kahru. Using tRCD+tRP+tRTP+2 seems optimal as gain mem speed in Kahru, which also means tRAS looser than tRCD+tRTP which is tight setting.

tWTRS set to 4 seems too tight, as causes loss of memspeed in Kahru. Using 6 or 8 seems optimal as gain mem speed in Kahru.

DRAM VDD = DRAM VDDQ = VDDIO (ideal for data integrity)

AMD help strings from UEFI AMD Overclocking menu, as this section is AMD FW area, it's AMD guidance.

tRDWR on Auto is unsynced between memory channel A and B.

If tPHYRDL unsynched between memory channel A and B, changing ARdPtrInitVal P0 Control can synchronise (9000 series). Do note help string in UEFI, need to confirm is syncing correct way forward, as perhaps one channel is closer tracing to CPU thus 1 tick higher is not incorrect with higher MEMCLK.

FCLK VDCI Mode Pref to Predictive can improve stabilty with increased FCLK.
 
#539 ·
A HUGE thank you @gupstergv2.0 - Your cheat sheet I currently have printed off infront of me and has been the basis for me getting my new build stable. I actually found it on the OCUK forums a while back and it helped me get 6400 stable and I only realised a few days ago you were on here also. Still learning DDR5 myself but your list really helped, plus I see alot of stuff we've discovered recently on here thanks to the clever folks on here!
tPHYRDL, FCLK VDCI etc.

I thought I had cracked CL28-37-37-49 at 1.435vdd, but finally found some errors quite late on in Karhu so back to my stable settings for now at CL30 at 1.4v which has survived everything i've thrown at it - p95 large fft, y cruncher FFT/FFTv4/VT3, TM5 absolut, Karhu and AIDA stress.

Technology Number Screenshot Software Computer hardware


I guess what i'm trying to understand is stuff like buildzoid's ez 6000 Hynix timings and he is using tRAS of 30 and tRC of 68 and I just wonder how that works... but like you said you can go lower... it's just if its stable or helps performance or not.
 
#540 · (Edited by Moderator)
@genelecs

No worries :) .

I see your running the Corsair 6000C28 kit. I had considered one of those to purchase, then decided against it as it had locked PMIC. I reckon your gonna need ~1.45V VDD/VDDQ for 6400C28, as that's what I'm seeing with my SK Hynix A Die, but as the PMIC is locked on your kit, it might not do it.

Ref this post, let's say JEDEC state 8 clock cycles for a particular timing parameter, the memory clock will be lower then what we are running, so as ns we have already improved on JEDEC rule. There are others aspects to memory timings, some are linked with one another.

Source quote link.

Now it is only important that always 4 Activates can be executed one after the other. The Four Activate Window (tFAW) describes how long the time window for 4 Activates remains open at least. So it makes sense to dimension this timing with at least 4 * Min (tRRD_S, tRRD_L). If 4 Activates would take longer than tFAW, the window will still remain open and tFAW will effectively be extended. The timing therefore only describes a minimum duration, with which the RAM bank groups can still be given a “breather” after 4 activates. However, this is not necessary for most modern RAM ICs and the formula tFAW = 4* Min (tRRD_S, tRRD_L) is completely sufficient.
Click to expand...
Below is 1:1 setups I've currently got as profiles, MCLK CL TRCD TRP TRAS TRC.

6000 28 35 35 49 84
6200 28 37 37 53 90
6400 28 38 38 58 96

Lets now look at them as ns.

6000 9.33 11.66 11.66 16.33 28
6200 9.03 11.93 11.93 17.09 29.03
6400 8.75 11.87 11.87 18.12 30

So far to me 6000C28 is the most optimal IMO. I maybe losing some on CL, but rest of the timings are better. Then voltages are also lower across the board for me. SOC is part of CPU power limits. I would think VDDIO and VDDP is also.

I haven't yet run the 9800X3D I have, but on 9600X (which has lower stock power limits). I have to either do CO/CS tweaks or increase CPU PPT, not to lose CPU boost clock, as SOC is increasing with memory clock.

6000C28 SOC 1.05V VDDP 0.925V
6200C28 SOC 1.1V VDDP 0.950V
6400C28 SOC 1.2V VDDP 1.05V.

On 9600X with CPU stock, but RAM 6200C28 needs very mild PPT boost to keep CPU boost, but 6400C28 needs larger/largest PPT boost.

@buildzoid is on OCN, in the past I have discussed GPU VBIOS mod with him on/off forum as I was heavily into it. Perhaps he'll chime in on how/why he sets timings as he does.
 
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