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Asus X670E Extreme

I still have serious boot instability on 2703 when running EXPO profiles. I can only boot on auto. I think I've had this issue since 25xx or 26xx.

If EXPO I or II is enabled, I get constant 4D errors on boot. It can take somewhere between 1-20 restarts to boot (once it boots, it's fine).

Any suggestions?
 
Asus X670E Extreme

I still have serious boot instability on 2703 when running EXPO profiles. I can only boot on auto. I think I've had this issue since 25xx or 26xx.

If EXPO I or II is enabled, I get constant 4D errors on boot. It can take somewhere between 1-20 restarts to boot (once it boots, it's fine).

Any suggestions?
If you haven't already, go into Tweaker's Paradise and enable the monitoring software reboot workaround.
 
Good News, after the Thunderbolt firmware update, my OWC Express 1M2 TB4 drive (AsMedia ASM2464PD Controller)
  • Now shows up in the Thunderbolt Control Center
  • Now shows connected at full 4x4 speed instead of legacy
  • Since being a Thunderbolt connection instead of just USB, it now shows up in Samsung Magician for firmware updates
 
I've got an X670E Hero on the latest 2702 beta bios and just got a 9800X3D and no matter what I do, in cinebench it doesn't boost above 5.25ghz, temps are below 80, power below all limits PBO enabled set to motherboard limits -35 CO and +200mhz override, something seems to be bugged but I got no idea what or where. Any ideas what it could be?
 
I've got an X670E Hero on the latest 2702 beta bios and just got a 9800X3D and no matter what I do, in cinebench it doesn't boost above 5.25ghz, temps are below 80, power below all limits PBO enabled set to motherboard limits -35 CO and +200mhz override, something seems to be bugged but I got no idea what or where. Any ideas what it could be?
Try UEFI 2703 beta, link.

As you have 9000 series UEFI 2703 with AEGSA 1.2.0.3a could well be better to use as has CPU SMU FW update for 9000 series (Granite Ridge), link.

I'm on TUF Gaming X670E Plus Wifi with 9600X, using a beta with AEGSA 1.2.0.3a, CO tweak with PBO +200MHz.

Software Font Graphics software Technology Multimedia Software

Software Graphics software Font Technology Multimedia Software

I also have a Crosshair X670E Hero, 9700X and 9800X3D, not used any of that kit as been busy with 9600X + TUF X670E.

I'm doing a massive test run of CB23 on various profiles to do a thread on per CO profile setting.

As even 9000 series is working like Zen3 on AM4, you'll see info what I mean here. Then couple years later in same thread others are looking into the single powerplane as stated by The Stilt to me in private discussion back in 2021 with 5900X and applied to 5800X3D in 2022, also did a 5700X3D CO that method.

You can cross reference The Stilt's reddit post with Skatterbencher AM5 voltage topology and see dLDO are again bypass mode on AM5 as on AM4. Also see this post by Martin Malik (Mumak on OCN), link.

See attached txt on some CO profiling I did on a 9600X using my VID harmonisation method based on The Stilt's original CO guidance on AM4.

Quote below has reference to 12 cores, as question to The Stilt back in 2021 was posed in regard to 5900X CO tweaking pointers.

Most people don't realize the so-called binding situation: In your case there are twelve cores and hence, potentially twelve different voltage request under load, yet only a single power plane. In order to prevent a binding situation from happening, find out which of the cores have the highest voltage request under the same workload. Once you have found it, start tuning this core and lower it's curve as much as you can. When you see that the effective VID is no longer decreasing, start again and find the core which holds it up.
 

Attachments

@safedisk, loaded the new 2703 bios, seems okay. One thing which I previously mentioned is when you load a profile under "Ai Overclock Tweaker" the voltages and trfc's are fixed to defaults regardless what you set. The only one that works is Auto. So if I load say Expo or Expo 2 and try and change vdd/q it will ignore and be set at 1.45v for both VDD/Q, this for manual as well. I dont know if other are experiencing the same. Auto seems to unlock for user input.
I can change frequency, voltages and timings running EXPO on 2703 with Gene board.

Technology Software Screenshot Video Game Software Operating system
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Technology Software Screenshot Video Game Software Computer
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Try UEFI 2703 beta, link.

As you have 9000 series UEFI 2703 with AEGSA 1.2.0.3a could well be better to use as has CPU SMU FW update for 9000 series (Granite Ridge), link.

I'm on TUF Gaming X670E Plus Wifi with 9600X, using a beta with AEGSA 1.2.0.3a, CO tweak with PBO +200MHz.



I also have a Crosshair X670E Hero, 9700X and 9800X3D, not used any of that kit as been busy with 9600X + TUF X670E.

I'm doing a massive test run of CB23 on various profiles to do a thread on per CO profile setting.

As even 9000 series is working like Zen3 on AM4, you'll see info what I mean here. Then couple years later in same thread others are looking into the single powerplane as stated by The Stilt to me in private discussion back in 2021 with 5900X and applied to 5800X3D in 2022, also did a 5700X3D CO that method.

You can crossreference The Stilt's reddit post with Skatterbencher AM5 voltage topology and see dLDO are again bypass mode on AM5 as on AM4. Also see this post my Martin Malik (Mumak on OCN), link.

See attached txt on some CO profiling I did on a 9600X using my VID harmonisation method based on The Stilt's original CO guidance on AM4.

Quote below has reference to 12 cores, as question to The Stilt back in 2021 was posed in regard to 5900X CO tweaking pointers.
Yes there is little benefit to tune CO individually with corecycler.

Under any moderately heavy mulitcore loads, the CO still apply the worse core VID to all cores. You can do -30 for 5 of 8 cores, but if your worst core is -5, you are fooked!

The thing is i dont understand why Amd and Intel are averse with enabling dLDOs for their desktop parts. I believe laptop chips can clock down individual cores, caches and even fclk uclk
 
Yes there is little benefit to tune CO individually with corecycler.

Under any moderately heavy mulitcore loads, the CO still apply the worse core VID to all cores. You can do -30 for 5 of 8 cores, but if your worst core is -5, you are fooked!

The thing is i dont understand why Amd and Intel are averse with enabling dLDOs for their desktop parts. I believe laptop chips can clock down individual cores, caches and even fclk uclk
Noob question;

How can i find out which are my good cores and the differences in voltage between them?
 
Yes there is little benefit to tune CO individually with corecycler.

Under any moderately heavy mulitcore loads, the CO still apply the worse core VID to all cores. You can do -30 for 5 of 8 cores, but if your worst core is -5, you are fooked!
I harmonize the VID ;) . You may have not got the process I do for per core CO, maybe I am not explaining it right.

I have done not one 5900X/5800X3D using my method, but quite a few, plus the 5700X3D and now 9600X. And I do do further tests, not only CoreCycler, just not reached that stage with 9600X.

Current 9600X CC run ZIP (~10hrs). Will continue testing with other test loads and report back :) .

The thing is i dont understand why Amd and Intel are averse with enabling dLDOs for their desktop parts. I believe laptop chips can clock down individual cores, caches and even fclk uclk
Yes I agree, odd.

I did see on Zen5, at defaults there are more states to FCLK & MEMCLK.

Software Electronic device Technology Number Screenshot

I don't know at what point when we tweak MEMCLK these states disappear and it just become one state (P0), not had time, been inclined to check.

But you can unsync states, I saw this as option in UEFI, again not had time, been inclined to explore this yet.

This is also why there are termination/ODT options with P0/P1/P2, to setup termination/ODT per state.
 
@dansi

Maybe this will make sense, maybe it won't.

Below is what I class as MAX CO per core tweak for my CPU.

2 cores have reached 50, as I said the process is gain MHz per core and lower/harmonize VID request.


Software Graphics software Font Technology Screenshot

This profile is highly unlikely to pass stability testing from what my past experience has been with CPUs. So then I globally roll back CO per core. The CO profile will still try to maximise per core clock, but VID has been increased and as harmonized all cores are on same VID.

Software Font Graphics software Technology Screenshot

Let's say above isn't stable in stability testing. I again can tick back globally again.

Software Graphics software Font Technology Screenshot

Some other screenies, so you can see clocks/VIDs, organise files in this ZIP by time.

Statuscore loading CPU, per core.
HWINFO, polling rate 250ms, Snapshot mode, average read.

ClockEff.ClockVIDSVI3
Core 0 (-36)5649MHz5663MHz1.328V1.338V
Core 1 (-25)5644MHz5655MHz1.327V1.335V
Core 2 (-33)5649MHz5664MHz1.328V1.339V
Core 3 (-22)5645MHz5658MHz1.330V1.338V
Core 4 (-45)5650MHz5666MHz1.326V1.336V
Core 5 (-45)5649MHz5662MHz1.332V1.340V
 
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@gupstergv2.0

Saw your RAM...highly recommend first OC RAM, after that CPU If needed
Thank you for viewing and commenting :) .

I have done RAM OC on my hardware, but only did that on it's own to see aspects of that.

Currently RAM OC is not applied as I am seeing and testing purely CPU CO tuning aspect.

Final stage I combine CPU CO tuning and RAM OC.

I just like to explore CPU and RAM OC separately and then combined.
 
@dansi

Maybe this will make sense, maybe it won't.

Below is what I class as MAX CO per core tweak for my CPU.

2 cores have reached 50, as I said the process is gain MHz per core and lower/harmonize VID request.



This profile is highly unlikely to pass stability testing from what my past experience has been with CPUs. So then I globally roll back CO per core. The CO profile will still try to maximise per core clock, but VID has been increased and as harmonized all cores are on same VID.


Let's say above isn't stable in stability testing. I again can tick back globally again.


Some other screenies, so you can see clocks/VIDs, organise files in this ZIP by time.
Maybe dual ccd chips wiil show it up easier. I think even Asus Shamino confirmed here before that the weakest VID/CO will take precedance at a moderately heavy all cores workload.

For dual ccd with a 3D ccd is even worse having single power plane and no dLDOs. Every one was praying X800 will have 2 power planes. Aida64 SHA3 seems to trip up 7000X3D -CO
 
Maybe dual ccd chips wiil show it up easier. I think even Asus Shamino confirmed here before that the weakest VID/CO will take precedance at a moderately heavy all cores workload.
No problem :) ,will have a look at that :) .

Only dual CCD CPU I have had were 5900X. The process I use to set per core CO, will in stability testing and my use cases pass. As always we can only test so much.

Even if I roll back CO globally, I never end up way back on core as -5 as you state here. What I've seen on several AM4 CPUs and 1x 9000 series, my best cores have lowest negative offset. As they tend to boost the most at stock and use least voltage. See also this post.

The highest rated cores (on a Ryzen 5000-series CPU) are the highest clocking ones, or ones that otherwise have the best overall characteristics in terms of silicon quality. While it is correct to expect that higher frequency generally equals higher voltage, it isn't just as simple as that.

Depending on the difference in the quality and the SIDD (static leakage) a higher clocking core can actually have lower voltage at higher frequency, than a weaker and potentially a bit less leaky core at lower voltage. In fact, it isn't even that uncommon, especially on Ryzen SKUs which use 2 CCD and of both which have slightly different characteristics and targets. However, it can just as happen within the same piece of silicon, depending on how "dramatic" the core-to-core differences are.

Sure, despite the CPU core (VDDCR_CPU) being shared across all of the cores, you can check the voltage of an individual core by executing a workload with manually set affinity. Workloads that manage affinity on their own, during the execution (e.g. Cinebench R15, R20, R23) won't work however, any normal workload will work. You can set the core affinity from the task manager, or by launching the application from the command prompt with "start /affinity 0x???? appname.exe" command. ???? being the affinity mask in hexadecimal (0x1 = core 1, 0x4 core 2, etc). Note that all of the other cores must be idling, or at least not loaded while you are doing this.
I've separated the VID data I posted here, into just stock and PBO +200MHz and hopefully you will see that.
 

Attachments

Yes there is little benefit to tune CO individually with corecycler.

Under any moderately heavy mulitcore loads, the CO still apply the worse core VID to all cores. You can do -30 for 5 of 8 cores, but if your worst core is -5, you are fooked!

The thing is i dont understand why Amd and Intel are averse with enabling dLDOs for their desktop parts. I believe laptop chips can clock down individual cores, caches and even fclk uclk
9800X3D behaves very strange TBH when trying to work out CO, it doesnt clock stretch like 7000 did, if the CO is too low on a core, the system just locks up.
 
Not what I was spcifically referring to, but anyway, try and adjust the voltages now in while you have the expo profile loaded.
Somehow after fiddling with "manual" I managed to adjust voltages, worked on the 3rd reboot
I started noticing on 2703 some of my binned 2X24GB M-die kits will not post, boot into Windows,.. getting amber light, code 15, pumps ramped up.. most kits only show the amber light, code 15 for a few seconds then changes to red light, then runs through all codes,.. I hear the pumps ramp down and system boots. I thought that was strange as these kits work fine on other BIOS.

After seeing your post about EXPO, issues,.. I decided to test EXPO on my system, normally I don't test EXPO,.. that's when I noticed the known good kits not booting. But others working fine, and I can make voltage, all other adjustments while running in EXPO,.. the not booting is strange.
 
question ... for the 2703 there's no renaming process ... is it ok to use it without renaming the bios CAP file ?
 
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