AMD DDR5 OC And 24/7 Daily Memory Stability Thread

ViTosS · Mar 1, 2025

6600Mhz seems a no go no matter what I do, error in like 5s on TM5, I was able to pass also 8200CL34.

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owikh84 · Mar 2, 2025

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owikh84 · Mar 2, 2025

8100 GDM off with A-die is more difficult than my M-die 2x24GB.
V-Class M-die ICs (Kingston Fury CUDIMM) is stronger than A-Class M-die ICs (V-Color Manta XFinity 8200).

TEAM Xtreem A-die 2x16GB: 8100 34-16-47-42-54-1T
VDD 1.57v | VDDQ 1.47v | VDDIO 1.45v | vSOC 1.15v | vMISC 1.10v | GDM on

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SunnyStefan · Mar 2, 2025

Here's where I'm at with my 2:1 48GB M-Die setup:

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Any suggestions on where to go from here? My gut is telling me that VSOC is too low, but I'm not seeing any improvements when increasing it.

I've tried many combinations of differing voltages but can't seem to get any of the following to work out:
❌ 2233MHz FCLK - Won't boot, seems to be a hard wall
❌ GDM Off - Produces errors 5 min into stress tests, even with super loose timings or wildly different VDD/VDDQ/VDDIO values

apav · Mar 2, 2025

Does 1.25v SOC sound about right for 6200MHz 2133 FCLK? Seems stable and Linpack doesn't have much variance, but I ask because I got 2067 stable at 1.24v and was erroring at 1.23v. I didn't even test 1.24v at 2133 yet because I just assumed it needed more voltage and 1.25v would be my starting point for testing. Is not that much extra voltage required to go from 2067 to 2133?

bradsm87 · Mar 2, 2025

apav said:
Does 1.25v SOC sound about right for 6200MHz 2133 FCLK? Seems stable and Linpack doesn't have much variance, but I ask because I got 2067 stable at 1.24v and was erroring at 1.23v. I didn't even test 1.24v at 2133 yet because I just assumed it needed more voltage and 1.25v would be my starting point for testing. Is not that much extra voltage required to go from 2067 to 2133?

FCLK generally favours less vSOC, not more. Also it isn’t worth only increasing FCLK by 67MHz and losing the 2:3 ratio to UCLK/MCLK. Leave at 2067 and enjoy 👍

httuner · Mar 2, 2025

apav said:
Does 1.25v SOC sound about right for 6200MHz 2133 FCLK? Seems stable and Linpack doesn't have much variance, but I ask because I got 2067 stable at 1.24v and was erroring at 1.23v. I didn't even test 1.24v at 2133 yet because I just assumed it needed more voltage and 1.25v would be my starting point for testing. Is not that much extra voltage required to go from 2067 to 2133?

Here is what I learn; you can stabilize higher FCLK by adjusting your VDDG CCD/IOD Voltages(Without the need to adjust SOC voltages; in fact lower helps with stabilizing it than higher); at .900mv on both VDDG CCD/IOD (Global) I can stabilize 2133 and even run 1.14v SOC with 6000/2133.

Bumping VDDG CCD/IOD to .950mv stabilizes 2200 FCLK for me and setting Ram speed to 6400MT/s I had to bump SOC voltages to 1.23 to stabilize it; settling for 6400/2200.

My findings where SOC voltage stabilizes higher UCLK due to running 1/1 but has a way of destabilizing FCLK; however adjusting VDDG voltages up will re-stabilze the FLCK. I don't have much knowledge on this really but after weeks of playing around with a variety of settings and headaches I came to this conclusion.

Bam_Bam · Mar 2, 2025

KedarWolf said:
My Team Group 8000MHz Xtreem are really well binned.

They are Intel, but I manually set everything anyways.

This passes KARHU.

View attachment 2699050

@all @anta777 @Veii :
Why is such a low tWR possible with Ryzen 9xxx?

Alexshunter · Mar 2, 2025

httuner said:
Here is what I learn; you can stabilize higher FCLK by adjusting your VDDG CCD/IOD Voltages(Without the need to adjust SOC voltages; in fact lower helps with stabilizing it than higher); at .900mv on both VDDG CCD/IOD (Global) I can stabilize 2133 and even run 1.14v SOC with 6000/2133.

Bumping VDDG CCD/IOD to .950mv stabilizes 2200 FCLK for me and setting Ram speed to 6400MT/s I had to bump SOC voltages to 1.23 to stabilize it; settling for 6400/2200.

My findings where SOC voltage stabilizes higher UCLK due to running 1/1 but has a way of destabilizing FCLK; however adjusting VDDG voltages up will re-stabilze the FLCK. I don't have much knowledge on this really but after weeks of playing around with a variety of settings and headaches I came to this conclusion.

I will experimenting now FCLK 2200MHz too, because SOTTR game seems gives more fps than with 2133MHz FCLK. How to know my FCLK is stable? Seems Linpack numbers are quite even but not perfectly.

bradsm87 · Mar 2, 2025

Alexshunter said:
I will experimenting now FCLK 2200MHz too, because SOTTR game seems gives more fps than with 2133MHz FCLK. How to know my FCLK is stable? Seems Linpack numbers are quite even but not perfectly.

Another easy thing to check is if it can boot into Windows at 2267, it’s very likely to be stable at 2200. Go 2 steps below max frequency that will boot into Windows.

Alexshunter · Mar 2, 2025

bradsm87 said:
Another easy thing to check is if it can boot into Windows at 2267, it’s very likely to be stable at 2200. Go 2 steps below max frequency that will boot into Windows.

Absolutely not, 2200MHz the top most it is booting.

bradsm87 · Mar 2, 2025

Alexshunter said:
Absolutely not, 2200MHz the top most it is booting.

The highest FCLK that boots can't be the highest that's stable. I'd stick to 2133 if the highest that boots is 2200.

Goose3080 · Mar 2, 2025

bradsm87 said:
The highest FCLK that boots can't be the highest that's stable. I'd stick to 2133 if the highest that boots is 2200.

If you can boot at 2200 then use it, theres no need to lower it unless its unstable, to test it, use Linpack extreme in safe mode with 10gb of ram selected, 20 passes, the gflops should be no more than 2 or 3 apart, if they are then its unstable, either then lower it or raise voltages, FCLK has an amazing built in error correction.

gupsterg · Mar 2, 2025

Follow up on post #26,193

System passed TM5 Extreme 9hrs, link.

Without PBO CO OC RAM/FCLK profile passed ~33k Kahru RAM Test, besides LinpackXtreme and other tests.

With PBO CO OC:-

~8hrs AIDA64 CPU FPU CACHE
~8hrs Y-Cruncher default Stress test (Required FCLK VDCI Predicative, VDDG CCD/IOD: 920mV)
~24hrs CoreCycler P95
~24hrs CoreCycler AIDA64 CPU FPU CACHE
~24hrs CoreCycler Y-Cruncher

~3hrs TM5 1usmus (Required VDDG CCD/IOD: 940mV)
~10hrs+ TM5 Absolute (7hrs test was tRDRDscl/tWRWRscl 8/8, 5/5 failed, 6/6 passed ~3hrs, so profile became 6/6)
~1hr OCCT CPU+RAM AVX2 Large Variable (only have free version so limited to 1hr run)
~8hrs+ TM5 3D (Required SOC bump of 0.01V, so became 1.135V)
~2hrs TM5 Extreme
~2hrs TM5 Heavy
~2hrs TM5 Intel
~8hrs TM5 1usmus (Dropped tRTP from 14 to 12, changed tRAS and tRC, 59/96 to 57/94)

From here system was WC

~8hrs TM5 3D
~4.5k% Kahru (Dropped tWR from 60 to 48)
~7hrs TM5 3D
~3hrs TM5 Absolute
~1.5hrs TM5 Extreme
rerun TM5 Extreme FAIL ~7.5hrs of 8.5hrs
~9hrs TM5 Extreme (Used SOC bump of 0.015V, so became 1.15V, may retest with slightly lower another day)

My take on TM5 Extreme run of 9hrs PASS needing higher SOC maybe down to more PCI-E HW in use on WC setup vs when setup was air cooled. When on air I was just using CPU/RAM/BOARD/HD 5850/MX500 1TB, now I got RX 7900 XTX/2xSN770 2TB/2x 870 EVO 4TB.

gupsterg · Mar 2, 2025

deehoC said:
Thanks for the share. I'm also running 1-2-0 with Swap APU. Our timings are fairly similar so I'm guessing something is unstable/not properly configured and I'm losing performance somehow, or your profile with GDM off and higher FCLK makes up the difference?

gupsterg said:

FCLK, I had some testing I can't find at present. I'll post some 2000-2233 setups.

Click to expand...

No Swap APU used, Nitro as in screen shots, settings as in txt, I only change FCLK. You can see FCLK 2233MHz at 45/60min isn't raising test speed like at 15/30 and lower FCLK tests, so crapping out.

9800X3D Kahru RAM Test FCLK 2000 to 2233 testing ZIP. Will add to OP of my thread soon.

FCLK 2233 on WC is more stable then when I was on air cooling. Before LinpackXtreme just error before 1st run complete. Now I do get 2 runs, then freezes.

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luxcro said:
Is it worth lowering ARdPtrInitVal even if my phys are matched? Auto (3) 35/35, 1 and 2 35/35, 0 33/35. In this case is it worth lowering to 1, aida and pyprime showed no improvements between 1 and 3, maybe some training benefits?

Not in my opinion, just leave Auto as tPHYRDL matches. Auto as 3 should technically be better training/stability then 1 or 2.

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SunnyStefan said:
Here's where I'm at with my 2:1 48GB M-Die setup:

View attachment 2699104

View attachment 2699110

View attachment 2699106

Any suggestions on where to go from here? My gut is telling me that VSOC is too low, but I'm not seeing any improvements when increasing it.

I've tried many combinations of differing voltages but can't seem to get any of the following to work out:
❌ 2233MHz FCLK - Won't boot, seems to be a hard wall
❌ GDM Off - Produces errors 5 min into stress tests, even with super loose timings or wildly different VDD/VDDQ/VDDIO values

From your table of testing you seem to be passing CPU tests with that FCLK/MEMCLK setup, so I don't see a reason to bump SOC yet.

You could try tRDWR 15, tWRRD 1, lowering tWTRS/L. Any of those are not going to give big gains, so your choice.

Andy1981 · Mar 2, 2025

anamolydetected😉 said:
Looking good... time to dial in the secondaries?

what do you think about this:

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main difference, the one you were referring to
was nitro 1/2/1, mine is 1/2/0

Saiger0 · Mar 2, 2025

@gupsterg
Thanks for the comprehensive write up. Good to know how useful the FCLK VDCI setting seems to be, free stability and no drawback (so far).
My other takeaway is that SLC at 4/4 or 5/5 might be too low even for 6200 and 6/6 is a safe go-to.
Have you tried 5/9 or 5/17 yb any chance? Although with seeing some guys running wrwrscl at 1 this setting might really be irrelevant on amd.

Andy1981 · Mar 2, 2025

Alexshunter said:
I will experimenting now FCLK 2200MHz too, because SOTTR game seems gives more fps than with 2133MHz FCLK. How to know my FCLK is stable? Seems Linpack numbers are quite even but not perfectly.

here is my setting:

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and here is my linpack in save mode:

gupsterg · Mar 2, 2025

Saiger0 said:
@gupsterg
Thanks for the comprehensive write up. Good to know how useful the FCLK VDCI settings seems to be, free stability and no drawback (so far).

No worries

.

Saiger0 said:
My other takeaway is that SLC at 4/4 or 5/5 might be too low even for 6200 and 6/6 is a safe go-to.
Have you tried 5/9 or 5/17 yb any chance? Although with seeing some guys running wrwrscl at 1 this setting might really be irrelevant on amd.

Scl 4/4 was showing a gain in test speed of Kahru vs looser if I remember correctly, 5/9 I have not used. 5/17 I have, if I remember correctly was slightly slower in test speed of Kahru vs 4/4 or even 6/6. Due to time constraint I didn't use other benchmarks.

My plan has been to get max stability testing done first on most tuned 6200C28 1:1 GDM: on profile. I am nearing the end of any further timings tweaks I can do to profile plus stability testing, as I think it is high stability.

So my next step is to try differing Nitro/Bank Swap APU. As my AM5 setup now has GPU that may show gains from timings in games, I will try games as well usual synthetic RAM benchmarks. I will loosen timings on profile as well and test, but will keep same PBO CO/FCLK/MEMCLK.

Yes I have seen some running tWRWRSCL as 1. Watch Buildzoids video from about here , then just here he talks about tWRWRscl at 1. To me I think we need tool that show what we set vs what IMC uses as value. Then as Buildzoid says some of those values crash on Intel, but not on AMD, so what is AMD IMC doing!?

Some tests just end up being run to run variance and unclear if get gain or not from x memory timing tweak.

Buildzoid in his video also say he asked AMD concerning some timings and got no answer. Any I thought who may have some inside knowledge also gave no answer.

PhilipFry · Mar 2, 2025

Veii said:
Legacy.
RRD_ & WTR_ are not CCD_
CCD_L is expected to be 12 & CCD_L_WR(2) is expected to be 24.
By side-effects SC_L change can affect CCD_ ,
but if it's no boot then it didnt change or reached minimum floor allowed.

Optimally they are kept the same length, for transitional purposes
RRD/WTR _L & CCD (WR) _L

Veii said:
BL16
RD-X-X-X-X-X-X 2nd-BC8 start
WTR_S 4
X-X-X-X WR-X-X-X / X-X-X-X X-X-X-X
NOP-NOP-NOP-WR NOP-NOP-NOP-NOP-NOP-NOP-NOP-NOP WR & Timebreak ++ RD Start
3 ticks & WR (4th) + BURST (8) end & WR
4+8 = 12

RD every start of BC8
8+8 ~ 16
RD BL = 16
CCD_ , 8
CCD_L roundtrip, 8+8 = start at 16th tick or called "first".
But AMD ~ 12
RR = 16-24 (same DIMM 32-48)
WW = 12-16 same DIMM, short 3-4nCK
WRWR SameChip_Long = roundtrip 🤭
SameChip_Short = 1nCK

Some interesting reading the last few days! thanks @Veii and @anta777 for the posts. If you have time can you let me know if I am on the right track here? Changed my rtp and ras based on the discussions, as well as changed wrwrscl from 17 to 12 after reading the above. Seems more consistent in testing now, maybe slightly less performance, but that could just be an illusion from the run to run variation tightening up.

Veii said:
^
With tWTR_S 4 usage ~ _WW = 12nCK
It's CCD_L_WR 12/18/24 on CWL 2 gap or 24/32 on CWL 4
But 16 works

With 5 to 8 tWTR_S ~ _WW is 16nCK
16/24 on tCWL 2 & 32 on CWL 4
12 can't work
24 min can work if CWL is gap of 2-3.

tWTR_S 3, _WW is 11+AL
12 can work.

2Rx8, wants tCWL gap of 4
& 24/32 min
Requires tWTR_S 6.
==================================
CWL gap 2
CCD_L 12/16,
_WR = 24/32, and 36/48
^ 1/2/3x allowed

CWL gap of 4
_WR = 48/64
^ 4x required
Required on 2R, 1R up to (board) electrical design.
Doesn't really scale on 1Rx8. Does a lot on 2R & default on Gear4.

Will depend on Controller.
Will depend on Gearmode, but 4x doesnt work well
1x and 2x is default, 3x is extended on Gap of 2.

Does this apply to me though? specifically the part about 2Rx8 wanting a cwl-cl gap of 4? Mine is hard set at 2, and cant be changed so not sure how to apply that? My Dimms are dual rank 16gb sticks (kinda unusual)

Appreciate any input, have a good weekend! 🍻

AMD DDR5 OC And 24/7 Daily Memory Stability Thread

ViTosS

owikh84

owikh84

SunnyStefan

apav

bradsm87

httuner

Bam_Bam

Alexshunter

bradsm87

Alexshunter

bradsm87

Goose3080

gupsterg

gupsterg

Andy1981

Saiger0

Andy1981

gupsterg

PhilipFry

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