Here is what I gathered so far......

Intel RC ACPI Settings

PTID Support

it's a power/monitoring chip so as an OEM you could get your own and feed in data to the BIOS/EC in order to control the system.

Allows to enable\disable proprietary temperature and voltage monitoring device PTID, which essentially drops one of the SSDT tables called PtidDevc from the BIOS if you set to disable this feature.

BDAT Table

CPU Flex Ratio Override

PECI

Intel Trusted Execution Technology

FCLK Frequency

FCLK = some sort of BUS between PCI-E and CPU, 1Ghz is the default when using premas bios, i asked him about that about 1 year ago, on the P775DM3 i never checked but i would guess that's 1ghz already too. Here is a good article about it, back then at release when 800mhz was still forced due to a bug.

Race To Halt RTH

Race to halt is the concept of boosting a workload quickly in order to sleep quickly (AKA race to sleep)

HDC Control

Energy Efficient P-State

Energy Efficient Turbo

VR Mailbox Command Options

CPU Lock Configuration

IMON Scaling Support

WDT Enable

XTU Interface

vBoost Enable

RSR

about RSR it's Residency State Regulation, don't count me on that but i think it's some sort of protection that the voltage doesn't bounce too dangerous levels when trying real high voltages, like for me when i tried the 4.9Ghz 5.0Ghz runs, the stock bios decided to limit it to max 1.38-1.4v so i never could get 5.0ghz validation stable, HWinfo then reported that RSR was the Throttling reason and my ratio got limit to max x41

Residency State Regulation (RSR)
Allows you to determine whether to automatically lower the CPU turbo ratio if the CPU voltage/temperature
is too high. source

Uncore

Above 4GB MemoryMappedIO BIOS Assignment

X2 APIC Opt Out

 

I believe you might have found the answers since but here is a few from your list:

HDC aka (Hardware Duty Cycling)
Intel processors may contain support for Hardware Duty Cycling (HDC), which enables the processor to autonomously force its components inside the physical package into idle state. For example, the processor may selectively force only the processor cores into an idle state. HDC is disabled by default on processors that support it. System software can dynamically enable or disable HDC to force one or more components into an idle state or wake up those components previously forced into an idle state. Forced Idling (and waking up) of multiple components in a physical package can be done with one WRMSR to a packaged scope MSR from any logical processor within the same package.
Source:
http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-3b-part-2-manual.pdf

Energy Efficient P-State
Processor Performance Power States
Known as Enhanced Intel SpeedStep®
Technology (EIST) or
 Demand Based Switching (DBS)
 Based on CPU utilization the P-states
reduce the electrical power consumption,
whereas the processor executes code
 P-states are a combination of processor
voltage and processor frequency
 P-states can be compared with various
performance levels
source:
https://sp.ts.fujitsu.com/dmsp/Publications/public/wp-haswell-bios-settings-primergy-ww-en.pdf

Hope this helps.