Nice scores and temps! Direct Die?

Do you see voltage scaling past -30?

 

Oh no, it's just an ordinary 360 AIO liquid cooler. Due to the HTFMax, the CB23 score basically only depends on the temperature. When I turn the room air conditioner to the coldest setting, CB23 can reach 47.6K (normal mode) and 47.7K (safe mode).

Sorry I don't quite understand your second question. Do you mean whether there is a voltage change when the CO value exceeds -30? As the CO value continues to deepen, the voltage will naturally decrease after the core reaches the fmax frequency.

 

I didn't even realize the 9950X3D had an HTFmax limit (below 95C anyway), though I did know it was a feature of the 9950X.

Is that HTFmax limit on both the v-cache CCX and the non-vcache one, or only on the latter?

The absolute values of most CO values in this set are higher than those obtained by the voltage alignment method. Therefore, I had an interesting idea: why not merge the two sets of CO values? For each core, use the CO value with a higher absolute value from the two methods.

The overriding reason not to do this is that if you're at a deeper negative CO than what you tested to be stable you could compromise stability.

 

I didn't even realize the 9950X3D had an HTFmax limit (below 95C anyway), though I did know it was a feature of the 9950X.

Is that HTFmax limit on both the v-cache CCX and the non-vcache one, or only on the latter?



The overriding reason not to do this is that if you're at a deeper negative CO than what you tested to be stable you could compromise stability.

I didn't even realize the 9950X3D had an HTFmax limit (below 95C anyway), though I did know it was a feature of the 9950X.

Is that HTFmax limit on both the v-cache CCX and the non-vcache one, or only on the latter?

I obtained a multiplier limit formula for the 9950X3D:
R = -0.0025×T² + 0.0625×T + 60.125.
For example, when T = 60°C, R is approximately 55, at which point the maximum frequency of CCD0 is 5.5 GHz and that of CCD1 is 5.7 GHz. Similarly, when T = 50°C, R = 57, with the maximum frequency of CCD0 being 5.7 GHz and that of CCD1 being 5.9 GHz.

So I know a overclocking method is to adjust the eCLK to 111.7 and lower the Fmax by 400. In this case, the maximum frequency of CCD0 is calculated as: 5550 - 400 = 5150, and 5150 × 1.117 = 5752.22 (MHz). The corresponding HTFMax temperature limit for the 5150 MHz frequency is approximately 73.4°C. However, this method requires high CO and CS values. From my experience, although the effective frequency can reach 5.75/5.95 GHz under idle and light loads, the actual frequency can only be maintained at around 5.6 GHz in medium-to-heavy load scenarios, and stability is poor.

The overriding reason not to do this is that if you're at a deeper negative CO than what you tested to be stable you could compromise stability.

Sorry I didn't clarify this sufficiently.
The two sets of CO values I merged have both undergone stability verification: one is the limit CO values for each core tested via CoreCycler (Set A), and the other is the CO values obtained through voltage alignment (Set B). I then took the CO value with the larger absolute value for each core from the two Sets to form a new collection of CO values (Set C). Currently, Set C operates stably, and its scores in CB23 and CPU Profile are identical to those of Set B—both, of course, outperform Set A.

 

Incorrect response, but I don't know how to delete the post.

 

I'm eager to hear everyone's thoughts and look forward to your responses.

I am trying to understand your results. I noticed that the max CPU PPT and voltage is much higher for your third run (230W to 260W), but the CO values are lower and the score is slightly worse. I also do not see any indication of 'combining' the two sets. e.g. core 8 has the CO values -37, -28, and -35 in the three runs. Why not just use the CO values from run 2? You get the best performance at the lowest power with them.

My quick test:

My guess is that although most CO values in Set A seem more ideal, the failure to "pull the voltage to a flat plane" affects Core 6 and Core 3, causing them to fail the CoreCycler test.

Don't you break the voltage synergy if you change the values from those discovered while using that method? How would using the lower values from the CoreCycler method be beneficial? It does not seem to help based on your benchmark results.

 

I am trying to understand your results. I noticed that the max CPU PPT and voltage is much higher for your third run (230W to 260W), but the CO values are lower and the score is slightly worse. I also do not see any indication of 'combining' the two sets. e.g. core 8 has the CO values -37, -28, and -35 in the three runs. Why not just use the CO values from run 2? You get the best performance at the lowest power with them.

My quick test:
View attachment 2716704



Don't you break the voltage synergy if you change the values from those discovered while using that method? How would using the lower values from the CoreCycler method be beneficial? It does not seem to help based on your benchmark results.

Oh, I'm very sorry. The CO values used in the third test were the ones I had been using for a long time. After completing the stability test, I increased the CO of all cores by +2 to ensure long-term stability and saved the results in the BIOS configuration file. During this test, I only loaded the file and forgot to globally set CO to -2. I retested, and the results didn't differ much.
My personal view is that the core with the highest voltage does determine the performance under multi-core loads, so aligning the voltages and then globally reducing the CO values is a better approach.

 

The previous reply was incorrect and has been edited.

 

@broken Frost Imprisonment

Sorry been offline for few days, had been playing with my own HW.

Glad the thread helped and great to read a result on dual ccd CPU, enjoy your HW!

I'm really curious to know if there's any significance to per-core negative voltage that's more extreme than voltage alignment？ The only thing I can think of is that it might result in lower standby power consumption and temperatures. I'm eager to hear everyone's thoughts and look forward to your responses.

In regard to "lower standby power consumption and temperatures" I don't think you can improve that. If you use Ryzen Master you will see cores "Sleep" at idle/low loads.

Spoiler